JPS6144430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital communication system using optical fiber or coaxial cable. In particular, it relates to a system for searching for faults in repeaters from a distance in a digital signal relay transmission system using CMI codes. CMI (Coded Mark Inversion) here
A code is a binary code with a clock frequency of ₂₀ , in which the marks of the input binary code sequence with a clock frequency of 0 are alternately code-converted to ``11'' or ``00'', and the spaces are also code-converted to `` ₀₁ ''. say.

FIG. 1 is a diagram showing an example of the configuration of a conventional system of this type. PNG1 is a pseudo-random code sequence generator in which the clock frequency is ₀ but the mark rate is not equal to 1/2.
occurs. RASG is a relay point designation signal generator and generates a relay point designation signal RAS. The relay point designation signal RAS is a square wave signal with a cycle of Tc (=1/c) and a mark period and a space period are equal. EXOR is an exclusive OR circuit, MC is a polynomial multiplication circuit [X+1] at a clock frequency of ₀ , CMICOD is a CMI code converter, S is a transmission code sequence, LINE is a relay transmission line, and R is a reception code sequence. In the repeater, DEC is a discriminator, DR is an identification output code sequence, CMIDEC is a CMI code inverter, and DC is a
This is a CMI decoding code sequence. DC1 is a polynomial division circuit of 1/X+1 at a clock frequency of ₀ , D is a division output code sequence,
BPF is a bandpass filter tuned to c, and B is a transfer signal, which is transmitted to an intervening pair or another communication system.

FIG. 2 is a waveform diagram of CMI code conversion. IN indicates the input code sequence, and OUT indicates the output code sequence.
The CMI code converter CMICO converts the mark of the input binary code sequence to "11" or "00" alternately,
The space of the input binary code sequence is code-converted to "01}.The CMI code inverse converter CMIDEC performs the code conversion opposite to that of the CMI code converter CMICOD.

Figure 3 is a block diagram of the polynomial multiplier circuit MC, in which EXOR is an exclusive OR circuit, and DL1 is T ₀ (=
This is a delay circuit with a delay time of _1/0 ).
The polynomial multiplication circuit MC is a circuit that performs an exclusive OR of the current input code and the input code 1 bit before the current time to produce an output code.

FIG. 4 is a block diagram of the polynomial division circuit DC1, in which EXOR and DL1 are the same parts with the same symbols in FIG. Polynomial division circuit
DC1 is a circuit that calculates the exclusive OR of the output code one bit before the current time and the input code at the current time to obtain an output code. Polynomial division circuit like this
For details on the operation of DC1, see for example the document W.
As described in "Error-Cerrecting Codes" by W. Peterson, a detailed explanation will be omitted here, but each time a mark is input as an input code, a phase inversion occurs in the output code.

FIG. 5 is a block diagram for explaining the operation of the transmission system shown in FIG. 1 in a simplified manner. A discriminator code error pulse is input to the terminal T1, and a CMI code inverse converter code error pulse is input to the terminal T2.

Now, in the transmission system shown in Figure 1, the code error occurring in the discriminator DEC and the CMI code inverter CMIDEC
If the code errors that occur in the CMI decoded code sequence DO occur with a time lag, both of these code errors appear as code errors in the CMI decoded code sequence DO at the time when each code error occurs. On the other hand, if a code error occurring in the discriminator DEC and a code error occurring in the CMI code inverse converter CMIDEC occur at the same time, the two code errors are canceled out and do not appear as code errors in the CMI decoding code sequence DO. . That is, the discriminator
Code errors occurring in DEC and CMI code inverse converter
The output of the exclusive OR operation with the code error that occurs in CMIDEC becomes the equivalent code error included in the CMI decoding code series DO, so regarding code errors, the transmission system in Figure 1 and the transmission system in Figure 5 is equivalent to

The transmission system in Figure 5 has a mark rate at the transmitter.
A pseudo-random code sequence that is not equal to 1/2 is modulated with a relay point designation signal of period Tc, thereby adding a single frequency component of frequency c to the spectrum of the output code sequence D of polynomial division circuit DC1 in the repeater. If a discriminator DC code error occurs, the phase of the single frequency component is reversed to search for a faulty repeater that has generated a code error. The details of the operation of the transmission system in Figure 5 are as follows:
Literature “Journal of Electronics and Communication Engineers of Japan J59―A.11.p.961
(1976), so a detailed explanation will be omitted here.

As explained above, the conventional system equivalently has the configuration shown in FIG. 5 regarding code errors, but
The actual configuration is shown in FIG. Since it is necessary to incorporate the complicated CMI code inverse converter CMIDEC into the repeater, the repeater configuration is complicated. Furthermore, as mentioned above, the discriminator DEC
Code errors occurring in CMI code inverse converter
Since the output of the exclusive OR operation with the code error occurring in CMIDEC becomes equivalently the code error included in the CMI decoded code series DO, it becomes possible to separate and detect both code errors. Therefore, although the discriminator DEC does not generate a code error and the repeater main signal system operates normally, a code error occurs in the CMI code inverter CMIDEC, so the band A phase reversal may occur in a single frequency component of the output of the repeater BPF, and the repeater may be determined to be a faulty repeater. Also the discriminator DEC and CMI
If code errors occur at the same time in the code inverse converter CMIDEC, both code errors cancel each other out, and the repeater may not be determined to be a faulty repeater even though a fault has occurred. As described above, the conventional system has the disadvantage that the repeater configuration is complicated and that highly accurate fault detection is not possible.

The present invention eliminates these drawbacks and provides a fault search method that eliminates the need for a complex CMI code inverter built into the repeater and can perform repeater fault search with high accuracy. The purpose is to

The present invention controls the number of consecutive spaces of a pseudorandom code sequence to be an even number in a transmitter, converts it into a CMI code sequence, and performs an exclusive OR operation on this CMI code sequence and a relay point designation pulse. It is characterized in that a transmission code sequence is created using a repeater, and a polynomial division of 1/X+1 is performed at a clock frequency of ₂₀ in a repeater.

Next, the present invention will be explained in more detail using examples.

FIG. 6 is a block diagram of an embodiment of the present invention.
PNG is a pseudo-random code sequence generator,
Generate a pseudorandom code sequence PN. ZCC is a space continuation number control circuit that counts the number of consecutive spaces in an input code sequence, creates a binary code sequence in which the number of consecutive spaces is controlled to be an even number, and converts the binary code sequence into a CMI It is supplied to the CMI code converter CMICOD as a conversion input sequence CI.
CMI code converter CMICOD is a CMI conversion input series
Perform CMI code conversion on CI and CMI conversion output series
Create a CO.

The relay point designated pulse generator RAPG has a constant cycle
A relay point designation pulse RAP having a 1-bit mark is generated every Tc/2. exclusive OR circuit
EXOR is CMI conversion series CO and relay point designation pulse
An exclusive OR operation with RAP is executed to create a transmission code sequence S. This transmission code sequence S is transmitted through the relay transmission path LINE.

In the repeater, first, the received code sequence R is passed through a discriminator.
It is supplied to the DEC to obtain the identification output code sequence DR. Next, this identification output code sequence DR is converted to the polynomial division circuit DC
A polynomial division of 1/X+1 is performed at a clock frequency of ₂₀ to create a divided output code sequence D, which is converted into a band wave by a band waver BPF to create a transfer signal B. This transfer signal is sent to another communication system such as an intervening pair, and is monitored by a monitoring station not shown.

FIG. 7 is a block diagram of the polynomial division circuit DC, where EXOR is an exclusive OR circuit and DL is T ₀ /2 (=
This is a delay circuit with a delay time of 1/2 ₀ ). The divider circuit DC performs a polynomial division of 1/X+1 at a clock frequency of ₂₀ .

FIG. 8 shows an example of the configuration of the continuous space number control circuit ZCC. EXOR1 is an exclusive OR circuit, DL2,
DL3 is a delay circuit each having a delay time of T ₀ (=1/ ₀ ). INV is a complementary code conversion circuit,
OR is an OR circuit, AND1 and AND2 are AND circuits, and TFF is a trigger flip-flop circuit. MHD is a continuous mark head detection circuit,
The starting point of consecutive marks in input signal A is detected. C is an output signal, W is a space continuation number control signal, and LK is a clock signal with a frequency of ₀ .

The input signal A is branched into three branches and supplied to the first input of the exclusive OR circuit EXOR1, the input of the delay circuit DL2, and the input of the continuous mark head detection circuit MHD. The input signal A input to the delay circuit DL2 is delayed by _T0 to become a signal E, and further converted into a complementary code by a complementary code converter INV to become a signal G. This signal G is supplied to the second input of the OR circuit OR. The first input of the logical sum circuit OR is
A signal Y obtained by delaying the space continuation control signal W by _T0 by the delay circuit DL3 is input. The output signal H of the OR circuit OR is supplied to the first input of the AND circuit AND1, and the output signal H of the AND circuit AND1 is supplied to the second input of the AND circuit AND1.
The clock signal supplied to the input of the clock signal is ANDed with CLK to become the RZ (Return to Zero) signal U.

This RZ signal U is a trigger flip-flop circuit.
Supplied to TFF. The trigger flip flip circuit TFF is a circuit in which the phase of the output signal is inverted every time a pulse of "1" is input as the input RZ signal U. Therefore, when the number of "1" pulses included in the RZ signal U is an even number, the phase of the output signal V is the same as the state before the RZ signal U is input; When the number of "1" pulses included in the RZ signal is an odd number, the phase of the output signal V is inverted with respect to the state before the RZ signal U is input. Trigger flip-flop circuit
The output signal V of TFF is supplied to the first input of the logical sum circuit AND2, and the second input of the logical product circuit AND2
A logical AND operation is performed with the mark continuous mark head detection output Q supplied to the input of , and a continuous space number control signal W is obtained. The space continuation number control signal W is supplied to the second input of the exclusive OR circuit EXOR1, and as described above, the exclusive logic with the input signal A supplied to the first input of the exclusive OR circuit EXOR1 is established. A sum operation is performed to obtain an output signal C.

First, the operation of the consecutive space number control circuit ZCC will be explained. FIG. 9 shows an example of operating waveforms of the space continuation number continuation circuit ZCC shown in FIG. Consider a case where the input signal A is as illustrated in FIG. 9A. OD・
SP indicates a continuation of an odd number of spaces, and EV/SP indicates a continuation of an even number of spaces. At this time, if there is no space continuation control signal W, the output signal H of the OR circuit OR will be as shown by the solid line in FIG. 9H. Therefore, the output signal U of the AND circuit AND1 is as shown by the solid line in FIG. 9U, and the output signal V of the trigger flip-flop circuit TFF is as shown by the solid line in FIG. There is. Assuming that the output signal V of the trigger flip-flop TFF is initially "0" as shown in FIG. 9V, when the number of consecutive spaces of the input signal A is an odd number (OD SP),
The output signal V of the trigger flip-flop circuit TFF becomes "1" at the mark point immediately after the continuous space period of the input signal A, that is, at the point in time when the continuous mark head detection output Q becomes "1".

Therefore, at the time of the mark immediately after the space continuity period (OD SP) consisting of an odd number of consecutive spaces in the input signal A, the space continuity control signal W
becomes "1". Therefore, the output signal C, which is the AND output of the space continuation number control signal W and the input signal A, changes as shown by the broken line in FIG. 9C. That is, the mark immediately after the space continuous period (OD/SP) consisting of the odd number of consecutive spaces is converted into a space, and the number of consecutive spaces is controlled to be an even number.

Next, the space continuation number control signal W is controlled by a delay circuit.
The signal Y is delayed by T ₀ by DL3 and is supplied to the first input of the OR circuit OR. Therefore, the output signal H of the OR circuit OR changes as shown by the broken line in FIG. 9H. Logical product circuit AND1
The output signal U changes as shown by the broken line in FIG. 9U. As a result, the triggered flip-flop circuit
As shown by the broken line of the 9th V, the output signal V of TFF is converted to "0" at the time T ₀ after the period corresponding to the continuous space period (OD SP) consisting of an odd number of consecutive spaces in the input signal A. and prepares for the arrival of the next new space continuous period of input signal A.

On the other hand, when the output signal V of the trigger flip-flop circuit TFF is initially "0" and the number of consecutive spaces of the input signal A is an even number (EV SP)
is the space continuous period (EV・
At the mark point immediately after SP), the output signal V of the trigger flip-flop circuit TFF becomes "0".
Therefore, at the time of the mark immediately after the space continuous period (EV/SP) consisting of an even number of consecutive spaces in the input signal A, the space continuous control signal W becomes "0".
It is. Therefore, input signal A is output as output signal C as it is.

Figure 10 shows the continuous mark head detection circuit in Figure 5.
This is an example of MHP configuration. DL4 is a delay circuit with a delay time of T ₀ , EXOR2 is an exclusive OR circuit,
AND3 is a logical product circuit.

Input signal A is branched into three branches, each with a delay circuit.
Input of DL4, first of exclusive OR circuit EXOR2
is supplied to the first input of the AND circuit AND3. The output signal F of the delay circuit DL4 is supplied to the second input of the exclusive OR circuit EXOR2,
A signal Z is obtained by performing an exclusive OR operation with the input signal A. This signal Z is applied to the AND circuit.
It is supplied to the second input of AND3, and subjected to an AND operation with input signal A to become output signal Q.

Next, the operation of the continuous mark head detection circuit MHD will be explained. FIG. 11 is a diagram showing an example of operating waveforms of the continuous mark head detection circuit MHD shown in FIG. 10.
When the input signal A is as shown in FIG. 11A, the output signal F of the delay circuit DL4 is as shown in FIG. 11F. Therefore, the output signal Z of the exclusive OR circuit EXORZ becomes "1" at the beginning of the continuous space period and the beginning of the continuous mark period, as shown in FIG. 11Z. Therefore,
Exclusive OR circuit EXOR2 with OR circuit AND3
By performing an AND operation on the output signal Z of and the input signal A, only the portion corresponding to the beginning of the mark continuation period is selected among the "1"s of the output signal Z of the exclusive OR circuit EXOR2, A continuous mark head detection output Q is obtained as shown in FIG. 11Q.

As explained above, in the embodiment system of the present invention shown in FIG.
The number of consecutive spaces in the output code sequence C is controlled so that it is always an even number.

Next, the overall operation of the present invention will be explained. FIG. 12 is a diagram showing an example of operation waveforms when there is no relay point designation pulse RAP in the embodiment system of the present invention shown in FIG. In Figure 12, the pseudorandom code sequence
Regardless of whether the number of consecutive spaces in PN is odd or even, the number of consecutive spaces in CMI conversion input series CI is always controlled to be an even number as described above.

In Figure 12, the CMI conversion output series is CO, mark continuous reaction blocks (MB, IMB) corresponding to the mark continuous period of the CMI conversion input series CI, and space continuous response blocks (MB, IMB) corresponding to the space continuous period of the CMI conversion input series CI. (SB). MB is a block that supports continuous marks excluding isolated marks, IMB is a block that supports isolated marks, SB
indicates a continuous space correspondence block.

As shown in Figure 2 before, the CMI conversion output series
In CO, the CMI conversion input series CI mark is converted to "11" or "00" alternately, and the CMI conversion input series
CI spaces are converted to "01". In the CMI conversion output series CO, the marks in the continuous mark correspondence block always appear as 2-bit pairs in the form of "11", so the number of marks is an even number.

In the continuous space period of the CMI conversion input series CI, the number of consecutive spaces is controlled to be an even number as described above, so in the CMI conversion output series, the number of marks in the continuous space corresponding block (SB) is still an even number. It is. That is, in the CMI conversion output series CO, the number of marks in the block corresponding to continuous marks and the number of marks in the block corresponding to continuous spaces (SB) are always even numbers.

This kind of CMI conversion output series CO is used as a relay transmission line.
It is transmitted through LINE and becomes the received code sequence R, which is identified by the discriminator DEC and becomes the identified output code sequence.
DR, which is then input to the polynomial division circuit DC. As described above, the polynomial division circuit DC causes a phase inversion in the output code every time a mark is input as the input code. Therefore, if there is no code error in the discriminator DEC, the last bit of each block in the division output code sequence D is always either "1" or always "0". , does not change as the block progresses.

In the division output code sequence D, when the final bit of each block is "1", it is a positive mode, and when the final bit of each block is "0", it is a negative mode, then the sign patterns of the positive and negative modes are mutually exclusive. has a complementary sign pattern. Therefore, if the mark rate in the block (MB) corresponding to consecutive marks in the division output code sequence D in the case of positive mode is α, then the mark rate in this block corresponding to consecutive marks in the division output code sequence D in the case of negative mode is α. The rate is (1-α).

As shown in FIG. 12D, the mark rate in the block (MB) corresponding to consecutive marks in the division output code sequence D is the same as when the number of consecutive marks is 1 (CM
1 is not equal to 1/2 except when the input sequence is an isolated mark). That is, in general, α≠1/2, except for isolated mark compatible blocks (IMB). On the other hand, the mark rate in the space continuation corresponding block (SB) in the division output code sequence D is 1/2 regardless of whether the mode is positive or negative, as shown in FIG. 12D. Next, if the sum of the block lengths of the continuous mark corresponding blocks (MB) excluding the isolated mark corresponding block (IMB) occupies a proportion of r in the entire division output code sequence D, then the space continuous corresponding blocks (SB) and relaxation of the block length of the isolated mark corresponding block (IMB), the division output sequence D
The proportion in the whole is (1-r). As described above, the CMI conversion input sequence CI is a pseudo-random code sequence PN in which the number of consecutive spaces is controlled to be an even number, and since there is always a continuous period of marks that are not isolated marks, the value of r is not equal to 0.

From the above, the overall mark rate of the division output code sequence D is m ₁ in equation (1) in the positive mode, and m ₁ in equation (2) in the negative mode.

m ₁ = αr + 1/2 (1-r) (1) m ₂ = (1-α) r + 1/2 (1-r) (2) However, α is the block corresponding to consecutive marks (MB) excluding the block corresponding to isolated marks. This is the mark rate within. Furthermore, from equations (1) and (2), m ₁ +m ₂ =1 (3) is always satisfied.

When formula (1) is transformed, m ₁ = 1/2 + (α - 1/2) r (4) However, as mentioned above, in general, for continuous mark corresponding blocks (MB) excluding isolated mark corresponding blocks, α is not equal to 1/2 and r
is not equal to 0, so m ₁ in equation (4) is not equal to 1/2. That is, m ₁ in equation (1) is not equal to 1/2.
Furthermore, referring to equation (3), it can be seen that m ₂ in equation (2) is also not equal to 1/2.

From the above, it can be concluded that if there is no relay point designation pulse RAP and there is no code error in the discriminator DEC, the overall mark rate of the divided output code sequence D is not equal to 1/2.

FIG. 13 is an explanatory diagram of the effect of using the relay point designation pulse. FIG. 13a shows the case where there is no relay point designation pulse, and FIG. 13b shows the case where there is a relay point designation pulse.

The operation when a pulse sequence having a 1-bit mark with a period Tc/2 (=1/2c) as shown in FIG. 13b is used as the relay point specifying pulse RAP will be described. The relay point designation pulse RAP
When using, as shown in FIG. 13b, every time the relay point designation pulse RAP is input, the divided output code sequence D undergoes a phase inversion and is converted into a complementary code sequence. Therefore, since the mark D of the division output code sequence alternately switches between m ₁ of equation (1) and m 2 of equation (2) at the time interval of Tc/ ₂ , the division output code sequence D has a frequency c It has the following components. If this component of frequency c is extracted by the bandpass filter BPF shown in FIG. 6 and transferred to the monitoring station, the monitoring station can receive the sine wave signal of frequency c.

Next, if a code error occurs in the discriminator DEC, the divided output code sequence D is converted into a complementary code after the code error occurs, as shown in FIG. Therefore, since the phase of the transfer signal B changes, by detecting this phase change, a code error in the repeater can be detected, and a faulty repeater can be identified with high accuracy.

The above explanation has been about a configuration in which the frequency c component included in the division output code sequence D is extracted and transferred by the bandpass filter BPF tuned to this frequency c, as shown in FIG. vessel
The present invention can be implemented in the same way by a configuration in which the component of the frequency c extracted by the BPF is further modulated with another frequency _l and transferred.As explained above, according to the present invention, the CMI In code transmission, code errors in a repeater can be detected with high accuracy by simply providing a very simple circuit in the repeater. The system of the present invention has the advantage that searching for faulty repeaters and remote measuring repeater code errors in a relay transmission system using CMI codes can be realized extremely easily and with high accuracy.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional system. FIG. 2 is a diagram showing a waveform diagram of CMI code conversion. Figure 3 is a polynomial multiplication circuit
MC configuration diagram. FIG. 4 is a configuration diagram of a conventional polynomial division circuit DC1. FIG. 5 is a simplified block diagram for explaining the operation of the transmission system of FIG. 1. FIG. 6 is a configuration diagram of an embodiment system of the present invention. FIG. 7 is a configuration diagram of a polynomial division circuit DC in an embodiment of the present invention. 8th
The figure shows the configuration of the space continuous control circuit. Figure 9 is an operating waveform diagram of the space continuous control circuit ZCC. FIG. 10 is a configuration diagram of the continuous mark head detection circuit MHD. 1st
Figure 1 is an example of the operation waveforms of the continuous mark head detection circuit MHD. FIG. 12 is a diagram showing an example of operation waveforms when there is no relay point designation pulse in the embodiment of the present invention. FIG. 13 is an explanatory diagram of the effect of using a relay point designation pulse. 14th
The figure is an explanatory diagram of the error detection operation according to the embodiment of the present invention. PNG1, PNG...pseudo-random code sequence generator, PN1, PN...pseudo-random code sequence, RASG
…Relay point designation signal generator, RAS…Relay point designation signal, EXOR, EXOR1, EXOR2…Exclusive OR circuit, MC…Polynomial multiplication circuit, CMICOD…CMI code converter, S…Transmission code series, LINE…Relay transmission R...Received code string, DEC...Discriminator, DR...Discrimination output code sequence, CMIDEC...CMI code inverse converter,
DC...CMI decoding code series, DC1, DC...polynomial division circuit, D...divider output code series, BPF...bandwidth wave generator, B...transfer signal, DL1, DL2, DL3, DL
4, DL...delay circuit, ZCC...space continuation number control circuit, CI...CMI conversion input series, RAPG...relay point specification pulse generator, RAP...relay point specification pulse, INV
...Complementary code conversion circuit, OR...Order circuit, AND1,
AND2, AND3...AND circuit, TFF...Trigger flip-flop circuit, MHD...Continuous mark head detection circuit, A...Continuous space number control circuit input signal,
C... Space continuation number control circuit output signal, E... Delay circuit DL2 output signal, G... Complementary code conversion circuit output signal, H... OR circuit output signal, CLK... Clock signal, U... AND circuit AND1 output signal, V ...Trigger flip-flop output signal, W...Continuous space number control signal, Y...Delay circuit DL3 output signal, Q
...Continuous mark head detection output, F...Delay circuit DL4
Output signal, Z...exclusive OR circuit EXOR2 output signal.

Claims (1)

[Claims] 1. The marks of the binary code series with a clock frequency of ₀ are code-converted alternately to "11" or "00", and the spaces of the binary code series are code-converted to "01", and the clock frequency is _20. In a fault search method for a digital transmission relay system that includes means for creating a CMI code sequence of means for performing CMI code conversion on the output signal of this means; means for performing exclusive OR of the output signal of this means and a repeater designation pulse periodically having a 1-bit mark; _means for transmitting the output of means for extracting a signal with a cycle twice the mark generation cycle of the repeater specified pulse from the signal obtained from the output of the repeater, and means for transmitting the output of this means to the monitoring station, A failure detection method for a digital transmission relay system, comprising: means for detecting a phase reversal of an output signal of a transmitting means.