JPS6145310B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a magnetic bubble memory.

A control device is essential when assembling magnetic bubble chips into a memory device, and reducing the cost of this part is an important key for magnetic bubble memory to compete with semiconductor memory. However, the currently mainstream major-minor loop type chips require the generation of complex drive timing pulses. There are various major-minor loop systems, but their operation will be explained here using the magnetic bubble chip configuration of the major-minor loop system shown in FIG. minor·
Loop 1 and major loop 2 are circular shift registers. The minor loop 1 stores data depending on the presence or absence of bubbles, and addresses are assigned to arrays (bubble patterns) indicating the presence or absence of bubbles at the same bit position in a plurality of minor loops 1.

The bubble pattern moves through a minor loop and a major loop in synchronization with the rotating magnetic field.

To access data at a certain address, move the bubble pattern of that address stored on minor loop 1 to transfer gate 3, operate transfer gate 3, and then
Transfer onto loop 2. Next, it moves on the measurer loop 2 and guides it to the detector 4, eraser 5, and generator 6, performs detection, erasure, and generation a prescribed number of times, and then moves on the measurer loop 2 to the transfer gate 3.

Finally, transfer gate 3 is operated to transfer the data to minor loop 1. At this time, the chip is configured so that the address to which the data on minor loop 1 is transferred is the address from which the original data was extracted.

First, transfer gate 3 is operated to transfer data from minor loop 1 to major loop 2, detection, erasure, and generation are performed on major loop 2, and data on major loop 2 is transferred to transfer gate 3. The operation from operation to storage in minor loop 1 is defined as major operation.

In order to control such operations, conventionally, as described in Japanese Patent Publication No. 7329/1983, a second counter is used to count the number of bits in the minor loop, and a second counter is used to count the number of bits in the major loop. 2
A third counter was provided to count the time positions of magnetic bubble splitting, erasure, detection, generation, etc. Of these, the second and third counters are necessary for the measurer operation. However, counters are relatively expensive compared to other ICs, and
However, the use of more than one circuit is an obstacle to reducing the cost of the control circuit. There is also a problem in terms of miniaturization.

An object of the present invention is to solve the above-mentioned conventional problems and provide a small and inexpensive magnetic bubble memory control device.

The present invention compares an address register holding an externally requested address with a counter synchronized with the movement of bubble data, and the contents of the address register and the counter, generates a match signal, and resets the counter. a first comparator, a flip-flop set by the coincidence signal and masking the coincidence signal; and a flip-flop activated by the flip-flop, which compares each timing of the measure operation of the counter and the bubble. and a second comparator that resets the flip-flop and loads the requested address held in the address register into the counter by a signal that coincides with the end timing of the measurer operation, and a measurer output from this comparator. This is a magnetic bubble memory control device consisting of a flip-flip group that is set or reset by a signal that coincides with each operation timing and outputs each major operation signal.

The present invention will be explained in detail below using the drawings.

FIG. 2 shows an embodiment of the present invention. The three conventional counters are here replaced by only one counter 8. This counter 8 operates as a conventional first counter except during the major operation, and its contents change by 1 in synchronization with the rotating magnetic field, and the address (internal address). When the first comparator 9 detects a match between the contents of the counter 8 and the address set in the address register 7 (externally requested address), the match output is passed through the gate to the magnetic bubble drive circuit. 12
added to. Then, the magnetic bubble drive circuit 12
operates the transfer gate 3 and transfers data from the minor loop 1 to the major loop 2.

At the same time, this coincidence output resets the counter 8 to 0, making it ready for use as a counter for a measurer operation.

The output of the first comparator 9 then sets the flip-flop 10 to the high state.
The period when the output of flip-flop 10 is high is the period of the measurer operation in which data is present on the measurer loop. During the measure operation, flip-flop 10 activates second comparator 11. At this time, counter 8
counts the period since the data was transferred to measurer loop 2. One embodiment of the second comparator 11 corresponds to each cycle of the measurer operation, that is, the start and end cycle of the detector 4, the start and end cycle of the eraser 5, the start and end cycle of the generator,
Then, the measurer operation is completed and the transfer gate 3
It is composed of a plurality of comparators that compare the operating period of the counter 8 with the contents of the counter 8 and output a match signal.

Another embodiment of the second comparator 11 decodes the output of the counter 8 and outputs a plurality of coincidence signals respectively when the output of the counter 8 reaches each cycle of the measure operation and the end period of the measure operation. It consists of a decoder with an output.

Each coincidence signal of the second comparator 11 is input to a flip-flop group 13, which is set and reset. The output of this flip-flop group 13 is input to a magnetic bubble drive circuit 12, which controls the generation of drive pulses.

Among the coincidence signals of the second comparator 11, the coincidence signal of the end period of the major operation is applied to the magnetic bubble drive circuit 12, which operates the transfer gate 3 to transfer data from the major loop 2 to the minor loop 1. At the same time, it is input to the counter 8,
Counter 8 is loaded with the contents of address register 7, which is also input to flip-flop 10, which is reset to a low state.

As a result, the contents of the counter 8 come to indicate the address of the data passing through the bit position close to the transfer gate 3, and the next access can be accepted.

In this way, all the control of the magnetic bubble chip is achieved with only one counter 8, and a small-sized magnetic bubble control device can be easily constructed at a low cost.

In the embodiments in this text, a case is described in which a major-minor loop type chip using a transfer gate is used. Conventionally, there have been chips that use rebricator-type gates that transfer data by duplicating it from a minor loop to a major loop when reading. When using such a chip, the measuring operation during reading is assumed to end immediately after all the data on the measuring loop has passed through the detector, and the value obtained by subtracting a certain number from address register 7 is stored in counter 8. May be set. Although the value of the address register 7 may be set in the counter 8 at the same timing as shown in the embodiment, the time required to complete reading increases.

Variations of the chip configuration shown in Figure 1 include a chip with two major loops for a set of multiple minor loops, a chip that performs detection after duplicating the data on the major loops, and a chip with two major loops.
There are chips that include minor loop units. The control device of the present invention can be realized using any major-minor-loop type chip, and the above description does not limit the scope of the present invention.

Address information given from the outside may include information for selecting a chip or information for selecting information transferred to the major loop, in addition to the address within the chip (internal address).
In this case, address register 7 in FIG. 2 must be interpreted as representing a portion holding internal addresses.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a major-minor loop type magnetic bubble chip, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Minor loop, 2... Major loop, 3... Transfer gate, 4... Detector, 5...
Eraser, 6... Generator, 7... Address register, 8... Counter, 9, 11... Comparator, 10
...Flip-flop, 12...Magnetic bubble drive circuit, 13...Flip-flop group.

Claims (1)

[Claims] 1. An address register that holds an externally requested address, a counter that is synchronized with the movement of pable data, and a first device that compares the contents of the address register and the counter, generates a match signal, and resets the counter. a comparator, a flip-flop which is set by the coincidence signal and masks the coincidence signal; and a flip-flop activated by the flip-flop, which compares the counter with each timing of the measure operation of the bubble, and performs a measure operation. a second comparator that resets the flip-flop and loads the requested address held in the address register into the counter by a signal that coincides with the end timing of the second comparator; and each timing of the measurer operation output from this comparator. 1. A magnetic bubble control device comprising a group of flip-flops which are set and reset by a matching signal of the flip-flops and which output respective measurer operation signals.