JPS6145391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a novel structure in which the combination of an insulating substrate and the internal structure of a transistor is devised. Therefore, the base-collector junction capacitance is small and high-speed switching is possible. High performance and high performance, such as when it is used in the order of emitter, base, and collector from the surface, and when it is used in the reverse order (hereinafter referred to as a reverse transistor) as a bidirectional transistor. The present invention relates to a semiconductor device having multiple functions and a method for manufacturing the same.

Conventional semiconductor devices of this type have a structure in which a base surrounds an emitter formed on the surface of a semiconductor crystal, and a collector surrounds the base, as an extension of the concept of isolation between pn junction elements. That is, the areas increase in the order of emitter, base, and collector (or vice versa when used as a reverse transistor, as in the case of IIL). This is because it was necessary to separate the base and the substrate at the collector region. Furthermore, because each region is expanded isotropically through a process such as normal diffusion, such a structure is inevitably required. Therefore, when looking at the planar structure,
The planar size of the base is larger than the planar size of the emitter, and the planar size of the collector is also larger than this. Therefore, the entire lower surface of the base is in contact with the collector (or emitter in the case of a reverse transistor). Therefore, the base-collector junction area becomes large, and the junction capacitance at this portion increases.

In addition, conventionally, the collector region constituting a transistor is connected to a semiconductor (single crystal) through a PN junction.
Since it is connected to the substrate, the collector of the transistor has a large parasitic capacitance due to the PN junction. These parasitic capacitances become a major obstacle in increasing the operating speed of the circuit when forming a circuit using these transistors. Furthermore, when the emitter and collector of this transistor are replaced and used as a reverse transistor, the emitter-base junction extends outward more than the base-collector junction, so the emitter injection efficiency deteriorates and the transistor cannot be used properly. It also had the drawback of not being able to provide the desired characteristics.

Also, JP-A-49-38592 and JP-A-50-
Publication No. 784 discloses a structure in which a semiconductor region as a collector region of a transistor, a semiconductor region as a base region, and a semiconductor region as an emitter region are formed in a semiconductor single crystal layer formed on an insulating plate. An integrated semiconductor circuit device having an integrated semiconductor circuit device is shown.

According to such a configuration, since the semiconductor region serving as the collector region is formed on the insulating plate,
There is no large parasitic capacitance at the collector of the transistor.

However, since the entire lower surface of the semiconductor region serving as the base region is connected to the semiconductor region serving as the collector region, it has the same drawbacks as the conventional integrated semiconductor circuit device described above.

The present invention aims to provide a semiconductor device having a novel transistor structure that overcomes the above-mentioned conventional drawbacks, and a method for manufacturing the same.

The structural feature of the semiconductor device disclosed in the present invention is that an insulating substrate is used, and the collector (or emitter in the case of a reverse transistor) interposed between the insulating substrate and the base region is polar; The point is that the base and substrate may be in direct contact without a collector (or emitter). Therefore, a structure in which the base area is larger than the collector (or emitter) is also possible, so that part of the lower surface of the base is connected to the collector, and the other part of the lower surface of the base is not connected to the collector, and The basic feature is that it is connected to the insulating plate.

The details of the present invention will be explained below using the drawings.

1 to 3 show a first embodiment of a semiconductor device according to the present invention, and FIG. 1 is a plan view of a semiconductor device (transistor) having the structure of the present invention,
Figures 2 and 3 are Y-Y in Figure 1, respectively.
It is a sectional view taken along the line XX.

That is, a semiconductor single crystal layer 2 formed on an insulating plate 1 made of silicon oxide, for example, is used, and within the semiconductor single crystal layer 2, for example, an N-type layer is locally connected to the insulating plate 1 side. A semiconductor region 3 is formed locally.

As is clear from FIGS. 2 and 3, the first semiconductor region has a rectangular cross-sectional shape in one direction, and an L-shaped cross-sectional shape in the other direction perpendicular to this. A collector (or emitter in the case of a reverse transistor) electrode 13 is formed in an L-shape, passing through a second semiconductor region 4 to be described later, and extending onto the upper surface of the single crystal 2.

Furthermore, a P-type semiconductor region 4 is formed in the semiconductor single crystal layer 2 so as to surround the semiconductor region 3 and to be connected to the top and side surfaces of the semiconductor region 3 and to the insulating plate 1 .

Further, in the semiconductor single crystal layer 2, at a position facing the semiconductor region 3 on the side opposite to the insulating plate 1 side, an N-type semiconductor region 5 connected to the semiconductor region 4 and separated from the semiconductor region 3 is provided. is formed locally.

Thus, an NPN type transistor Q is constructed in which the semiconductor regions 3, 4, and 5 are respectively used as a collector (emitter in the case of a reverse transistor) region, a base region, and an emitter (collector in the case of a reverse transistor) region.

Note that the semiconductor regions 4 and 5 also have a base electrode 14 and an emitter (collector in the case of a reverse transistor) electrode 1 on the upper surface of the single crystal layer 2, respectively.
5 is attached.

The effect obtained by such a structure is that, first of all, the entire lower surface of the base region is not connected to the collector region, so the area of the PN junction between the collector region and the base region is Compared to conventional integrated semiconductor circuit devices,
It can be made small enough. Therefore, the base-collector junction capacitance of the transistor Q can be reduced. When the transistor is used as a switch with its emitter grounded, for example, the amount of feedback between the collector and emitter can be reduced, and the input impedance and switching speed can be greatly improved. Second, when using the semiconductor regions 3, 4 and 5 as an inverted transistor in which the emitter region, base region and collector region are respectively used,
It is possible to improve the emitter injection efficiency and increase the current amplification factor. This is because in the conventional structure, if the collector is used as the emitter of a reverse transistor, the junction area with the base will be larger than the part where the emitter and collector are closely facing each other, and the current injected from there will not operate as a transistor. This is because, on the other hand, the structure of the present invention is reduced to this extra area.

That is, in the present invention, the semiconductor region 4 as the base region is connected to surround the semiconductor region 3 as the emitter region in this case, and is also connected to the insulating plate 1, so that the lower surface of the base region Since the entire area is not connected to the emitter region, the emitter junction area in this case can be made smaller than that when the conventional transistor described above is used as a reverse transistor. Impurity concentration of semiconductor region 3 and semiconductor region 4 as a base region in this case
The ratio of the impurity concentration to the impurity concentration can easily be made larger than that when the above-described conventional transistor is used as an inverse transistor.

Therefore, the reverse transistor in this case can operate with greater emitter injection efficiency than when the conventional transistor described above is used as the reverse transistor. In this way, the transistor can be used in both directions.

Such effects were only made possible by a combination of the insulating substrate and the internal structure of the transistor. The above is the first embodiment of the semiconductor device of the present invention. Such a semiconductor device can be manufactured by the manufacturing method of the embodiment shown in FIG. 4, as described below.

That is, as shown in FIG. 4A, an N-type semiconductor single crystal layer 2a is formed on the insulating plate 1.

Next, by locally diffusing N-type impurities from above into this N-type semiconductor single crystal layer 2a,
As shown in FIG. 4B, a highly doped N-type region 3a having a depth reaching the insulating plate 1 from the upper surface of the semiconductor single crystal layer 2a is formed.

Next, as shown in FIG. 4C, an N-type semiconductor single crystal layer 2b is formed on the semiconductor single crystal layer 2a in which such a region 3a is formed, for example, by an epitaxial growth method. At the time, within this layer 2b,
A highly doped N-type region 3b is formed by diffusion of N-type impurities from the region 3a.

Next, by diffusing P-type impurities from above into the regions 3a and 3b of the N-type semiconductor single crystal layer 2b and the regions surrounding them,
As shown in FIG. 4D, a P-type semiconductor region 4a having a depth reaching the insulating plate 1 is formed, and at this time, the region 3a
and 3b are formed in N-type regions 3c and 3d with diluted N-type impurity concentrations due to the diffusion of P-type impurities at this time.

Next, the N-type impurity is locally diffused into the P-type semiconductor region 4a from above, as shown in FIG.
As shown in FIG. 3, an N-type region 3e having a depth reaching region 3d is formed.

Next, or before that, by diffusing N-type impurities into the P-type semiconductor region 4a from above,
As shown in FIG. 4F, an N-type region 5 is formed.

Next, as shown in FIG. 4G, conductive layers 13a, 14a and 15a are ohmicly applied to N-type region 3e, P-type region 4a and N-type region 5a, respectively.

By the above method, the N-type regions 3c, 3d, and 3e are formed into the semiconductor region 3, the P-type region 4a into the semiconductor region 4, the N-type region 5a into the semiconductor region 5, and the conductivity type layer 13.
a, 14a and 15a are electrodes 13 and 14, respectively.
and 15, the semiconductor device shown in FIGS. 1 to 3 can be manufactured.

Next, the structure of a semiconductor device according to a second embodiment of the present invention will be explained.

In the transistors described in FIGS. 1, 2, and 3, in the case of a circuit configuration in which the third semiconductor region 5 is used as a collector, a PN junction between the collector and the base is formed between the semiconductor and the metal electrode. It is possible to replace it with a Schottky junction. The structure in that case is shown in FIGS. 5, 6, and 7.

FIG. 5 is a plan view of a second embodiment of the semiconductor device (transistor) of the present invention, and FIGS. 6 and 7 are views taken from the Y'-Y' cross section and the X'-X' cross section in FIG. 5, respectively. FIG.

In the present invention, good characteristics can be obtained when used as a reverse transistor in which the emitter is formed deep when viewed from the surface and the collector is formed on the surface side, so there is value in using a Schottky junction for the collector junction. That is, when a Schottky junction is used on the collector side, there is an advantage that injection efficiency is increased, the transistor is not saturated, the base charge is small, and the speed can be further increased.

As a manufacturing technique for forming such a transistor, step 1 is used instead of step F in the embodiment shown in FIG.
A step of forming a metal electrode on the surface of the second semiconductor region in the upper layer film-like semiconductor single crystal facing the semiconductor region 3 of , and forming a Schottky junction between the metal electrode and the second semiconductor region by heat treatment. This can be achieved by inserting .

The above description merely shows a few examples of the present invention, and without departing from the spirit of the present invention,
Various modifications and changes may be made.

[Brief explanation of the drawing]

1, 2, and 3 are a schematic plan view showing a first embodiment of a semiconductor device according to the present invention, a cross-sectional view taken along the line Y-Y, and a cross-sectional view taken along the line X-X of FIG. FIG. FIG. 4 is a process diagram for explaining the first embodiment of the method for manufacturing a semiconductor device according to the present invention, and is a schematic cross-sectional view corresponding to FIGS. 2 and 3. FIG. 5, 6, and 7 are a schematic plan view showing a second embodiment of the semiconductor device according to the present invention, a cross-sectional view taken along the line Y'-Y', and FIG.
FIG. 3 is a sectional view taken along the line X′-X′. 1... Insulating plate, 2... Semiconductor crystal, 3, 4, 5
... Semiconductor region, 19 ... Conductive layer, 13,1
4,15...electrode.

Claims (1)

[Claims] 1. Using a semiconductor single crystal layer formed on an insulating plate, in the semiconductor single crystal layer, a first semiconductor region having a first conductivity type; reverse second
a second semiconductor region having a conductivity type and a third semiconductor region having a first conductivity type, the first semiconductor region being locally formed on the insulating plate side in connection therewith; the second semiconductor region is connected to an upper surface and a side surface of the first semiconductor region so as to surround the first semiconductor region,
A portion of the second semiconductor region is also connected to the first semiconductor region, and the other portion of the bottom surface is connected to the first semiconductor region. It has a configuration in which it is not connected to the semiconductor region and is connected to the insulating plate, and the third semiconductor region is located at a position opposite to the first semiconductor region on the opposite side to the insulating plate,
The first semiconductor region is formed to be connected to the second semiconductor region, and the first semiconductor region has an L-shaped cross section, and a portion of the first semiconductor region passes through the second semiconductor region onto the upper surface of the single crystal. A transistor that extends and includes the first semiconductor region, the second semiconductor region, and the third semiconductor region, and has them as a collector region, a base region, and an emitter region, respectively; A reverse transistor is configured as a region, and an electrode is connected to the third semiconductor region, and an electrode is connected to the first semiconductor region.
1. A semiconductor device characterized in that an electrode is formed in connection with an end of a semiconductor region having an L-shaped cross section and extending toward a surface. 2. Using a semiconductor single crystal layer formed on an insulating plate, in the semiconductor single crystal layer, a first semiconductor region having a first conductivity type and a second semiconductor region having a first conductivity type opposite to the first conductivity type are provided.
A second semiconductor region having a conductivity type of The first semiconductor region is connected to the top and side surfaces of the first semiconductor region so as to surround the semiconductor region, and is connected to the insulating plate, so that a part of the bottom surface of the second semiconductor region is connected to the first semiconductor region. The other part of the lower surface is not connected to the first semiconductor region and is connected to the insulating plate, and the insulating plate is connected to the second semiconductor region. a conductive layer is applied to form a shot barrier junction with the second semiconductor region at a position facing the plurality of first semiconductor regions on the side opposite to the first semiconductor region; , an inverse transistor is configured that includes the second semiconductor region and the conductive layer and uses them as an emitter region, a base region, and a collector region, respectively, and the first semiconductor region has an L-shaped cross section. and a portion thereof extends through the second semiconductor region onto the upper surface of the single crystal, and an electrode is formed in connection with the end portion extending to the surface. Semiconductor equipment. 3. A step of forming a lower film-like semiconductor single crystal layer on an insulating substrate, a step of forming a first semiconductor region having a locally high impurity concentration of a first conductivity type in the film, and a step of forming the lower layer. an upper film-like semiconductor single-crystal layer is formed in contact with the film-like semiconductor single-crystal layer, and a second conductivity type opposite to the first conductivity type is formed in the same layer in contact with the first semiconductor region. and introducing an impurity forming a first conductivity type into the second semiconductor region from the surface through the second semiconductor region,
A method of manufacturing a semiconductor device, comprising at least the step of forming a third semiconductor region opposite to the first semiconductor region. 4. A step of forming a lower film-like semiconductor single crystal layer on an insulating substrate, a step of forming a first semiconductor region locally having a high impurity concentration of the first conductivity type in the film, and a step of forming the lower layer. forming an upper film-like semiconductor single-crystal layer in contact with the film-like semiconductor single-crystal layer;
and a first semiconductor region in contact with the first semiconductor region in the same layer.
forming a second semiconductor region having a second conductivity type opposite to that of the first semiconductor region through the second semiconductor region on the surface of the upper film-like semiconductor single crystal layer; A method of manufacturing a semiconductor device, comprising at least the step of forming a conductive layer that forms a Schottky junction with the second semiconductor region at a position facing the semiconductor region.