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JPS6145785B2 - - Google Patents
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JPS6145785B2 - - Google Patents

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Publication number
JPS6145785B2
JPS6145785B2 JP53076024A JP7602478A JPS6145785B2 JP S6145785 B2 JPS6145785 B2 JP S6145785B2 JP 53076024 A JP53076024 A JP 53076024A JP 7602478 A JP7602478 A JP 7602478A JP S6145785 B2 JPS6145785 B2 JP S6145785B2
Authority
JP
Japan
Prior art keywords
wiring
fet
common line
resistance value
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53076024A
Other languages
Japanese (ja)
Other versions
JPS552956A (en
Inventor
Fumio Takahashi
Kimio Inagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7602478A priority Critical patent/JPS552956A/en
Publication of JPS552956A publication Critical patent/JPS552956A/en
Publication of JPS6145785B2 publication Critical patent/JPS6145785B2/ja
Granted legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Description

【発明の詳細な説明】 本発明は電子装置等における布線の良否を自動
的かつ高速に検査する布線検査装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring inspection device that automatically and quickly inspects the quality of wiring in electronic devices and the like.

従来布線検査装置において各布線端子の切替え
を行なうための素子としてリレー、SCR等が多
く用いられていた。しかし近年電子装置等の布線
量は極めて多くなつてきており数万本におよぶこ
とも少なくなく、リレー、SCR等では動作速
度、消費電力、占有スペース等の点で大容量の布
線検査装置の切替素子としては適当でない。そこ
で電界効果トランジスタ(以下、FETと略す)
を切替素子として採用した装置が開発されている
が、リレー等に比較してON抵抗値が数百Ωと大
きい上にばらつきも大きいため信頼性が充分でな
かつた。
Conventionally, relays, SCRs, and the like have often been used as elements for switching each wiring terminal in wiring inspection equipment. However, in recent years, the amount of wiring in electronic devices has become extremely large, often reaching tens of thousands of wires, and relays, SCRs, etc. are not suitable for large-capacity wiring inspection equipment in terms of operating speed, power consumption, and space they occupy. It is not suitable as a switching element. Therefore, field effect transistor (hereinafter abbreviated as FET)
Devices have been developed that use the switching element as a switching element, but the ON resistance value is several hundred ohms, which is large compared to relays, etc., and the variation is also large, so the reliability is not sufficient.

本発明の目的は上述の欠点を除去するとともに
布線検査を自動的かつ高速に行ないうる布線検査
装置を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a wiring inspection device that eliminates the above-mentioned drawbacks and can perform wiring inspection automatically and at high speed.

本発明によれば各布線端子をそれぞれ第1共通
線に接続する第1FET群と、前記各布線端子をそ
れぞれ第2共通線に接続する第2FET群と、基準
布線端子を前記第1共通線に接続する第1のリレ
ーと、前記基準布線端子を前記第2共通線に接続
する第2のリレーと、前記第1および第2FET群
の任意のFETと第1および第2リレーを選択し
開閉する手段とを有する選択部と、前記第1共通
線に電圧を供給する電源と、前記第2共通線の電
圧を感知し抵抗値を計算し出力する検出部と、前
記第1および第2FET群の各FETのON抵抗値を
記憶する記憶部と、前記選択部を制御し前記検出
部の出力と前記記憶部の情報により布線状態を検
査し外部に出力する制御部とよりなる自動布線検
査装置が得られる。
According to the present invention, a first FET group connects each wiring terminal to the first common line, a second FET group connects each of the wiring terminals to the second common line, and a reference wiring terminal connects the first FET group to the first common line. a first relay that connects to a common line, a second relay that connects the reference wiring terminal to the second common line, and any FET of the first and second FET groups and the first and second relays. a selection section having a means for selecting and opening/closing; a power source that supplies voltage to the first common line; a detection section that senses the voltage of the second common line and calculates and outputs a resistance value; It consists of a storage section that stores the ON resistance value of each FET of the second FET group, and a control section that controls the selection section, inspects the wiring state based on the output of the detection section and the information of the storage section, and outputs it to the outside. An automatic wiring inspection device is obtained.

図は本発明の一実施例を示すブロツク図で、被
検査装置1は布線端子P1,P2,P3,と基準布線端
子P4を有し、P1,P3が布線でつながり回路2を形
成している。FET S11,S12,S13は第1FET群を
形成し、FET S21,S22,S23は第2FET群を形成
している。第1FET群のFETはドレイン端子が全
て第1共通線4を通じて電源6に接続されてお
り、他方の端子は各々対応する布線端子につなが
つている。また第2FET群のFETはソース端子が
全て第2共通線5を通して電圧レベルを検出する
検出部7に接続され他方の端子は各々対応する布
線端子に接続されている。第1FET群のFETが
ONすると対応する布線端子が電源につながり、
第2FET群のFETが動作すると対応する布線端子
が検出部7につながる。各FETは選択部8から
の信号により各々独立して開閉できる。リレー
R1は一方の端子が第1共通線4を通じて電源6
に接続されており他方の端子は基準布線端子P4
接続されている。またリレーR2は一方の端子が
第2共通線5を通じて電圧レベルを検出する検出
部7に接続され他方の端子は基準布線端子P4に接
続されている。リレーR1が閉じると基準布線端
子P4が電源につながりリレーR2が閉じると基準
端子P4が検出部7につながる。リレーR1,R2
選択部8からの信号により各々独立して開閉でき
る。前憶部10は検出部7から出力された各
FETのON抵抗値を記憶しておき、必要に応じて
制御部9に各FETのON抵抗値を送る。制御部9
は選択部8を通じて全FETおよびリレーを制御
すると同時に検出部7からの出力と記憶部10か
らのFETのON抵抗値を受け布線の良否の判定を
行ない結果を出力する。
The figure is a block diagram showing one embodiment of the present invention, in which the device to be inspected 1 has wiring terminals P 1 , P 2 , P 3 , and a reference wiring terminal P 4 , and P 1 and P 3 are wiring terminals P 1 , P 2 , P 3 , and a reference wiring terminal P 4 . are connected to form circuit 2. FETs S 11 , S 12 , and S 13 form a first FET group, and FETs S 21 , S 22 , and S 23 form a second FET group. The drain terminals of the FETs in the first FET group are all connected to the power supply 6 through the first common line 4, and the other terminals are connected to the respective wiring terminals. Further, the source terminals of the FETs of the second FET group are all connected to the detection unit 7 for detecting the voltage level through the second common line 5, and the other terminals are connected to the respective wiring terminals. The FETs of the 1st FET group are
When turned on, the corresponding wiring terminal is connected to the power supply,
When the FETs of the second FET group operate, the corresponding wiring terminals are connected to the detection section 7. Each FET can be independently opened and closed by a signal from the selection section 8. relay
One terminal of R1 is connected to the power supply 6 through the first common line 4.
The other terminal is connected to the reference wiring terminal P4 . Furthermore, one terminal of the relay R2 is connected to the detection section 7 for detecting the voltage level through the second common line 5, and the other terminal is connected to the reference wiring terminal P4 . When relay R 1 closes, reference wiring terminal P 4 is connected to the power supply, and when relay R 2 closes, reference terminal P 4 is connected to detection section 7 . Relays R 1 and R 2 can be opened and closed independently by signals from selection section 8. The pre-memory section 10 receives each output from the detection section 7.
The ON resistance value of each FET is stored and sent to the control unit 9 as necessary. Control unit 9
controls all FETs and relays through the selection section 8, and at the same time receives the output from the detection section 7 and the ON resistance value of the FET from the storage section 10, judges whether the wiring is good or bad, and outputs the result.

次に本発明の動作について説明する。制御部9
にはあらかじめ被検査装置の布線情報が入力され
記憶されているものとする。まず各FETのON抵
抗値を測定し記憶部10に記憶する。各FETの
ON抵抗値の測定方法をFET S11を例に説明す
る。布線端子P1,P2,P3,と基準布線端子P4を全
て短絡してあるユニツト3を布線検査装置に接続
しFET S11およびリレーR2をONし、他のFET、
リレーを全てOFFする。こうすることにより電
源電圧がFET S11、端子P1,P2,P3およびリレ
ーR2を通して検出部に接続される。リレーR2
ON抵抗と布線端子P1,P2,P3の布線抵抗はほぼ
0なので、検出部7に入力された電圧と電流によ
りFET S11のON抵抗値が計算できる。計算によ
り算出された値を記憶部10に送ることにより
FET S11のON抵抗値の登録が完了する。残りの
FETについても同様の手順によりON抵抗値を測
定し記憶部10に登録する。次に被検査装置1を
布線検査装置に接続し制御部9からの信号で全て
のFET、リレーをOFFにする。初めに布線回路
2の導通検査を行なう。このためにまずFET
S11をONし布線端子P1に電源電圧を加える。次に
FET S23をONして布線端子P3と検出部7を接続
する。布線端子P1,P3の間に布線が存在すれば検
出部7に電源電圧が加わり検出部7から制御部9
へ布線端子P1,P3間の抵抗値が送られ制御部9で
はこの抵抗値から記憶部10から送られてきた
FET S11,S23のON抵抗値の和を減算し、その結
果制御部9では布線端子P1,P3間が導通状態であ
ると判定する。もし布線端子P1,P3の間に布線が
なければ検出部7には電圧が加わらず検出部7か
ら制御部9へ極めて高い抵抗値が送られ制御部9
では布線端子P1,P3の間が絶縁状態であると判定
し不良として記憶する。次に布線回路2と他の全
布線端子との絶縁検査を行なう。このためにまず
FET S11,S13をONして布線端子P1,P3を電源に
接続する。次にFET S22をONして布線端子P2
検出部7に接続する。もしも布線回路2が布線端
子P2と絶縁されているならば検出部7には電圧が
加わらない。布線回路2と布線端子P2との間に導
通がある場合には検出部7に電圧が加わり制御部
9では導通検査の時と同様の手段で布線回路2と
他端子との間に導通ありと判定し不良として記憶
する。以上に述べた検査を被検査装置1の全布線
回路に対して行ない、その過程で記憶された不良
箇所を制御部9が出力して検査は終了する。
Next, the operation of the present invention will be explained. Control unit 9
It is assumed that the wiring information of the device to be inspected is input and stored in advance. First, the ON resistance value of each FET is measured and stored in the storage unit 10. of each FET
The method for measuring ON resistance value will be explained using FET S11 as an example. Connect unit 3, in which wiring terminals P 1 , P 2 , P 3 , and reference wiring terminal P 4 are all short-circuited, to the wiring inspection device, turn on FET S 11 and relay R 2 , and check other FETs,
Turn off all relays. By doing so, the power supply voltage is connected to the detection section through FET S 11 , terminals P 1 , P 2 , P 3 and relay R 2 . Relay R 2
Since the ON resistance and the wiring resistance of the wiring terminals P 1 , P 2 , and P 3 are approximately 0, the ON resistance value of the FET S 11 can be calculated from the voltage and current input to the detection unit 7. By sending the calculated value to the storage unit 10
Registration of the ON resistance value of FET S 11 is completed. Remaining
The ON resistance value of the FET is also measured using the same procedure and registered in the storage unit 10. Next, the device to be inspected 1 is connected to the wiring inspection device, and all FETs and relays are turned OFF using a signal from the control section 9. First, the wiring circuit 2 is tested for continuity. For this we first need to use the FET
Turn on S11 and apply power supply voltage to wiring terminal P1 . next
Turn on FET S 23 and connect wiring terminal P 3 and detection section 7. If there is a wire between the wire terminals P 1 and P 3 , the power supply voltage is applied to the detection section 7 and from the detection section 7 to the control section 9 .
The resistance value between the wiring terminals P 1 and P 3 is sent to the control unit 9, and the resistance value is sent from the storage unit 10 based on this resistance value.
The sum of the ON resistance values of FETs S 11 and S 23 is subtracted, and as a result, the control unit 9 determines that the wiring terminals P 1 and P 3 are in a conductive state. If there is no wire between the wire terminals P 1 and P 3 , no voltage will be applied to the detection section 7 and an extremely high resistance value will be sent from the detection section 7 to the control section 9 .
In this case, it is determined that there is an insulating state between the wiring terminals P 1 and P 3 and it is stored as a defect. Next, an insulation test is performed between the wiring circuit 2 and all other wiring terminals. For this, first
Turn on FETs S 11 and S 13 and connect wiring terminals P 1 and P 3 to the power supply. Next, turn on FET S 22 and connect wiring terminal P 2 to detection section 7. If the wiring circuit 2 is insulated from the wiring terminal P2 , no voltage is applied to the detection section 7. If there is continuity between the wiring circuit 2 and the wiring terminal P2 , a voltage is applied to the detection unit 7, and the control unit 9 detects the voltage between the wiring circuit 2 and other terminals using the same means as in the continuity test. It is determined that there is continuity and it is stored as a defect. The above-described inspection is performed on all the wiring circuits of the device to be inspected 1, and the control section 9 outputs the defective locations stored in the process, and the inspection is completed.

以上述べたように本発明によれば、駆動電流の
小さいFETを切替素子として使用し各FETのON
抵抗値を補正するため布線の良否の判定精度の高
い低消費電力、小型の装置が実現できる。さらに
多数の布線端子間の導通、絶縁を高速かつ自動的
に検査でき、例えば工場等での組立後の検査の迅
速化を計ることができるため製品等のコストダウ
ンが計れる等、その実用的効果は極めて大きい。
As described above, according to the present invention, FETs with small drive current are used as switching elements, and each FET is turned on.
Since the resistance value is corrected, it is possible to realize a small device with low power consumption and high accuracy in determining whether the wiring is good or bad. Furthermore, continuity and insulation between a large number of wiring terminals can be tested automatically and at high speed. For example, it is possible to speed up inspections after assembly in factories, etc., which can reduce the cost of products. The effect is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明による布線検査装置の一実施例を示
すブロツク図で、1は被検査装置、2は布線回
路、3は短絡ユニツト、4は第1共通線、5は第
2共通線、6は電源、7は検出部、8は選択部、
9は制御部、10は記憶部、S11,S12,S13は第
1FET群、S21,S22,S23は第2FET群、R1,R2
リレーを示す。
The figure is a block diagram showing an embodiment of the wiring inspection device according to the present invention, in which 1 is a device to be inspected, 2 is a wiring circuit, 3 is a short circuit unit, 4 is a first common line, 5 is a second common line, 6 is a power supply, 7 is a detection section, 8 is a selection section,
9 is a control unit, 10 is a storage unit, S 11 , S 12 and S 13 are
The first FET group, S 21 , S 22 , and S 23 are the second FET group, and R 1 and R 2 are relays.

Claims (1)

【特許請求の範囲】[Claims] 1 各布線端子をそれぞれ第1共通線に接続する
第1FET群と、前記各布線端子をそれぞれ第2共
通線に接続する第2FET群と、基準布線端子を前
記第1共通線に接続する第1のリレーと、前記基
準布線端子を前記第2共通線に接続する第2のリ
レーと、前記第1および第2FET群の任意のFET
と第1および第2のリレーを選択し開閉する手段
とを有する選択部と、前記第1共通線に電圧を供
給する電源と、前記第2共通線の電圧を感知し抵
抗値を計算し出力する検出部と、前記第1および
第2FET群の各FETのON抵抗値を記憶する記憶
部と、前記選択部を制御し前記検出部の出力と前
記記憶部の情報により布線状態を検査し外部に出
力する制御部とよりなる自動布線検査装置。
1 A first FET group that connects each wiring terminal to the first common line, a second FET group that connects each wiring terminal to a second common line, and a reference wiring terminal that connects to the first common line. a first relay that connects the reference wiring terminal to the second common line, and an arbitrary FET of the first and second FET groups.
a selection unit having means for selecting and opening/closing the first and second relays, a power source for supplying voltage to the first common line, and sensing the voltage of the second common line to calculate and output a resistance value. a detection unit for controlling the ON resistance value of each FET of the first and second FET groups, and a storage unit for controlling the selection unit and inspecting the wiring state based on the output of the detection unit and the information in the storage unit. Automatic wiring inspection device consisting of a control unit that outputs to the outside.
JP7602478A 1978-06-22 1978-06-22 Automatic wiring tester Granted JPS552956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7602478A JPS552956A (en) 1978-06-22 1978-06-22 Automatic wiring tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7602478A JPS552956A (en) 1978-06-22 1978-06-22 Automatic wiring tester

Publications (2)

Publication Number Publication Date
JPS552956A JPS552956A (en) 1980-01-10
JPS6145785B2 true JPS6145785B2 (en) 1986-10-09

Family

ID=13593249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7602478A Granted JPS552956A (en) 1978-06-22 1978-06-22 Automatic wiring tester

Country Status (1)

Country Link
JP (1) JPS552956A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057271A (en) * 1983-09-09 1985-04-03 Hitachi Ltd Continuity testing device
US7326546B2 (en) 2005-03-10 2008-02-05 Ajinomoto Co., Inc. Purine-derived substance-producing bacterium and a method for producing purine-derived substance
BRPI0709635A2 (en) 2006-04-24 2011-07-19 Ajinomoto Kk bacteria belonging to the genus bacillus, and, methods for producing a purine-derived substance, and a purine nucleotide
ES2401607T3 (en) 2006-04-24 2013-04-23 Ajinomoto Co., Inc. Bacteria that can produce a purine substance and procedure to produce a purine substance
RU2365622C2 (en) 2006-12-22 2009-08-27 Закрытое акционерное общество "Научно-исследовательский институт Аджиномото-Генетика" (ЗАО АГРИ) METHOD OF PURINE NUCLEOZIDES AND NUCLEOTIDES PRODUCTION BY FERMENTATION WITH APPLICATION OF BACTERIA BELONGING TO GENUS Escherichia OR Bacillus

Also Published As

Publication number Publication date
JPS552956A (en) 1980-01-10

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