JPS6145795B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an audio clock that notifies an alarm or a time signal using a melody. Alarms and time signals in conventional electronic watches are made by intermittent single frequencies obtained from the middle of a frequency division stage. However, such intermittent single frequency only causes discomfort. Therefore, the present invention attempts to provide a pleasant alarm or time signal by adding a melody to the alarm or time signal. SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic clock that notifies an alarm or a time signal using a melody. Another object of the present invention is to effectively utilize the timing signal of a clock circuit to generate a melody, thereby simplifying the structure. Still another object of the present invention is to provide an electronic timepiece having the above-mentioned structure that can generate a pseudo-scale and can be put to practical use as an alarm or time signal. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall circuit configuration. The reference signal generating circuit 1, the frequency dividing circuit 2, the time counter 3, the decoder circuit 4, and the display 5 constitute a conventionally known clock circuit. That is, the reference signal generation circuit 1 is composed of, for example, a crystal oscillator.
A reference signal of 32.768 KHz is generated, and the frequency dividing circuit 2 divides the frequency of this reference signal to an appropriate frequency and inputs it to the time counter 3. The time counter 3 measures each time information using the frequency-divided signal, and the contents of the time measurement are displayed by being supplied to the display 5 via the decoder circuit 4. Now, this embodiment has an alarm function, and in order to check the coincidence between the time measured by the clock counter 3 and the pre-stored alarm time, the clock output of the clock counter 3 is also sent to the coincidence detection circuit 6. I am typing. The alarm time memory circuit 7 stores alarm times to be compared, and is connected to an input circuit 8 controlled by an external switch or the like.
An appropriate alarm time is input via the . R.S.
When a suitable alarm time is stored in the alarm time memory circuit 7, the flip-flop 9 is set by the coincidence detection output of the coincidence detection path 6 and turns on the gate circuit 10 to generate a melody as an alarm sound. . Appropriate frequency division outputs and time measurement outputs of the frequency division circuit 2 and time measurement counter 3 are inputted to the gate circuit 10.
When the gate circuit 10 is turned on, these outputs are supplied to the melody control circuit 11. As will be explained in detail later, the melody control circuit 11 is composed of, for example, a programmable ROM, and sequentially selects and outputs programmed scale control signals. The scale frequency generation circuit 12 inputs the reference signal from the reference signal generation circuit 1 and the scale control signal from the melody control circuit 11, and generates a pseudo signal corresponding to each scale from the reference signal according to the scale control signal. This will be explained in detail later. The audio output circuit 13 is composed of, for example, a speaker and generates a melody according to the output of the scale frequency generation circuit 12. By the way, when using the reference signal frequency of 32.768 KHz, pseudo-similar frequencies can be created for each scale by combining simple frequency division ratios as shown in Table 1. Table 1 is the C note in the third octave.
It shows the correct frequency corresponding to the C′ note, the division ratio from 32.768KHz, the frequency of the pseudoscale, and the deviation from the correct frequency of the pseudoscale.As is clear from this table, the frequency division from 32.768KHz 15 as ratio
By using a frequency division ratio of ~31, it is possible to create a pseudo scale with a deviation within ±1.0% by combining two frequency division ratios at most.

【table】

[Table] FIG. 2 shows details of the scale frequency generation circuit 12. The frequency divider 14 is provided separately from the clock frequency dividing circuit 2, and is composed of a four-stage flip-flop, which inputs the base signal G from the reference signal generation circuit 1 and divides the Q output of each stage. He is trying to supply it to the frequency ratio control part 15. The frequency division ratio control unit 15 is composed of a ROM matrix of N-channel MOS transistors, and each output line receives the reference signal G and the logic of the frequency division stage outputs Q ₁ , Q ₂ , Q ₃ , Q ₄ (Q ₄ , Q ₃ ,
Q ₂ , Q ₁ , G) are (01111), (10000), (10001),
...(11111), it is programmed to generate a "0" level output. In other words, these logical values correspond to each frequency division ratio 15 in Table 1 above.
(01111) to 31 (11111), and the frequency division ratio is determined from the reset state of the frequency divider 14 with respect to the reference signal G.
When counting the halved cycles, a "0" level output is sequentially generated on each output line. AND gate group A ₁₅ of frequency division ratio selection control section 16 ~
A ₃₁ inputs the inverted output signals of each output line of the ROM matrix to one side, and inputs scale control signals C, C#, D, ..., H, C', which will be described later, to the other side, and operates according to the scale control signals. The output signal of the ROM matrix is extracted from the ROM matrix, and the output is supplied to the reset pulse generation circuit 17 via the OR gate O. The reset pulse generating circuit 17 resets the frequency divider 14 every time the reset pulse R is generated, and resets the frequency divider 14 every cycle in which the corresponding frequency division ratio is halved according to the selection by the scale control signal. After all, these are the and gate group A ₁₅ ~
A ₃₁ selected by the dividing ratio in Table 1, respectively.
It operates as a variable frequency divider that divides the frequency at a frequency division ratio of 1/2, and the reset pulse R is the frequency-divided output. That is, the reset pulse R is the first pulse from the reference signal G.
Extract a frequency signal twice the frequency divided by the frequency division ratio shown in the table. The T flip-flop 18 operates as a waveform shaping circuit, and by inputting the reset pulse R of the reset pulse generation circuit 17, it further reduces the waveform by half.
The frequency is divided and shaped into a 1/2 duty pulse, and a pseudo frequency signal M corresponding to each scale in Table 1 is output. As an example, a pseudotone scale corresponding to D note (1176Hz)
The case where the frequency signal M of 1170.3 Hz is generated is as follows. In the table,
The division ratio to obtain the D pseudoscale from 32.768KHz is 28.
is an AND gate that inputs the scale control signal D.
A ₂₈ is turned on, and only the output of the corresponding output line of the ROM matrix is input to the reset pulse generation circuit 17 via the AND gate A ₂₈ and the OR gate O, and is divided every 28/2 = 14 cycles of the reference signal G. Reset the frequency generator 14. This situation is as shown in the time chart shown in Fig. 3. The reset pulse R is input to the waveform shaping flip-flop 18, which further divides the frequency by 1/2 and shapes it into a 1/2 duty pulse. Frequency divided by 1/28
Obtain a frequency signal M of 1170.3Hz. Furthermore, as is clear from Table 1, C#, D#,
For scales such as F, A#, H, and C', pseudoscales can be obtained by combining two frequency division ratios. In Figure 2,
Another T flip-flop 19 to which the reset pulse R is input is provided to control this frequency division ratio, and the AND gate group _A15 ' to _A19 ', _A23 of the frequency division ratio selection control section 16 is provided. ′, A ₂₄ ′, A ₂₆ ′,
_{The corresponding AND gates A 15 to A 31} are switched on alternately. For example, for the C# note, the scale control signal C# is the AND gate A ₃₀ ',
A ₂₉ ' is input to each one of the outputs of the flip-flop 19 for frequency division ratio control, which is inverted every time the reset pulse R is generated.
Select A ₃₀ and A ₂₉ alternately. As a result, the frequency divider 14 repeats the operations of frequency division by 1/15 and frequency division by 1/14.5. OR gate group O ₁ to _{O 3} are A sound, A# sound, H sound,
This is to deal with the fact that the frequency division ratio of the C' note overlaps with the adjacent scale, and the logic shown in Table 2 is obtained as the output logic of the AND gates _A15 ' to _A19 '.

[Table] Therefore, now the scale control signal A corresponding to the A# note.
Assuming that # is input, the AND gates A ₁₇ ′ and A ₁₈ ′ are turned on through the OR gates O ₂ and O ₃ , and as in the previous example, each Q and output of the flip-flop 19 for frequency division ratio control are turned on. AND gates A ₁₇ and A ₁₈ are alternately selected to perform two types of frequency division ratio control. Note that when a pseudoscale is obtained by a combination of two frequency division ratios, the frequency signal M of the pseudoscale obtained from the waveform shaping flip-flop 18 does not have an accurate 1/2 duty pulse waveform, but this error is different from the reference signal. It is half a cycle of G and can be ignored. FIG. 4 is a detailed diagram of the melody control circuit 11. The melody control circuit 11 consists of a timing decoder section 20 and a scale control signal generation section 21. The timing decoder section 20 is composed of an N-channel MOS transistor, and the scale control signal generation section 21 is composed of a ROM matrix of P-channel MOS transistors. The signals S ₁ to _{S 6} input to the timing decoder section 20 are the frequency division output and time _measurement output shown in FIG. A _2-second signal S ₄ , a 4 _- second signal S ₅ , and an 8-second signal S ₆ are input as time measurement outputs. That is, this timing decoder section 20 can program steps of 8 seconds at minimum 1/8 second intervals. In FIG. 1, when the time measured by the time counter 3 and the alarm time stored in the alarm time memory circuit 6 match, the match detection circuit 6 detects this, sets the RS flip-flop, and divides the clock through the gate circuit 10. The cycle output and the clock output are input to the melody control circuit 11. At this time, the frequency division output and time measurement output, that is, the signal S ₁ to
Assuming that all S ₆ are at “0” level,
Along with time measurement, the timing decoder section 20
Then, the ROM matrix generates a "0" level output on each output line in order from the top according to the program. The ROM matrix of the scale control signal generator 21 selects a scale and generates scale control signals C, C, and C, respectively.
C#, D, . . . H, C', and supplies each scale control signal to the scale generation circuit 12 as detailed in FIG. Now, assuming that the length of a quarter note is 1 second, the minimum step of 1/8 second is the length of a 32nd note, and scales of 32nd note or higher can be programmed here.
However, especially when the same scale continues, it is necessary to make a clear break between each note, so
It is preferable to insert a pause corresponding to the note length of a diacritical note, and make the corresponding note have a total note length. In other words, more than 16th notes can be programmed, and 32
16th note with half note + 32nd rest, 32nd note x 3 + 32
It is best to use a quarter rest as an eighth note. Furthermore, according to this embodiment, the tone length is controlled by the timing decoder section 20 and the scale control signal generation section 21.
It can also be programmed with any ROM matrix. If all the output lines of the timing decoder 20 are configured to generate "0" level output every 1/8 second, the length of each scale will be between the length of the last 1/32nd rest. It is only necessary to program the parts corresponding to each scale control signal line of the scale control signal generating section 21 except for the following. Further, depending on the passage of time and the note length of the musical scale, it is possible to omit an arbitrary step of the timing decoder section 20 in programming. FIG. 5 is a time chart showing the generation of the scale control signal in the detailed diagram of FIG. 4. Here, the tone length of a quarter note is 1 second. The scale control signal C for the C note is actually output for only 1/8 second, which corresponds to a 32nd note, but a 32nd rest is inserted next to make the break in the note clear, so it behaves as a 16th note. I'm letting you do it. This also applies to scale control signals D, E, H, C, etc. corresponding to other scales. In addition, in generating a quarter note of the scale control signal D of the D note, in FIG. 00100), (00101), (00110), (00111) 4
The step is output from one output line, and the logic of (0100×) is set corresponding to the next program position, and two steps (01000) and (01001) are output from one output line, and the timing decoder section 20 The number of steps in is omitted. This omission of the number of steps is also applied to the eighth note of the E note. Omitting such steps is useful because it simplifies the configuration of the timing decoder section 20 and furthermore, the scale control signal generation section 21. The melody control circuit 11 is programmed like this.
By configuring it with a ROM matrix, it is possible to program any melody according to the user's preference. We also offer erasable EPROM matrices, as well as electrically programmable and erasable
If an EEPROM matrix is used, it can be easily rewritten according to the user's requirements, allowing for a fresh and never-boring melody program. The end of the melody can be automatically stopped, for example, by resetting the RS flip-flop 9 shown in FIG. 1 with the output of the final step of the timing decoder section 20. Of course, there is no problem in resetting the RS flip-flop 9 as appropriate by operating a switch from the outside. In this embodiment, the alarm time is stored and a melody is generated as an alarm when the time coincides with the clocked time. It is very easy to generate a melody. As described above, the present invention provides a means for effectively utilizing timing signals from a clock circuit for the reference signal, frequency division output, time measurement output, etc., and dividing the frequency of the timing signal of the clock circuit using a plurality of frequency division ratios. , means for generating a frequency signal pseudo-similar to each musical scale using a combination of one or more of the frequency division ratios;
The device is equipped with a means for sequentially selecting the above-mentioned scales in response to a timing signal from a clock circuit, and has a simple configuration and can notify alarms and time signals using melodies using pseudoscales that can be used for practical purposes. , can provide useful electronic clocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a block diagram showing details of the main parts of FIG. 1, FIG. 3 is a time chart showing signal waveforms of each part in FIG. 2, and FIG. 4 is a block diagram showing details of other main parts of FIG. 1. FIG. 5 is a time chart showing signal waveforms at various parts in FIG. 4. DESCRIPTION OF SYMBOLS 1... Reference signal generation circuit, 2... Frequency division circuit, 3... Time counter, 10... Gate circuit, 11... Melody control circuit, 12... Scale frequency generation circuit, 13...
Audio output circuit, 14... Frequency divider, 15... Frequency division ratio control section, 16... Frequency division ratio selection control section, 17... Reset pulse generation circuit, 18... Flip-flop for waveform shaping, 19... Flip-flop for frequency division ratio control, 20
...timing decoder section, 21... scale control signal generation section.

Claims (1)

[Claims] 1. Inputting a timing signal from a clock circuit and generating a frequency signal corresponding to each musical scale,
A frequency division operation using a plurality of frequency division ratios (integer values) that divides the reference frequency signal of the clock circuit, in which the scale to be generated is sequentially changed to notify an alarm or a time signal with a melody. means for selecting one frequency division ratio and a combination of two phase-adjacent frequency division ratios from among the plurality of frequency division ratios according to each musical scale; frequency, and means for generating a frequency signal pseudo-similar to each musical scale by repeated frequency division every half cycle of each frequency division ratio by a combination of two frequency division ratios. electronic clock.