JPS6146973B2 - - Google Patents
Info
- Publication number
- JPS6146973B2 JPS6146973B2 JP492277A JP492277A JPS6146973B2 JP S6146973 B2 JPS6146973 B2 JP S6146973B2 JP 492277 A JP492277 A JP 492277A JP 492277 A JP492277 A JP 492277A JP S6146973 B2 JPS6146973 B2 JP S6146973B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- forming
- present
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- GTDPSWPPOUPBNX-UHFFFAOYSA-N ac1mqpva Chemical compound CC12C(=O)OC(=O)C1(C)C1(C)C2(C)C(=O)OC1=O GTDPSWPPOUPBNX-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 125000003118 aryl group Chemical group 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 125000006158 tetracarboxylic acid group Chemical group 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 150000004984 aromatic diamines Chemical class 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は所定の基板上に形成された配線構造体
の製造方法に関し、特に微細化を強く要求される
半導体装置に適用して有用なものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a wiring structure formed on a predetermined substrate, and is particularly useful when applied to semiconductor devices that are strongly required to be miniaturized.
本発明を説明するために第１図によつて従来の
多層配線の製造方法と構造を説明する。 In order to explain the present invention, a conventional manufacturing method and structure of multilayer wiring will be explained with reference to FIG.
第１図ａは半導体基板１１上にAlもしくはAl
とSiやCuなどとの合金からなる下部配線１２を
形成し、さらにSiO2などからなる層間絶縁層１
３を被着し、次いで所定の位置に接続用開口１４
Ａおよび１４Ｂを形成し、下部配線の接続部分１
９Ａおよび１９Ｂを露出せしめた状態を示す。こ
の接続部分１９Ａ，１９Ｂの幅をそれぞれＷA，
ＷBとする。このように従来法では接続部分の幅
ＷA，ＷBは層間絶縁物に形成した接続用開口１４
Ａ，１４Ｂの幅と等しい。第１図ｂに示す如くこ
の上に上部配線用導体１５を被着し、上部配線を
形成するために所定の位置にホトレジストパター
ン１６を形成する。このホトレジストパターン１
６の幅をそれぞれＷC，ＷDとする。上部配線用導
体１５としてはAlもしくはAlとSiやCuとの合金
などが用いられる。次にホトレジストパターン１
６をマスクとしてエツチング液によつて上部配線
用導体１５をエツチングし、しかる後にホトレジ
ストパターンを除去すれば、第１図ｃに示す如き
ＷC，ＷDの幅の上部配線を有する構造の多層配線
が形成される。３層以上の配線を形成する場合
は、以上の方法をくり返せば良い。 FIG. 1a shows Al or Al on the semiconductor substrate 11.
A lower wiring 12 made of an alloy of Si, Cu, etc. is formed, and an interlayer insulating layer 1 made of SiO 2 etc. is formed.
3, and then insert the connection opening 14 in the predetermined position.
A and 14B are formed, and the connecting portion 1 of the lower wiring is formed.
9A and 19B are shown exposed. The widths of these connecting portions 19A and 19B are W A ,
Let it be W B. In this way, in the conventional method, the widths W A and W B of the connection portion are determined by the connection opening 14 formed in the interlayer insulator.
It is equal to the width of A and 14B. As shown in FIG. 1b, an upper wiring conductor 15 is deposited thereon, and a photoresist pattern 16 is formed at a predetermined position to form an upper wiring. This photoresist pattern 1
Let the widths of 6 be WC and WD , respectively. As the upper wiring conductor 15, Al or an alloy of Al and Si or Cu is used. Next, photoresist pattern 1
By etching the upper wiring conductor 15 with an etching solution using etching pattern 6 as a mask, and then removing the photoresist pattern, a multilayer wiring structure having upper wirings with widths W C and W D as shown in FIG. 1c is obtained. is formed. If three or more layers of wiring are to be formed, the above method may be repeated.
この様な従来の多層配線においては接続用開口
１４Ａ，１４Ｂとして示した如く、上下部配線の
接続部分１９Ａ，１９Ｂのおのおの一個について
必ず一個の接続用開口が必要である。また接続用
部分１９Ａ，１９Ｂの幅ＷA，ＷBよりも上部配線
の幅ＷC，ＷDは必ず大きく形成されていた。これ
はＷA，ＷBよりもＷC，ＷDの方が小さい場合、第
１図ｄに示す如く、接続用開口１４の上部にある
上部配線用導体１５にはホトレジストパターン１
６で覆われていない部分が存在することになり、
エツチングを行なうとホトレジストパターン１６
で覆われていない部分からエツチング液が浸透
し、下部配線１２をもエツチングして１８Ａ部の
ように信頼性の低下もしくは１８Ｂ部のように断
線に至らしめる可能性があるためである。 In such conventional multilayer wiring, one connection opening is required for each of the connection portions 19A and 19B of the upper and lower wiring, as shown as connection openings 14A and 14B. Furthermore, the widths W C and WD of the upper wiring were always larger than the widths W A and W B of the connection portions 19A and 19B. This means that when W C and W D are smaller than W A and W B , the upper wiring conductor 15 above the connection opening 14 is coated with a photoresist pattern 1, as shown in FIG. 1d.
There will be a part not covered by 6,
After etching, the photoresist pattern 16
This is because the etching solution may permeate through the portions not covered and may also etch the lower wiring 12, resulting in a decrease in reliability as in the section 18A or a disconnection as in the section 18B.
したがつて第１図ｃに示した断面図および第１
図ｅに示した上面図の如く、隣接する接続部分１
９Ａ，１９Ｂ相互の中心間の距離Ｌは
Ｌ＝ＷＣ＋ＷＤ／２＋Ｓ
（但し、Ｓは上部配線の配線間隔）
として表わされる。中心間の距離Ｌは上部配線の
幅ＷC，ＷDと配線間隔Ｓの最小値によつて制約さ
れる。たとえばＷA＝ＷB＝10μｍとすれば、ＷC
＝ＷD＝14μｍが必要であり、配線間隔Ｓを６μ
ｍとすれば、中心間の距離Ｌは20μｍ以下に狭め
ることはできない。Ｌを小さくするためにはＷ
C，ＷDを小さくする必要があるが、接続用開口１
４Ａ，１４Ｂの幅ＷA，ＷBを７μｍ以下に小さく
して安定に形成することは難しい。 Therefore, the cross-sectional view shown in FIG.
As shown in the top view in figure e, the adjacent connecting part 1
The distance L between the centers of 9A and 19B is expressed as L=W C +W D /2+S (where S is the wiring spacing between the upper wirings). The distance L between the centers is restricted by the widths W C and W D of the upper wiring and the minimum value of the wiring spacing S. For example, if W A = W B = 10 μm, W C
=W D =14μm is required, and the wiring spacing S is 6μm.
m, the distance L between the centers cannot be narrowed to 20 μm or less. To reduce L, W
Although it is necessary to reduce C and W D , the connection opening 1
It is difficult to reduce the widths W A and W B of 4A and 14B to 7 μm or less and form them stably.
したがつて上に述べたように中心間の距離Ｌは
20μｍ以下とすることは困難である。 Therefore, as stated above, the distance L between the centers is
It is difficult to reduce the thickness to 20 μm or less.
本発明は以上に述べた隣接する接続部分１９
Ａ，１９Ｂ中心間の距離Ｌを従来よりも大幅に狭
くすることを目的としたものである。 The present invention provides the above-described adjacent connecting portion 19
The purpose of this is to make the distance L between the centers of A and 19B much narrower than before.
本発明によつて形成された多層配線の構造を、
第２図ａにその上面図、ｂはその断面図を示す。
必要に応じて２個以上の接続部分たとえば２９
Ａ，２９Ｂ，２９Ｃを１個の接続用開口２４Ａの
中に含む構造を有することを特徴とする。本発明
の方法では接続用開口２４Ａを小さくする必要が
なくなり、隣接する接続部２９Ａ，２９Ｂの中心
線距離Ｌは上部配線の精度のみで定まることとな
る。すなわち上部配線の形成可能な最小パターン
寸法を４μｍとすれば、ＷA，ＷB，Ｓともに４μ
ｍの場合、隣接する接続部２９Ａ，２９Ｂの中心
間距離Ｌは８μｍにまで狭めることができる。な
お接続用開口２４Ｄはその中に接続部分２９Ｄを
１個のみ含む従来の構造を示している。なお、２
１は基板、２２は第１の配線、２５は第２の配線
を示す。 The structure of the multilayer wiring formed according to the present invention is as follows:
FIG. 2a shows its top view, and FIG. 2b shows its sectional view.
If necessary, connect two or more connecting parts, e.g. 29
A, 29B, and 29C are included in one connection opening 24A. In the method of the present invention, there is no need to make the connection opening 24A small, and the center line distance L between the adjacent connection parts 29A and 29B is determined only by the accuracy of the upper wiring. In other words, if the minimum pattern size that can be formed for the upper wiring is 4μm, then W A , W B , and S are all 4μm.
In the case of m, the distance L between the centers of adjacent connecting portions 29A and 29B can be narrowed to 8 μm. Note that the connection opening 24D has a conventional structure including only one connection portion 29D therein. In addition, 2
1 is a substrate, 22 is a first wiring, and 25 is a second wiring.
以下、本発明を実施例を参照して詳細に説明す
る。 Hereinafter, the present invention will be explained in detail with reference to Examples.
実施例 １
第３図ａは半導体基板３１上の第１の配線たと
えば下部配線３２を被覆する絶縁層３３の所定の
位置に接続用開口３４を形成した状態を示す。次
に第３図ｂの如く、この上に、PIQ樹脂やホトレ
ジストなどのリフトオフ材３７によつて第２の配
線たとえば上部配線の逆パターンを形成した状態
を示す。図３ａでは接続用開口３４に２個の接続
用部分３９Ａ，３９Ｂが含まれている。ちなみに
PIQ樹脂は芳香族ジアミンと芳香族テトラカルボ
ン酸二無水物と、芳香族ジアミンカルボンアミド
とを反応して得られる高耐熱性重合物である。更
に詳しくは特公昭48−2956号公報に記載されてい
る。またリフトオフ材としてはポリイミド樹脂を
用いることもできる。ポリイミド樹脂は芳香族テ
トラカルボン酸二無水物とを反応して得られる重
合物である。Embodiment 1 FIG. 3a shows a state in which connection openings 34 are formed at predetermined positions in an insulating layer 33 covering a first wiring, for example, a lower wiring 32, on a semiconductor substrate 31. In FIG. Next, as shown in FIG. 3B, a second wiring, for example, a reverse pattern of the upper wiring is formed thereon using a lift-off material 37 such as PIQ resin or photoresist. In FIG. 3a, the connecting opening 34 includes two connecting parts 39A, 39B. By the way
PIQ resin is a highly heat-resistant polymer obtained by reacting aromatic diamine, aromatic tetracarboxylic dianhydride, and aromatic diamine carbonamide. More details are described in Japanese Patent Publication No. 48-2956. Moreover, polyimide resin can also be used as the lift-off material. Polyimide resin is a polymer obtained by reacting with aromatic tetracarboxylic dianhydride.
この場合接続用開口は十分に大きな幅ＷAを有
するもので良い。接続用開口３４の一部がリフト
オフ材３７で覆われていても良い。次に第３図ｃ
に示す如く上部配線用導体層３５をこの上に被着
する。最後にリフトオフ材３７のエツチング液に
半導体基板３１を浸し、リフトオフ材３７および
リフトオフ材上の導体層３５を除去すれば第３図
ｄに示す如く本発明の配線構造が実現される。 In this case, the connection opening may have a sufficiently large width W A . A portion of the connection opening 34 may be covered with a lift-off material 37. Next, Figure 3c
An upper wiring conductor layer 35 is deposited thereon as shown in FIG. Finally, by immersing the semiconductor substrate 31 in an etching solution for the lift-off material 37 and removing the lift-off material 37 and the conductor layer 35 on the lift-off material, the wiring structure of the present invention is realized as shown in FIG. 3d.
図２ａや図３ｄに示す如く、本発明の多層配線
構造では、隣接する接続部分相互の中心間距離Ｌ
はＷA，ＷB，Ｓによつてのみ制約される。ＷA，
ＷB，Ｓは上部配線パターンの精度によつて制約
されるのみであるからＬを10μｍ以下とすること
も可能である。 As shown in FIGS. 2a and 3d, in the multilayer wiring structure of the present invention, the distance L between the centers of adjacent connection parts is
is constrained only by W A , W B , and S. W A ,
Since W B and S are limited only by the accuracy of the upper wiring pattern, it is also possible to set L to 10 μm or less.
すなわち、本発明によれば、配線間の距離を、
従来よりも著るしく短かくすることが可能であ
り、上部配線の集積度向上に有効である。 That is, according to the present invention, the distance between the wires is
It can be made significantly shorter than the conventional one, and is effective in improving the degree of integration of the upper wiring.
また、本発明は基板はセラミツク基板等を用
い、配線構造体を作製する場合にも適用できるも
のである。 Further, the present invention can also be applied to the case where a ceramic substrate or the like is used as the substrate to produce a wiring structure.
第１図は本発明の説明に供するための、従来の
多層配線構造の断面および上面を示す図、第２図
は本発明の多層配線構造の上面および断面を示す
図、第３図は本発明の実施例を説明する図であ
る。
1 is a diagram showing a cross section and a top surface of a conventional multilayer wiring structure for explaining the present invention, FIG. 2 is a diagram showing a top surface and a cross section of a multilayer wiring structure according to the present invention, and FIG. 3 is a diagram showing a cross section of a conventional multilayer wiring structure according to the present invention. It is a figure explaining an example.
Claims (1)
体基板上に形成する工程と、開口部を有する絶縁
膜を上記導電体膜の互いに離間した部分の一部お
よび上記半導体基板表面の一部が上記開口部を介
して露出するように上記導電体膜上に形成する工
程と、樹脂膜を全面に形成する工程と、上記樹脂
膜の所望部分を選択的に除去して上記絶縁膜がそ
の上に形成されていない部分の上記導電体膜の少
なくとも一部を露出させる工程と、第２の導電体
膜を全面に形成する工程と、上記樹脂膜を該樹脂
膜上の上記第２の導電体膜とともに除去すること
により、上記絶縁膜の開口部内に互いに離間され
た上記導電体膜と上記第２の導電体膜からなる積
層膜を形成する工程を含むことを特徴とする半導
体装置の製造方法。1. A step of forming a conductive film having portions spaced apart from each other on a semiconductor substrate, and forming an insulating film having an opening so that part of the spaced apart portion of the conductive film and a part of the surface of the semiconductor substrate are formed in the opening. a step of forming a resin film on the conductive film so as to be exposed through the portion; a step of forming a resin film on the entire surface; and a step of selectively removing a desired portion of the resin film and forming the insulating film thereon. a step of exposing at least a part of the conductive film in a portion that is not covered, a step of forming a second conductive film on the entire surface, and a step of depositing the resin film together with the second conductive film on the resin film. A method for manufacturing a semiconductor device, comprising the step of forming a laminated film consisting of the conductor film and the second conductor film spaced apart from each other in an opening of the insulating film by removing the conductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP492277A JPS5390886A (en) | 1977-01-21 | 1977-01-21 | Wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP492277A JPS5390886A (en) | 1977-01-21 | 1977-01-21 | Wiring structure |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60093605A Division JPS60258937A (en) | 1985-05-02 | 1985-05-02 | Manufacture of wiring structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5390886A JPS5390886A (en) | 1978-08-10 |
| JPS6146973B2 true JPS6146973B2 (en) | 1986-10-16 |
Family
ID=11597096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP492277A Granted JPS5390886A (en) | 1977-01-21 | 1977-01-21 | Wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5390886A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133674A (en) * | 1981-02-13 | 1982-08-18 | Hitachi Ltd | Structure of multilayer wiring |
| US5266835A (en) * | 1988-02-02 | 1993-11-30 | National Semiconductor Corporation | Semiconductor structure having a barrier layer disposed within openings of a dielectric layer |
-
1977
- 1977-01-21 JP JP492277A patent/JPS5390886A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5390886A (en) | 1978-08-10 |
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