JPS6146992B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing isolated junction field effect transistors (hereinafter referred to as J-FETs).

The figure of merit (F・M) of J-FET is generally expressed as F・M=gm/Ci. It is said that the larger this value is, the better the high frequency characteristics are. In the above equation, gm is mutual conductance and Ci is input capacitance.

Incidentally, Ci is the sum of the junction capacitance between the substrate and the isolation region and the island region, and the junction capacitance between the gate and the island region, and in a J-FET with a somewhat large gm, the former junction capacitance accounts for about 85%.

On the other hand, gm is proportional to W/L, where L is the gate length and W is the gate width, but L cannot be made very thin due to limitations in photo-etching operations. Therefore, if W is made longer in order to increase gm, many gates will be formed within the island region, and the area of the island region will eventually increase. Since the junction capacitance between them would also increase, it was not possible to increase the figure of merit.

Therefore, in order to increase the figure of merit, it is better to reduce Ci, and the most desirable is a so-called insulation isolation type J-FET in which the junction capacitance between the substrate, the isolation region, and the island region can be ignored.

The inventors had previously proposed an insulating isolation structure using porous silicon in Japanese Patent Application No. 133371-1982, but
When attempting to obtain a J-FET with a large figure of merit by reducing Ci by applying the above structure, the following disadvantages occurred.

FIG. 1 shows a cross-sectional structural diagram of an isolation type J-FET. A P-type Si thin layer 2 is formed on the main surface of an N-type Si substrate 1 by an epitaxial method or a diffusion method.
Furthermore, an N-type Si epitaxial layer 3 is formed, and separation diffusion is performed until it reaches the P-type layer 2, thereby making it porous. The porosity progresses selectively in the P-type region, and the area under the separation region does not become deeply porous due to the adoption of the N-type substrate, which is a feature of this structure, but instead moves toward the lateral P-type layer as shown by the arrow. It is made porous and transformed into a waterfall porous region 4. This region 4 is further converted into an insulator by oxidation treatment, and the isolation regions at the bottom and sides of the N-type island region are made into an insulator.
On the other hand, when increasing the gate width to increase gm, for example, a J-FET with a comb-shaped plane pattern
As shown in the figure, there are many sources within the N-type island region.
It is necessary to form a drain 6 and a gate 7. However, for this reason, the width X of the N-type island region increases, often from 100 μm or more to several hundred μm.
Therefore, it takes a long time to make the P-type layer at the bottom of the N-type island region porous, and in some cases, the P-type layer may remain without being made porous, making it impossible to obtain a complete insulation isolation structure. It was difficult.

The present invention provides a manufacturing method that improves these conventional drawbacks.

Examples will be described below with reference to the drawings. First, an N-type silicon substrate 11 is prepared, and P
A silicon layer 12 having a thickness of approximately 1 .mu.m is formed by epitaxial growth, for example, and an N-type silicon layer 13 having a thickness of approximately 2 to 3 .mu.m is subsequently formed thereon by epitaxial growth. Note that the P-type silicon layer may be formed by thermal diffusion or ion implantation. (FIG. 2A) Next, a SiO ₂ film 14 is formed as a diffusion mask on the surface of the N-type silicon layer 13 by, for example, thermal oxidation, and an isolation diffusion window 15 and source/drain forming portions are formed by normal photoetching. Diffusion windows 16 are opened in a plurality of predetermined regions of the region, and P-type impurities are diffused through the diffusion windows 15 and 16 by thermal diffusion or ion implantation, and P-type impurities are spread across the N-type silicon layer 13. P-type impurity diffusion layers 17 and 18 are formed to reach the silicon layer 12. Reference numeral 17 indicates an isolation region, and as a result, an N-type island region 19 whose side and bottom surfaces are surrounded by P-type regions 17 and 12 is formed, and a plurality of regions which become a source and a drain within the N-type island region are formed. A P-type region 18 is also formed therein. (Fig. 2B) A plan view of Fig. 2B is shown in Fig. 3. FIG. 2B is a sectional view taken along the line -' in FIG. In order to increase gm, a plurality of gates G (indicated by broken lines) to be formed in a later step are arranged in the N-type island region 19, and opposing sources and drains are later arranged on both sides of the diffusion layer 18. This is a so-called comb-shaped pattern, and therefore the planar dimension of the N-shaped island region is also large, for example, about 150 μm square. A P-type diffusion layer, that is, a P-type region 18, reaching the bottom P-type silicon layer is also formed in the source/drain region formation portion.

Next, the above-mentioned substrate is immersed in an electrolytic solution such as a hydrofluoric acid aqueous solution to perform anodization, and the P-type region 1 is
Only 7, 18, 12 are porous silicon 20, 2
Make it 1,22.

In this case, in the present invention, the silicon substrate is of N type and the substrate is not made porous, but P
If the shaped regions 17 and 18 are made porous, the porosity is caused by the P-type silicon layer 1 at the bottom of the N-type island region 19.
2. Proceed laterally. Furthermore, in the past, the P-type region below the N-type island region was made porous from a separate P-type region, so if the N-type island region has a width of 150 μm, the width of the P-type region below the N-type island region is 75 μm even if it advances from both sides.
It is necessary to make the material porous by m, and it takes a very long time to make the material porous. In some cases, areas that are not made porous remain, resulting in disadvantages such as generation of steps and distortions. In contrast, the present invention has a plurality of P-type regions 1 in the source and drain regions (source and drain region forming portions).
8, and in order to promote porosity from there, the P-type region 12 under the N-type island region is connected to each of the plurality of sources and drains in the N-type island region, regardless of the size of the N-type island region. determined by the distance between Therefore, if the distance between the source and the drain is set to 15 μm, for example, porosity will progress from both sides, so the P-type regions 12 at the bottom of the N-type island regions will only be made porous by 7.5 μm, which is half of each. All porosity has been completed, and the distance and time required to create porosity can be reduced to 1/10 of the conventional method. (Fig. 2C) Next, when the above substrate is heat-treated in an oxidizing atmosphere, the porous silicon 20, 21, 22 becomes SiO ₂ region 2.
3, 24, and 25, an N-type island region whose bottom and side surfaces are surrounded by SiO ₂ regions 25 and 23 and whose source and drain forming regions also have SiO ₂ regions 24 is obtained. In this case, since oxidation proceeds simultaneously from each porous silicon region in contact with the surface, the oxidation time is shortened and the porous silicon 22 on the bottom surface is completely oxidized.
is also oxidized. (Fig. 2D) Next, a diffusion window is opened including the SiO ₂ region 24.
A source 26 and a drain 27 are formed by forming N-type impurity diffusion layers on the island regions on both sides of the wafer 4. (Second
Figure E) Next, SiO ₂ in a predetermined area between the source and drain
Diffusion windows are opened in the film and P-type impurities are diffused to form the gate region 28. Furthermore, windows for electrodes are opened to form source electrodes 29, drain electrodes 30, and 30, respectively.
The gate electrode 31 is deposited and connected. (FIG. 2F) As explained above, according to the present invention, when the side and bottom surfaces of a large N-type island region are made porous and oxidized, multiple source and drain regions within the N-type island region are also P reaching the bottom P-type silicon layer
By forming the shaped region in advance, it became possible to make the bottom P-type silicon layer porous in about 1/10 of the time required by conventional methods. In addition, porous silicon can be completely oxidized in a short time, making it possible to completely oxidize porous silicon.
-FETs have become easier to obtain. A J-FET having a structure obtained by the method of the present invention
Therefore, even if gm is made larger than before and the area of the N-type island region increases, only the junction capacitance of the gate diffused from the surface needs to be considered for the P-N junction capacitance.
Ci was reduced to a fraction of that of the previous model, making it possible to increase the performance index by more than 10 times.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional insulation type J-FET, FIGS. 2A to 2F are process sectional views of an insulation type J-FET according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional insulation type J-FET. It is a top view in a state. 11... N-type silicon substrate, 19... N-type island region, 20, 21, 22... Porous silicon, 2
3, 24, 25... _SiO2 region, 26...source, 27...drain, 28...gate.

Claims (1)

[Claims] 1. A step of sequentially forming a P-type conductivity type semiconductor layer and an N-type conductivity type semiconductor layer on an N-type conductivity type semiconductor substrate, and a separation region and an island region partitioned by the separation region in the N-type conductivity type semiconductor layer. forming a P-type conductivity type impurity diffusion layer in a plurality of predetermined regions of the P-type conductivity type semiconductor layer so as to reach the P-type conductivity type semiconductor layer; a step of making the diffusion layer porous;
The process includes the steps of: converting the porous semiconductor layer into an insulator; and diffusing N-type conductivity type impurities into a plurality of insulator regions in the island region to form sources and drains. A method for manufacturing a junction field effect transistor, characterized in that: