JPS6147016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A clock pulse of a desired period can be obtained by applying a basic clock pulse obtained by a crystal oscillator or the like to a frequency divider. However, such a device has the disadvantage that the period of the obtained clock pulse cannot be arbitrarily set with a resolution greater than the period of the basic clock pulse. Accordingly, the present invention provides a clock pulse generator which has a higher resolution than the period of the basic clock pulse and can arbitrarily set the period.

FIG. 1 is a block configuration diagram of an embodiment of the present invention, in which a basic clock pulse generator P using a crystal oscillator etc.
For example, 100MHz as shown in Figure 2 a, so
A basic clock pulse with a period of 10 nS is sent out and the pulses are counted by a counter N. Further, one of the gate circuits G1 and G2 is always open and the other is closed according to the output of the flip-flop circuit F. When a suitable integer value is set by manual operation, the value setters S1 and S2 send out a digital signal corresponding to the value, such as binary or decimal, in the same format as the output signal of the counter N. . This signal passes through the gate circuit G1 or G2 and is applied to the coincidence circuit C together with the output signal of the counter N. Therefore, assuming that the numerical values "3" and "2" are set in the setters S1 and S2, respectively,
When the gate circuit G1 is open, the counter N is 3.
When the basic clock pulses a have been counted, one signal pulse is sent out from the coincidence circuit C, which resets the counter. Assuming that the gate circuit G2 is open, when the counter N counts two basic clock pulses, a signal pulse is sent out from the coincidence circuit C, and the counter is reset by this pulse. The pulses sent from the coincidence circuit C are applied to the AND gates A1 and A2, but these AND gates are controlled by the output of the flip-flop circuit F and are alternately opened, and the pulses that have passed through the AND gate A1 are applied to the OR gate O. The signal is sent out from the output terminal T via. Further, the output pulse of the AND gate A2 passes through a delay circuit D having a delay amount of 5 nS, and then is sent out from an output terminal T via an OR gate O. Furthermore, the pulse applied to the output terminal T drives the flip-flop circuit F at the same time.

In the device described above, assuming that gate circuit G1 and AND gate A1 are open, one pulse is sent out from coincidence circuit C when counter N has counted three basic clock pulses a.
This pulse is sent out from the output terminal T through the AND gate A1 and the OR gate O, resets the counter N, and resets the flip-flop circuit F.
Invert. Therefore, gate circuit G2 and AND gate A2 are then opened so that when counter N has counted two elementary clock pulses a, coincidence circuit C sends out one pulse. The pulse resets the counter N, passes through the delay circuit D and the OR gate O, is sent out from the output terminal T, and inverts the flip-flop circuit F again. Coincidence circuit C thus delivers an output pulse when counter N counts 3 and 2 elementary clock pulses alternately, so that the output pulse is represented in FIG.
The two output pulses are shown as c and d in the figure, respectively. The pulse shown in FIG. 2(d) passes through the delay circuit D and is delayed by 5 nS as shown in FIG. 2(e). The OR gate O synthesizes the pulses shown as c and e in Figure 2, so it is 25nS as shown in Figure 2 f.
A clock pulse with a constant period of 2 is sent out from the output terminal T. In other words, the period of the basic clock pulse a is 10 nS, but the output clock pulse f is not an integral multiple of that period but a fraction of 1 or less, 2.5 ns.
It has twice the period.

As described above with respect to one embodiment, the present invention includes a counter N, a coincidence circuit C, numerical value setters S1 and S.
The two-gate circuits G1, G2, flip-flop circuit F, etc. constitute a frequency divider whose frequency division ratio changes at a constant cycle, and a basic clock pulse is added to this divided cycle, and an integer fraction of the period of the basic clock pulse is added to this divided cycle. A delay circuit D having a delay amount of is provided, and the output pulses of the frequency divider are passed through the delay circuit alternately in synchronization with the change period of the frequency division ratio. Note that in the above embodiment, for simplicity, 1
Only one delay circuit is provided, which changes the frequency division ratio every time the clock pulse is counted, and has a delay amount that is half the period of the basic clock pulse. However, for example, a frequency divider is used that sends out three divided pulses with a dividing ratio of 2, and then sends out one divided pulse with a dividing ratio of 3, and the delay amount is 0 and the basic clock pulse. 1/4, 2/4, and 2/4 of the period of
When a 3/4 circuit is provided and each divided pulse is configured to pass through each of the circuits in turn, a clock pulse having a period 2.25 times that of the basic clock pulse is obtained. Thus, according to the present invention, the period of the output clock pulse can be arbitrarily set with a higher resolution than the period of the basic clock pulse.

[Brief explanation of the drawing]

Fig. 1 is a block configuration diagram of an embodiment of the present invention;
The figure is a time chart explaining the operation of the apparatus shown in FIG. In the figure, P is a basic clock pulse generator, N is a counter, C is a matching circuit, S1, S
2 is a numerical value setter, G1 and G2 are gate circuits, F is a flip-flop circuit, A1 and A2 are AND gates, D is a delay circuit, O is an OR gate, and T is an output terminal.

Claims (1)

[Scope of Claims] 1. A basic clock generator for sending out basic clock signals; B a counter for counting the number of basic clock signals; and C a number of different counts to be counted by the counter. A numerical value setter for setting one of them, and D. A numerical value from the numerical value setter and the counting result of the counter are given, and when the two match, a match signal is sent out and the counter is reset. a matching circuit; E a plurality of delay circuits having sequentially different delay times corresponding to integer fractions of the period of the basic clock signal; A gate circuit for applying a coincidence signal from G, a synthesis circuit for synthesizing the signals sent from the plurality of delay circuits on the time axis and outputting it as a clock pulse, and H for each time a clock pulse is obtained from the synthesis circuit. A clock pulse generator comprising: a control circuit that controls selection of the delay circuit and selection of the plurality of count values.