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JPS6147453B2 - - Google Patents
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JPS6147453B2 - - Google Patents

Info

Publication number
JPS6147453B2
JPS6147453B2 JP55158717A JP15871780A JPS6147453B2 JP S6147453 B2 JPS6147453 B2 JP S6147453B2 JP 55158717 A JP55158717 A JP 55158717A JP 15871780 A JP15871780 A JP 15871780A JP S6147453 B2 JPS6147453 B2 JP S6147453B2
Authority
JP
Japan
Prior art keywords
data
consecutive
bits
transmission
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55158717A
Other languages
Japanese (ja)
Other versions
JPS5781742A (en
Inventor
Mineo Hosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55158717A priority Critical patent/JPS5781742A/en
Publication of JPS5781742A publication Critical patent/JPS5781742A/en
Publication of JPS6147453B2 publication Critical patent/JPS6147453B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【発明の詳細な説明】 本発明は監視信号がNRZ等長符号の常時サイク
リツク2連送照合による遠方監視システムのフレ
ーム同期方式に関し、特に同期符号としてデータ
に付加することなしに監視信号の同期をとる方式
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization method for a remote monitoring system in which a monitoring signal is constantly cyclically transmitted twice and collated with an NRZ equal-length code. This is related to the method used.

従来、この種の遠方監視システムの監視信号の
同期方式は、一例として、12ビツトが連続して
“1”である同期符号(通信速度が50bit/secの場
合240msが“1”である信号)を付加し、データ
とタイミングを取り送受信を行なうフレーム同期
方式が用いられてきた。すなわち、例えば第1図
に示すように12ビツトが“1”である同期信号
1、スタートビツト2、パリテイビツト3、スト
ツプビツト4、8ビツトのデータ5〜8から成る
符号構成を有していた。
Conventionally, the synchronization method for monitoring signals in this type of remote monitoring system is, for example, a synchronization code in which 12 bits are continuously "1" (if the communication speed is 50 bit/sec, a signal in which 240 ms is "1"). A frame synchronization method has been used in which data is added and data is sent and received in synchronization with the timing. That is, as shown in FIG. 1, for example, it had a code structure consisting of a synchronizing signal 1 of which 12 bits were "1", two start bits, three parity bits, four stop bits, and data 5 to 8 of 8 bits.

したがつて、フレーム毎に同期符号を付加する
ことにより、データは冗長化し、12ビツトが連続
して“1”である信号の発生ロジツクと検出ロジ
ツクを必要としていた。また、1フレームの長さ
は、送受信側のクロツク周波数の安定度と受信符
号許容ひずみから定まるため、クロツクの精度及
び伝送路のひずみに対する性能とデータの冗長性
が関連性を持つていた。
Therefore, by adding a synchronization code to each frame, data becomes redundant, requiring logic for generating and detecting a signal in which 12 bits are continuously "1". Furthermore, since the length of one frame is determined by the stability of the clock frequency on the transmitting and receiving sides and the permissible distortion of the received code, there is a relationship between clock accuracy, transmission line distortion performance, and data redundancy.

本発明は監視信号の伝送形式が常時サイクリツ
ク2連送照合である特徴を利用し、フレームの初
めの2連送データを2連送生成又は照合の段階で
データの初めの2連送目の8ビツトを1連送目の
8ビツトに演算を加えたもので構成することによ
り、同一データを再送する他のデータと区別し、
前記の12ビツトが連続して“1”である同期符号
を付加することなく、フレームの初めの検出を可
能とし、また、ソフトウエアで取扱う8ビツトだ
けでフレーム同期符号を構成でき、クロツク等の
ハード上の理由と無関係にデータを冗長化しない
フレーム同期方式を提供するものである。
The present invention makes use of the feature that the transmission format of the monitoring signal is always cyclic double transmission verification, and the first two consecutive transmissions of a frame are generated or verified at the stage of two consecutive transmissions. By configuring the bits by adding calculations to the 8 bits of the first consecutive transmission, the same data can be distinguished from other data that is retransmitted.
It is possible to detect the beginning of a frame without adding the above-mentioned synchronization code in which the 12 bits are ``1'' consecutively, and the frame synchronization code can be configured with only 8 bits handled by software, making it easy to use for clocks, etc. This provides a frame synchronization method that does not make data redundant regardless of hardware reasons.

即ち、本発明は、遠方監視システムの監視信号
の同期符号を構成する場合、別に同期符号を付加
することなく、フレームの最初の2連送データの
1連送目と2連送目のデータ内容を、一定の関連
性を持つて異ならせ、同一データが再送される他
のデータと区別して構成することにより、フレー
ムの初めの2連送データを同期符号として取扱え
ることを特徴とする。
That is, when configuring a synchronization code for a monitoring signal of a remote monitoring system, the present invention allows the data contents of the first and second consecutive transmissions of the first two consecutive transmissions of a frame to be used without adding a separate synchronization code. By making the data different with a certain relationship and configuring the same data to be distinguished from other data that is retransmitted, it is possible to treat the two consecutively transmitted data at the beginning of the frame as a synchronization code.

次に本発明の実施例について図面を参照して説
明する。第2図は本発明の実施例であつて、2,
3,4はそれぞれスタートビツトパリテイビツ
ト、ストツプビツト2ビツト、9〜12はデータ
8ビツトであり、P−S変換時にデータ8ビツト
にビツト2,3,4を付加して1キヤラクタが構
成され、データ9,10を含むキヤラクタを除
き、同一キヤラクタが2回続く2連送形式をと
る。データ8ビツト10は1連送目のデータ+α
(ここではα=1で実施している)で構成され、
同期符号1と異なり、データ9,10を同期符号
として取扱う。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows an embodiment of the present invention, 2,
3 and 4 are start bit parity bits, 2 stop bits, 9 to 12 are 8 data bits, and one character is constructed by adding bits 2, 3, and 4 to the 8 data bits during P-S conversion. Except for characters including data 9 and 10, the same character is sent twice in a row. Data 8 bits 10 is the data of the first consecutive transmission + α
(Here, it is implemented with α = 1),
Unlike synchronous code 1, data 9 and 10 are handled as synchronous codes.

第3図、第4図は本発明の方式を用いて、ソフ
トウエアで実施した例である。送信側は13でデ
ータ9を送出し、14で上記のデータ10を生成
し送出する。次いで、15,16でデータ11,
12を送出し17でデータの終りを検出するまで
データ内容を更新し送出する。
FIGS. 3 and 4 are examples of software implementation using the method of the present invention. The transmitting side sends data 9 at 13, and generates and sends the above data 10 at 14. Then, at 15 and 16, data 11,
12 is sent out, and the data contents are updated and sent out until the end of the data is detected in 17.

受信側は18,19で1連送目と2連送目を入
力し、20で2連送目のデータ=1連送目のデー
タ+αをチエツクし、条件が一致するまで上記入
力及びチエツクを繰返し行ない、一致した場合同
期符号を検出したことになり、21へ進みデータ
の処理を行なう。以後22でデータの終りを検出
するまで、23,24で1連送目及び2連送目の
データを入力し、25で1連送目のデータ=2連
送目のデータをチエツクし、等しければ21へ、
異なれば26でエラー処理を行ない22へ進む。
The receiving side inputs the first and second consecutive transmissions at steps 18 and 19, and checks the second consecutive transmission data = first consecutive transmission data + α at 20, and continues the above input and checking until the conditions match. This is repeated, and if they match, it means that a synchronization code has been detected, and the process advances to step 21 to process the data. From then on, until the end of the data is detected at 22, the data of the first and second consecutive transmissions are input at 23 and 24, and at 25, the data of the first consecutive transmission = the data of the second consecutive transmission is checked, and if they are equal. To Ba21,
If they are different, error processing is performed at 26 and the process proceeds to 22.

以上の様に2,3,4のビツトと無関係に同期
符号の生成検出機能を持つことを可能にした。
As described above, it has become possible to have a synchronization code generation and detection function independent of bits 2, 3, and 4.

本発明は以上説明した様に、1の同期符号を付
加せずにフレームの初めを認識でき、かつ、ソフ
トウエアへの置き換を容易にする効果がある。ま
た、「α」の内容を変えることにより、状態変化
の有無等の情報を重畳することもできる。
As described above, the present invention has the effect of being able to recognize the beginning of a frame without adding a synchronization code of 1, and of facilitating software replacement. Furthermore, by changing the content of "α", information such as the presence or absence of a state change can be superimposed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の符号構成を示す図、第2図は本
発明の一実施例の符号構成を示す図、第3図と第
4図は本発明の方式を用いて実施した処理の流れ
図である。 1は12ビツトが“1”である同期信号、2はス
タートビツト、3はパリテイビツト、4はストツ
プビツト2ビツト、5〜12は8ビツトのデー
タ、13はデータ群の初めの1連送目の送出処
理、14は1連送目のデータ+αの生成及び送出
処理、15,16はデータ群の2番目以降のデー
タの1連送目及び2連送目の送出処理、17,2
1はデータ群の終了検出処理、18,23は1連
送目の入力処理、19,24は2連送目の入力処
理、20は2連送目のデータ=1連送目のデータ
+αの検出処理、21はデータ処理、25は2連
送目のデータ=1連送目のデータの検出処理、2
6はエラー処理である。
FIG. 1 is a diagram showing a conventional code structure, FIG. 2 is a diagram showing a code structure according to an embodiment of the present invention, and FIGS. 3 and 4 are flowcharts of processing performed using the method of the present invention. be. 1 is a synchronization signal in which 12 bits are "1", 2 is a start bit, 3 is a parity bit, 4 is a 2-bit stop bit, 5 to 12 are 8-bit data, and 13 is the first consecutive transmission at the beginning of a data group. Processing, 14 is the generation and sending process of the first consecutive data + α, 15, 16 is the sending process of the first and second consecutive data of the second and subsequent data groups, 17, 2
1 is the end detection processing of the data group, 18 and 23 are the input processing for the first consecutive transmission, 19 and 24 are the input processing for the second consecutive transmission, and 20 is the data for the second consecutive transmission = the data for the first consecutive transmission + α. Detection processing, 21 is data processing, 25 is detection processing of 2nd consecutive transmission data = 1st consecutive transmission data, 2
6 is error processing.

Claims (1)

【特許請求の範囲】[Claims] 1 データ群の最初の2連送データの1連送目と
2連送目のデータ内容を一定の関連を持つて異な
らせ、同一データが再送される2連送形式と区別
し、最初の2連送データをフレーム同期符号とし
て取扱うことを特徴とする同期方式。
1 The data contents of the first two consecutive transmissions of the first two consecutive transmissions of the data group are different from the second consecutive transmission with a certain relationship, and the data contents of the first two consecutive transmissions are different from the two consecutive transmission format in which the same data is retransmitted. A synchronization method characterized by handling continuous transmission data as a frame synchronization code.
JP55158717A 1980-11-11 1980-11-11 Synchronizing system Granted JPS5781742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55158717A JPS5781742A (en) 1980-11-11 1980-11-11 Synchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55158717A JPS5781742A (en) 1980-11-11 1980-11-11 Synchronizing system

Publications (2)

Publication Number Publication Date
JPS5781742A JPS5781742A (en) 1982-05-21
JPS6147453B2 true JPS6147453B2 (en) 1986-10-20

Family

ID=15677803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55158717A Granted JPS5781742A (en) 1980-11-11 1980-11-11 Synchronizing system

Country Status (1)

Country Link
JP (1) JPS5781742A (en)

Also Published As

Publication number Publication date
JPS5781742A (en) 1982-05-21

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