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JPS6148262B2 - - Google Patents
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JPS6148262B2 - - Google Patents

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Publication number
JPS6148262B2
JPS6148262B2 JP15831079A JP15831079A JPS6148262B2 JP S6148262 B2 JPS6148262 B2 JP S6148262B2 JP 15831079 A JP15831079 A JP 15831079A JP 15831079 A JP15831079 A JP 15831079A JP S6148262 B2 JPS6148262 B2 JP S6148262B2
Authority
JP
Japan
Prior art keywords
nitride film
melting point
molybdenum
point metal
high melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15831079A
Other languages
Japanese (ja)
Other versions
JPS5680144A (en
Inventor
Hiroshi Tokunaga
Nobuo Toyokura
Shinichi Inoe
Hajime Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15831079A priority Critical patent/JPS5680144A/en
Publication of JPS5680144A publication Critical patent/JPS5680144A/en
Publication of JPS6148262B2 publication Critical patent/JPS6148262B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は、高融点金属の微細な電極・配線を有
する半導体装置を製造する場合に適用して有効な
方法に関する。 近年、電極・配線にモリブデン(Mo),タング
ステン(W)など高融点金属がしばしば用いられ
る。その理由は、それ等金属材料が多結晶シリコ
ンに比較して低抵抗であるから装置の高速化に寄
与できること、精密なパターニングが可能である
など加工性に優れていること、電極・配線形成後
の熱処理温度に充分耐え得ることなどが主なもの
である。 ところで、一般に電極・配線パターンの形成は
紫外光を利用するフオト・リソグラフイ技術が多
用されているが、その技術を用いた場合の再現性
良くパターン微細化できる範囲は2〔μm〕まで
とされている。 本発明は、Mo,W,チタン(Ti),タンタル
(Ta),ニオブ(Nb),ハフニウム(Hf)などの
高融点金属からなる電極・配線を微細パターンで
再現性良く形成できるようにするものであり、以
下これを詳細に説明する。 第1図乃至第7図は本発明一実施例としてMIS
電界効果半導体装置のゲート電極を形成する工程
を表わすものであり、次に、これ等の図を参照し
つつ記述する。 第1図参照 (1) 一導電型、例えばn型を有するシリコン半導
体基板1に通常の技術を適用してフイールド用
絶縁膜2、ゲート絶縁膜2Gを形成する。 (2) スパツタ法を適用し、窒化モリブデン
(Mo2N)膜3を厚さ例えば3000〜5000〔Å〕程
度に形成する。 (3) 例えば化学気相成長法(CVD法)を適用
し、窒化シリコン(Si4N4)膜4を形成する。こ
の窒化シリコン膜4は窒化モリブデン膜3を還
元する場合のマスクとなるものであるから、そ
の厚さは水素(H2)が透過しない程度であれば
良い。 第2図参照 (4) フオト・レジスト膜(図示せず)を用いて窒
化シリコン膜4のパターニングを行なう。その
長さLはフオト・リソグラフイ技術にて可能な
2〔μm〕程度で良い。このときのエツチング
技術としてはドライ・エツチング法を適用する
ことが好ましい。 第3図参照 (5) 更に、例えばドライ・エツチング法を適用し
て窒化モリブデン膜3のパターニングを行な
う。 第4図参照 (6) 温度500〜900〔℃〕の水素雰囲気(還元性雰
囲気)中にて窒化モリブデン膜3の還元を行な
う。これは次式に依存して進行する。
The present invention relates to a method that is effective when applied to manufacturing a semiconductor device having fine electrodes and wiring made of a high melting point metal. In recent years, high melting point metals such as molybdenum (Mo) and tungsten (W) are often used for electrodes and wiring. The reasons for this are that these metal materials have lower resistance than polycrystalline silicon, which contributes to higher speed devices, that they have excellent processability, such as the ability to perform precise patterning, and that after forming electrodes and wiring, The main requirement is that it can sufficiently withstand the heat treatment temperature of . By the way, in general, photolithography technology that uses ultraviolet light is often used to form electrode and wiring patterns, but when using this technology, the range in which patterns can be miniaturized with good reproducibility is said to be up to 2 [μm]. ing. The present invention enables the formation of electrodes and wiring made of high-melting point metals such as Mo, W, titanium (Ti), tantalum (Ta), niobium (Nb), and hafnium (Hf) in fine patterns with good reproducibility. This will be explained in detail below. Figures 1 to 7 show MIS as an embodiment of the present invention.
This represents the process of forming a gate electrode of a field effect semiconductor device, and will be described next with reference to these figures. Refer to FIG. 1 (1) A field insulating film 2 and a gate insulating film 2G are formed on a silicon semiconductor substrate 1 having one conductivity type, for example, an n-type, by applying a conventional technique. (2) Applying a sputtering method, a molybdenum nitride (Mo 2 N) film 3 is formed to a thickness of, for example, about 3000 to 5000 [Å]. (3) For example, a chemical vapor deposition method (CVD method) is applied to form a silicon nitride (Si 4 N 4 ) film 4. Since this silicon nitride film 4 serves as a mask for reducing the molybdenum nitride film 3, its thickness may be sufficient as long as it does not allow hydrogen (H 2 ) to pass through. Refer to FIG. 2 (4) Pattern the silicon nitride film 4 using a photoresist film (not shown). The length L may be approximately 2 [μm], which is possible using photolithography technology. As the etching technique at this time, it is preferable to apply a dry etching method. Refer to FIG. 3 (5) Furthermore, the molybdenum nitride film 3 is patterned by applying, for example, a dry etching method. Refer to FIG. 4 (6) The molybdenum nitride film 3 is reduced in a hydrogen atmosphere (reducing atmosphere) at a temperature of 500 to 900 [°C]. This proceeds depending on the equation:

【表】 還元層3REDの厚さWはH2の拡散に依り決定
される為、時間で制御することができる。第8
図は厚さWと還元時間tとの関係を表わす線図
である。 第5図参照 (7) 所望時間の還元が終了した後、窒化シリコン
膜4を除去する。 第6図参照 (8) 燐酸系エツチング液或いはフエリシアン化カ
リ系エツチング液を用いて還元層3RED即ちモ
リブデン層のエツチングを行なう。この場合、
窒化モリブデンのエツチング・レートはモリブ
デンのそれに比較して極めて小さく、選択比は
充分に採れる。第9図はモリブデンと窒化モリ
ブデンのエツチング・レートを比較して示す線
図である。 第7図参照 (9) 再度還元を行なうと窒化モリブデン膜3がモ
リブデン・ゲート電極3Gとなるものである。
モリブデン・ゲート電極3Gの長さL′は2−
2W〔μm〕であり、これを例えば1〔μm〕
とするには前記工程(6)の還元時間tを制御する
ことに依つて容易に達成される。 以上の工程の後、通常のMIS電界効果半導体装
置の製法に従つて、モリブデン・ゲート電極3G
及びフイールド用絶縁膜2をマスクとするドナー
不純物(燐又は砒素)のイオン注入あるいは拡散
を行いn型ソース領域,ドレイン領域を形成する
(図示せず)。そして更に通常の製法に従つて、ソ
ース電極,ドレイン電極等の導出,配線の形成を
行う。 以上の説明で判るように、本発明に依れば、高
融点金属の電極・配線を有する半導体装置を製造
するにあたり、先ず高融点金属窒化物膜を形成
し、それを通常のフオート・リソグラフイ技術で
パターニングし、パターニングされた窒化物膜の
周辺を一部還元して窒化物よりエツチング・レー
トが著しく大である高融点金属そのものとしてか
ら、その高融点金属のみを除去し、最後に残つた
窒化物膜を還元して微細パターンの高融点金属か
らなる電極・配線を得ることができる。尚、本発
明を実施する場合、窒化モリブデンをパターニン
グするマスクを遠紫外光(deep UV)、電子ビー
ム、X線などで形成すれば更に微細化することが
可能である。 いずれにせよ本発明では高融点金属の窒化物を
還元する時間のみ制御すれば電極・配線パターン
の微細化をなし得るのでその実施は容易である。
[Table] Since the thickness W of the reduced layer 3 RED is determined by the diffusion of H 2 , it can be controlled by time. 8th
The figure is a diagram showing the relationship between thickness W and reduction time t. See FIG. 5 (7) After completion of the reduction for a desired time, the silicon nitride film 4 is removed. Refer to FIG. 6 (8) Etch the reduced layer 3 RED , that is, the molybdenum layer, using a phosphoric acid-based etching solution or a potassium ferricyanide-based etching solution. in this case,
The etching rate of molybdenum nitride is extremely small compared to that of molybdenum, and a sufficient selectivity can be achieved. FIG. 9 is a diagram comparing the etching rates of molybdenum and molybdenum nitride. Refer to FIG. 7 (9) When the reduction is performed again, the molybdenum nitride film 3 becomes a molybdenum gate electrode 3G.
The length L' of the molybdenum gate electrode 3G is 2-
2W [μm], for example, 1 [μm]
This can be easily achieved by controlling the reduction time t in step (6). After the above steps, the molybdenum gate electrode 3G is
Then, using the field insulating film 2 as a mask, donor impurity (phosphorus or arsenic) is ion-implanted or diffused to form an n-type source region and a drain region (not shown). Further, according to a conventional manufacturing method, a source electrode, a drain electrode, etc. are derived, and wiring is formed. As can be seen from the above description, according to the present invention, in manufacturing a semiconductor device having electrodes and wiring made of a high melting point metal, a high melting point metal nitride film is first formed, and then the film is processed using normal photolithography. The patterned nitride film is patterned using technology, and the periphery of the patterned nitride film is partially reduced to become the high-melting point metal itself, which has a significantly higher etching rate than nitride, and then only the high-melting point metal is removed, and the remaining nitride film is removed. By reducing the nitride film, fine patterns of electrodes and wiring made of high melting point metal can be obtained. When carrying out the present invention, further miniaturization is possible by forming a mask for patterning molybdenum nitride using deep UV light, an electron beam, X-rays, or the like. In any case, the present invention is easy to implement because the electrode/wiring pattern can be made finer by controlling only the time for reducing the nitride of the high melting point metal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第7図は本発明をゲート電極の形成
に適用した場合を説明するための工程要所に於け
る半導体装置の要部側断面図、第8図は還元と時
間の関係を表わす線図、第9図はエツチング・レ
ートの関係を表わす線図である。 図に於いて、1は基板、2はフイールド用絶縁
膜、2Gはゲート絶縁膜、3は窒化モリブデン
膜、3REDは還元層、3Gはゲート電極、4は窒
化シリコン膜である。
1 to 7 are side sectional views of main parts of a semiconductor device at key points in the process to explain the case where the present invention is applied to the formation of a gate electrode, and FIG. 8 shows the relationship between reduction and time. FIG. 9 is a diagram showing the relationship between etching rates. In the figure, 1 is a substrate, 2 is a field insulating film, 2G is a gate insulating film, 3 is a molybdenum nitride film, 3RED is a reduction layer, 3G is a gate electrode, and 4 is a silicon nitride film.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上に高融点金属窒化物膜を形成
し、該窒化物膜をパターニング後その周辺一部を
還元し高融点金属となしてから除去し、残留して
いる微細パターンの窒化物膜を還元して高融点金
属の電極・配線とする工程が含まれることを特徴
とする半導体装置の製造方法。
1. A high melting point metal nitride film is formed on a semiconductor substrate, and after patterning the nitride film, a part of its periphery is reduced to form a high melting point metal and then removed, and the remaining fine patterned nitride film is removed. A method for manufacturing a semiconductor device, comprising a step of reducing the metal to form electrodes and wiring of a high melting point metal.
JP15831079A 1979-12-06 1979-12-06 Preparation of semiconductor device Granted JPS5680144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15831079A JPS5680144A (en) 1979-12-06 1979-12-06 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15831079A JPS5680144A (en) 1979-12-06 1979-12-06 Preparation of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5680144A JPS5680144A (en) 1981-07-01
JPS6148262B2 true JPS6148262B2 (en) 1986-10-23

Family

ID=15668826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15831079A Granted JPS5680144A (en) 1979-12-06 1979-12-06 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5680144A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829363A (en) * 1984-04-13 1989-05-09 Fairchild Camera And Instrument Corp. Structure for inhibiting dopant out-diffusion
US4640004A (en) * 1984-04-13 1987-02-03 Fairchild Camera & Instrument Corp. Method and structure for inhibiting dopant out-diffusion

Also Published As

Publication number Publication date
JPS5680144A (en) 1981-07-01

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