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JPS6148288B2 - - Google Patents
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JPS6148288B2 - - Google Patents

Info

Publication number
JPS6148288B2
JPS6148288B2 JP1447779A JP1447779A JPS6148288B2 JP S6148288 B2 JPS6148288 B2 JP S6148288B2 JP 1447779 A JP1447779 A JP 1447779A JP 1447779 A JP1447779 A JP 1447779A JP S6148288 B2 JPS6148288 B2 JP S6148288B2
Authority
JP
Japan
Prior art keywords
circuit
stage
feedback
channel length
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1447779A
Other languages
Japanese (ja)
Other versions
JPS55107309A (en
Inventor
Toshiaki Nagaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1447779A priority Critical patent/JPS55107309A/en
Publication of JPS55107309A publication Critical patent/JPS55107309A/en
Publication of JPS6148288B2 publication Critical patent/JPS6148288B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34Negative-feedback-circuit arrangements with or without positive feedback
    • H03F1/342Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明は複数個の電界効果トランジスタを縦続
接続して構成される帰還回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a feedback circuit configured by cascading a plurality of field effect transistors.

従来、帰還回路はNチヤンネルMOSFET(金
属酸化シリコン電界効果トランジスタ)とPチヤ
ンネルMOSFETとのゲート電極を共通に接続
し、一方ドレイン電極同志を共通に接続してこれ
を出力とする所謂インバータ回路(C―MOS増
幅回路)を形成し、このインバータ回路(C―
MOS増幅回路)を複数段縦続接続することによ
り多段増幅回路を形成し、初段のインバータ回路
のゲート入力端子に入力インピーダンス素子を介
して入力信号を加え、最後段のインバータ回路の
ドレイン電極から出力を取り出し、これを帰還イ
ンピーダンス素子を介して初段のインバータ回路
のゲート入力端子に帰還せしめることによつて構
成されていた。即ち、通常のC―MOS増幅回路
の1段当りの電圧利得は約10〜20倍(通常、チヤ
ンネル長7〜8μ)であるため、高電圧利得の増
幅回路を得るためには、このインバータ回路を多
段縦続接続して使用しなければならなかつた。し
かしながら、C―MOS回路は比較的大きな占有
面積を必要とするため、インバータ回路を数多く
使用することは半導体基板上での占有面積が大き
くなり、このため高価格となり経済的に非常に不
利である。又、この様な増幅回路を用いて負帰還
回路を形成した場合、帰還率が大きくなつて高周
波帯域での自励発振を起こしてしまう。このため
高周波帯域での自励発振をおさえるために帰還回
路に周波数特性をもたせて高周波での出力利得を
小さくすることが考えられる。しかしながら、こ
のような場合、帰還インピーダンス素子として大
容量素子が必要とされ、一つの集積回路基板内に
集積化しにくく、又外付けする場合にはそれだけ
価格が高くなるという欠点があつた。
Conventionally, a feedback circuit is a so-called inverter circuit (C -MOS amplifier circuit) and this inverter circuit (C-
A multi-stage amplifier circuit is formed by cascading multiple stages of MOS amplifier circuits, an input signal is applied to the gate input terminal of the first stage inverter circuit via an input impedance element, and an output is output from the drain electrode of the last stage inverter circuit. It was constructed by taking out the inverter and feeding it back to the gate input terminal of the first stage inverter circuit via a feedback impedance element. In other words, since the voltage gain per stage of a normal C-MOS amplifier circuit is approximately 10 to 20 times (usually channel length 7 to 8 μ), this inverter circuit is required to obtain an amplifier circuit with high voltage gain. had to be used in multi-stage cascade connection. However, since C-MOS circuits require a relatively large area, using a large number of inverter circuits occupies a large area on the semiconductor substrate, resulting in high prices, which is extremely disadvantageous economically. . Furthermore, when a negative feedback circuit is formed using such an amplifier circuit, the feedback factor becomes large and self-sustained oscillation occurs in a high frequency band. Therefore, in order to suppress self-oscillation in the high frequency band, it is possible to give the feedback circuit a frequency characteristic to reduce the output gain at high frequencies. However, in such a case, a large capacitance element is required as the feedback impedance element, which is difficult to integrate on one integrated circuit board, and when it is externally attached, the cost increases accordingly.

本発明の目的は、上記欠点をなくし、低価格の
帰還回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a low-cost feedback circuit.

上記目的を達成するため、本発明の帰還回路は
出力段としての最後段のインバータ回路を形成す
るC―MOSFETの各FETのソース・ドレイン間
のチヤンネルの長さよりも、出力段に縦続接続さ
れる他段のうち少くとも1つのC―MOSFETの
各FETのチヤンネル長さを長くすることを特徴
とする。
In order to achieve the above object, the feedback circuit of the present invention is connected in cascade to the output stage with a length longer than the channel length between the source and drain of each FET of the C-MOSFET forming the last stage inverter circuit as the output stage. It is characterized by increasing the channel length of each FET of at least one C-MOSFET in the other stages.

以下、図面を参照して本発明の帰還回路の一実
施例を負帰還回路を用いて詳細に説明する。
Hereinafter, one embodiment of the feedback circuit of the present invention will be described in detail using a negative feedback circuit with reference to the drawings.

第1図は本実施例を示す回路図である。尚、説
明を簡単にするために本実施例においてはC―
MOSインバータ回路を3段縦続接続した例を提
示した。
FIG. 1 is a circuit diagram showing this embodiment. In addition, in order to simplify the explanation, in this example, C--
An example of cascading three stages of MOS inverter circuits was presented.

同図より、本実施例の負帰還回路はPチヤンネ
ルMOSFETとNチヤンネルMOSFETとのゲート
電極を共通に接続しこれを入力端とし、ドレイン
電極同志を共通に接続しこれを出力端とし、夫々
のソース電極を電源(VDD)及び接地に接続した
構造のC―MOSインバータ回路3,4,5の入
力端と出力端との相互に接続した3段縦続形式の
増幅回路と、初段のインバータ回路3のゲート電
極と入力端子1との間の入力インピーダンス素子
iとしての抵抗Riと、初段のインバータ回路3
のゲート電極(入力段)と最後段のインバータ回
路のドレイン電極(出力段)との間の帰還通路に
設けられた帰還素子Zfとして抵抗Rfとコンデン
サCfとの直列接続手段とにより構成される。
尚、初段及び2段目のC―MOSFETのチヤンネ
ル長(約15μ以上)を3段目のC―MOSFETの
チヤンネル長(約7〜8μ)よりも長く設定して
いる。この様に初段及び2段目のMOSFETのレ
ース・ドレイン間のチヤンネル長を長くするとチ
ヤンネルの飽和抵抗rds(=ΔVDS/ΔIDS;V
DS≧VG−VT)が大きくなり、ソース・ドレイン
間電圧の変動に伴う空乏層の影響も少なくなる。
従つて、長いチヤンネル長で形成されるC―
MOSインバータ増幅回路の1段当たりの電圧利
得は、第2図に示すようにチヤンネルの長さを長
くする程高くなる。
From the figure, the negative feedback circuit of this embodiment connects the gate electrodes of the P-channel MOSFET and N-channel MOSFET in common and uses this as the input terminal, and connects the drain electrodes in common and uses this as the output terminal. A three-stage cascade type amplifier circuit in which the input terminals and output terminals of C-MOS inverter circuits 3, 4, and 5 are connected to each other and the source electrodes are connected to the power supply (V DD ) and ground, and the first stage inverter circuit. A resistor R i as an input impedance element Z i between the gate electrode of No. 3 and input terminal 1, and the first stage inverter circuit 3
The feedback element Z f is provided in the feedback path between the gate electrode (input stage) of the inverter circuit and the drain electrode (output stage) of the last stage inverter circuit, and is composed of a series connection means of a resistor R f and a capacitor C f . be done.
Note that the channel lengths of the first and second stage C-MOSFETs (approximately 15 μm or more) are set longer than the channel lengths of the third stage C-MOSFETs (approximately 7 to 8 μm). In this way, by increasing the channel length between the race and drain of the first and second stage MOSFETs, the saturation resistance of the channel r ds (=ΔV DS /ΔI DS ;V
DS ≧V G −V T ) increases, and the influence of the depletion layer due to fluctuations in the source-drain voltage also decreases.
Therefore, C- formed with a long channel length.
The voltage gain per stage of the MOS inverter amplifier circuit increases as the length of the channel increases, as shown in FIG.

第2図はC―MOSインバータ回路1段で構成
した増幅回路における、チヤンネル長L〔μ〕の
変化とそれに伴う電圧利得の変化を示した図であ
る。尚、インバータ回路を構成するPチヤンネル
FET、NチヤンネルFETの夫々のチヤンネル長
は長さを等しくしている。
FIG. 2 is a diagram showing changes in channel length L [μ] and accompanying changes in voltage gain in an amplifier circuit configured with one stage of C-MOS inverter circuits. In addition, the P channel that constitutes the inverter circuit
The channel lengths of the FET and N-channel FET are made equal.

同図からも明らかなように、チヤンネル長10μ
の時、電圧利得は約13倍、20μの時約85倍、30μ
の時約150倍、60μの時約170倍となつている。従
つて本実施例のように増幅回路としてチヤンネル
長の長い(約15μ以上、場合によつては30μ,50
μとするも可)MOSFETを使用することによつ
て、少ない接続段数で高い電圧利得を有する増幅
回路を得ることができる。
As is clear from the figure, the channel length is 10μ.
When , the voltage gain is about 13 times, when it is 20μ, it is about 85 times, and when it is 30μ
It is about 150 times when it is , and about 170 times when it is 60μ. Therefore, as in this embodiment, the amplifier circuit has a long channel length (approximately 15μ or more, in some cases 30μ, 50μ or more).
By using MOSFETs, it is possible to obtain an amplifier circuit with a high voltage gain with a small number of connected stages.

更に、チヤンネル長が長くなる程、回路の高周
波特性が下がるため、高電圧利得動作させても高
周波帯域における自励発振を防止することがで
き、帰還インピーダンス素子Cfを省略すること
もできる。
Furthermore, the longer the channel length, the lower the high frequency characteristics of the circuit, so self-oscillation in the high frequency band can be prevented even in high voltage gain operation, and the feedback impedance element C f can be omitted.

ここで、チヤンネル長の長いMOSFETで増幅
回路を形成した場合、電圧利得は上がるが、相互
コンダクタンスGnが低下するため、出力インピ
ーダンスが高くなり、帰還電圧に変動が生じ良好
な帰還回路を得ることが困難になる。しかしなが
ら本実施例のように最後段に位置するC―MOS
インバータ回路のチヤンネル長を短かくすること
によつて相互コンダクタンスを大きくし、出力イ
ンピーダンスを下げ、高電圧利得で帰還出力電圧
変動の少ない負帰還回路を得ることができる。
Here, if an amplifier circuit is formed using MOSFETs with a long channel length, the voltage gain will increase, but the mutual conductance G n will decrease, so the output impedance will increase and the feedback voltage will fluctuate, making it difficult to obtain a good feedback circuit. becomes difficult. However, as in this example, the C-MOS located at the last stage
By shortening the channel length of the inverter circuit, mutual conductance can be increased, output impedance can be lowered, and a negative feedback circuit with high voltage gain and less feedback output voltage fluctuation can be obtained.

この様に、本発明によれば増幅回路を構成する
C―MOSインバータ回路のチヤンネル長を長く
し、飽和抵抗rdsを高め、少ない接続段数で高い
電圧利得を得ることができるとともに、高周波帯
域における自動発振を防止でき、しかも出力段
(最後段)のインバータ回路のチヤンネル長を他
のチヤンネル長より短かく形成することによつ
て、出力インピーダンスの小さい、帰還電圧変動
の少ない安定した負帰還回路を得ることができ
る。
As described above, according to the present invention, the channel length of the C-MOS inverter circuit constituting the amplifier circuit can be increased, the saturation resistance r ds can be increased, and high voltage gain can be obtained with a small number of connection stages. By making the channel length of the output stage (last stage) inverter circuit shorter than other channel lengths, we can create a stable negative feedback circuit with low output impedance and less feedback voltage fluctuation. Obtainable.

尚、本実施例では3段縦続した増幅回路を負帰
還回路に適用した例を提示したが、この接続段数
は任意自由に設定できるものである。又、最後段
のインバータ回路のチヤンネルの長さより長いチ
ヤンネル長を有するインバータ回路を少なく共1
個以上有していれば本発明の効果は得られるもの
であり、この構成のもとで各インバータ回路のチ
ヤンネル長は自由にその長さを設定してよい。更
に、増幅回路としてはC―MOSFETの他接合型
FETでもよい。又、本実施例では負帰還回路を
提示したが、本発明の構成で正帰還回路を作るこ
ともでき、更に負帰還回路を形成した場合入力段
のインピーダンス素子(抵抗Ri)として一端を
接地し、他端を初段CMOSFETのゲートに接続
することもできる。
Although this embodiment has presented an example in which three stages of amplifier circuits are applied to the negative feedback circuit, the number of connected stages can be set arbitrarily. In addition, at least one inverter circuit having a channel length longer than that of the last stage inverter circuit is used.
The effects of the present invention can be obtained if the number of inverter circuits is greater than 1, and the channel length of each inverter circuit may be set freely under this configuration. Furthermore, as an amplifier circuit, C-MOSFET other junction type is used.
FETs may also be used. Further, although a negative feedback circuit is presented in this embodiment, a positive feedback circuit can also be created with the configuration of the present invention. Furthermore, when a negative feedback circuit is formed, one end can be grounded as an impedance element (resistance R i ) in the input stage. However, the other end can also be connected to the gate of the first stage CMOSFET.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す負帰還回路の
回路図で、第2図は1段当りのC―MOSインバ
ータ増幅回路のチヤンネル長と電圧利得との関係
を表わす図である。 1……入力端子、2……出力端子、3,4,5
……C―MOSインバータ回路、Zi……入力イン
ピーダンス素子、Zf……帰還インピーダンス素
子、Ri,Rf……抵抗、Cf……コンデンサ。
FIG. 1 is a circuit diagram of a negative feedback circuit showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between channel length and voltage gain of a C-MOS inverter amplifier circuit per stage. 1...Input terminal, 2...Output terminal, 3, 4, 5
...C-MOS inverter circuit, Z i ...input impedance element, Z f ...feedback impedance element, R i , R f ...resistor, C f ... capacitor.

Claims (1)

【特許請求の範囲】[Claims] 1 P型及びN型電界効果トランジスタを含む相
補型回路を複数段継続接続し、初段の前記相補型
回路の入力部と最後段の出力部との間に帰還を施
した帰還回路において、前記最後段に位置する前
記電界効果トランジスタのチヤンネル長は他段を
構成する電界効果トランジスタのいづれかのもの
のチヤンネル長より短かいことを特徴とする帰還
回路。
1. In a feedback circuit in which a plurality of stages of complementary circuits including P-type and N-type field effect transistors are continuously connected, and feedback is provided between the input part of the complementary circuit in the first stage and the output part in the last stage, A feedback circuit characterized in that the channel length of the field effect transistor located in one stage is shorter than the channel length of any of the field effect transistors constituting other stages.
JP1447779A 1979-02-09 1979-02-09 Feedback circuit Granted JPS55107309A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1447779A JPS55107309A (en) 1979-02-09 1979-02-09 Feedback circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1447779A JPS55107309A (en) 1979-02-09 1979-02-09 Feedback circuit

Publications (2)

Publication Number Publication Date
JPS55107309A JPS55107309A (en) 1980-08-18
JPS6148288B2 true JPS6148288B2 (en) 1986-10-23

Family

ID=11862134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1447779A Granted JPS55107309A (en) 1979-02-09 1979-02-09 Feedback circuit

Country Status (1)

Country Link
JP (1) JPS55107309A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446444A (en) * 1981-02-05 1984-05-01 Harris Corporation CMOS Amplifier
US7227414B2 (en) * 2003-06-27 2007-06-05 Intel Corporation Apparatus for receiver equalization

Also Published As

Publication number Publication date
JPS55107309A (en) 1980-08-18

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