JPS6148666B2 - - Google Patents
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- Publication number
- JPS6148666B2 JPS6148666B2 JP12218678A JP12218678A JPS6148666B2 JP S6148666 B2 JPS6148666 B2 JP S6148666B2 JP 12218678 A JP12218678 A JP 12218678A JP 12218678 A JP12218678 A JP 12218678A JP S6148666 B2 JPS6148666 B2 JP S6148666B2
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- circuit
- zero point
- generates
- output
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- 238000001514 detection method Methods 0.000 claims description 28
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
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- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
この発明は例えば電源周波数が50Hzであるか60
Hzであるかを判別するための周波数判別回路に関
するものである。[Detailed Description of the Invention] [Technical Field] This invention is applicable to
This invention relates to a frequency discrimination circuit for determining whether the frequency is Hz or not.
従来例として、特開昭51−976号公報に開示さ
れた自動周波数判別回路がある。この自動周波数
判別回路は、直流電源によつてコンデンサを測定
すべき周波数の電圧の零点からコンデンサの充電
電圧が測定すべき周波数の電圧と一致する時間ま
で充電し、コンデンサの最終充電電圧を基準電圧
と比較することで周波数が50Hzか60Hzかを判別す
るように構成されていた。
As a conventional example, there is an automatic frequency discrimination circuit disclosed in Japanese Patent Laid-Open No. 51-976. This automatic frequency discrimination circuit charges a capacitor using a DC power supply from the zero point of the voltage at the frequency to be measured until the time when the charging voltage of the capacitor matches the voltage at the frequency to be measured, and then sets the final charging voltage of the capacitor to the reference voltage. It was configured to determine whether the frequency is 50Hz or 60Hz by comparing it with .
このような従来例においては、第７図に示すよ
うに、充電電圧波形Q1と50Hzまたは60Hzの交流
電圧波形Q2またはQ3との交点の充電電圧値R1ま
たはR2を基準電圧Ｓと比較するように構成して
いる。すなわち、異なる時刻t1，t2で電圧比較を
行つている。 In such a conventional example, as shown in FIG. 7, the charging voltage value R 1 or R 2 at the intersection of the charging voltage waveform Q 1 and the 50 Hz or 60 Hz AC voltage waveform Q 2 or Q 3 is set as the reference voltage S. It is configured to compare with. That is, voltage comparison is performed at different times t 1 and t 2 .
このように構成すると、50Hz交流電圧波形Q2
と充電電圧波形Q1との交点の充電電圧値R1と60
Hzの交流電圧波形Q3と充電電圧波形Q1との交点
の充電電圧値R2との差D2が小さくなり、充電電
圧値R1，R2間の電圧に設定する必要がある基準
電圧Ｓの設定範囲が狭くなり、充電回路の抵抗、
コンデンサ等のばらつきを考えると基準電圧Ｓの
設定がきわめて困難である。 With this configuration, the 50Hz AC voltage waveform Q 2
The charging voltage value R 1 and 60 at the intersection of and the charging voltage waveform Q 1
The difference D 2 between the charging voltage value R 2 at the intersection of the Hz AC voltage waveform Q 3 and the charging voltage waveform Q 1 becomes small, and the reference voltage needs to be set to a voltage between the charging voltage values R 1 and R 2 . The setting range of S becomes narrower, and the resistance of the charging circuit,
Considering variations in capacitors, etc., setting the reference voltage S is extremely difficult.
この発明の目的は、周波数判別のための基準電
圧を容易に設定することができる周波数判別回路
を提供することである。
An object of the present invention is to provide a frequency discrimination circuit that can easily set a reference voltage for frequency discrimination.
第１の発明の周波数判別回路は、被判別信号の
零点を検出してパルスを発生する零点検出回路
と、この零点検出回路がパルスを発生した後所定
時間経過した時の基準周波数信号の瞬時値と前記
被判別信号の瞬時値とを比較して前記被判別信号
の瞬時値が大きいときに出力を発生する比較器
と、この比較器の出力を前記零点検出回路がパル
スを発生した後前記所定時間経過した時に通過さ
せるゲート回路とを備えている。
The frequency discrimination circuit of the first invention includes a zero point detection circuit that detects the zero point of the signal to be discriminated and generates a pulse, and an instantaneous value of the reference frequency signal when a predetermined time has elapsed after the zero point detection circuit generates the pulse. and an instantaneous value of the signal to be determined and generates an output when the instantaneous value of the signal to be determined is large; It also includes a gate circuit that allows the passage of time to pass.
この第１の発明の構成によれば、零点検出回路
がパルスを発生した後所定時間経過した時の基準
周波数信号の瞬時値と被判別信号の瞬時値とを比
較器で比較し、この比較器の出力を、零点検出回
路がパルスを発生した後所定時間経過した時にゲ
ート回路を通過させることになる。 According to the configuration of the first invention, the comparator compares the instantaneous value of the reference frequency signal and the instantaneous value of the signal to be discriminated when a predetermined period of time has elapsed after the zero point detection circuit generates a pulse. The output is passed through the gate circuit when a predetermined period of time has elapsed after the zero point detection circuit generated the pulse.
第２の発明の周波数判別回路は、被判別信号の
零点を検出してパルスを発生する零点検出回路
と、前記被判別信号を積分する積分回路と、前記
零点検出回路がパルスを発生した後所定時間経過
した時の基準周波数信号の積分信号の瞬時値と前
記積分回路の出力瞬時値とを比較して前記積分回
路の出力瞬時値が大きいときに出力を発生する比
較器と、この比較器の出力を前記零点検出回路が
パルスを発生した後前記所定時間経過した時に通
過させるゲート回路とを備えている。 The frequency discrimination circuit of the second invention includes a zero point detection circuit that detects the zero point of the signal to be discriminated and generates a pulse, an integrating circuit that integrates the signal to be discriminated, and a predetermined frequency after the zero point detection circuit generates the pulse. a comparator that compares the instantaneous value of the integral signal of the reference frequency signal over time and the instantaneous output value of the integrating circuit and generates an output when the instantaneous output value of the integrating circuit is large; and a gate circuit that allows the output to pass when the predetermined time has elapsed after the zero point detection circuit generated the pulse.
この第２の発明の構成によれば、被判別信号を
そのまま比較するのではなく、積分したのち、基
準周波数信号の瞬時値と比較することになる。 According to the configuration of the second invention, the signals to be determined are not compared as they are, but are integrated and then compared with the instantaneous value of the reference frequency signal.
実施例
この発明の第１の実施例を第１図および第２図
に基づいて説明する。この周波数判別回路は、第
１図に示すように、被判別信号Ａの零点を検出し
てパルスを発生する零点検出回路４と、この零点
検出回路４がパルスを発生した後所定時間T1が
経過した時の基準周波数信号Ｅの瞬時値Ｂと前記
被判別信号Ａの瞬時値とを比較して前記被判別信
号Ａの瞬時値が大きいときに出力を発生する比較
器７と、この比較器７の出力を前記零点検出回路
４がパルスを発生した後前記所定時間T1が経過
した時に通過させるゲート回路８とを備えてい
る。Embodiment A first embodiment of the present invention will be described based on FIGS. 1 and 2. As shown in FIG. 1, this frequency discrimination circuit includes a zero point detection circuit 4 that detects the zero point of the signal A to be discriminated and generates a pulse, and a predetermined time period T1 after the zero point detection circuit 4 generates the pulse. a comparator 7 that compares the instantaneous value B of the reference frequency signal E over time with the instantaneous value of the signal to be determined A and generates an output when the instantaneous value of the signal to be determined A is large; and this comparator 7 is provided with a gate circuit 8 which allows the output of 7 to pass when the predetermined time T1 has elapsed after the zero point detection circuit 4 generates a pulse.
この場合、被判別信号Ａは、交流電源１の電圧
をトランス２で降圧し、さらにトランス２の２次
電圧を全波整流器３で整流して作つており、零点
検出回路４は、全波整流器３の出力の零点を検出
してパルスを発生することになる。 In this case, the signal A to be determined is created by stepping down the voltage of the AC power supply 1 with a transformer 2, and further rectifying the secondary voltage of the transformer 2 with a full-wave rectifier 3. A pulse is generated by detecting the zero point of the output of step 3.
また、ゲート回路８は、単安定マルチバイブレ
ータ８ａ、インバータ８ｂおよびアンドゲート８
ｃからなり、単安定マルチバイブレータ８ａは、
零点検出回路４の出力パルスによりトリガされ、
パルス幅が所定時間T1に等しいパルスを発生
し、アンドゲート８ｃは単安定マルチバイブレー
タ８ａの反転出力により単安定マルチバイブレー
タ８ａの休止期間中開成状態となる。 Further, the gate circuit 8 includes a monostable multivibrator 8a, an inverter 8b, and an AND gate 8.
The monostable multivibrator 8a consists of c,
Triggered by the output pulse of the zero point detection circuit 4,
A pulse whose pulse width is equal to the predetermined time T1 is generated, and the AND gate 8c is kept open during the rest period of the monostable multivibrator 8a due to the inverted output of the monostable multivibrator 8a.
この周波数判別回路の動作を50Hzと60Hzを判別
する場合を例にとり第２図を参照して説明する。
まず、50Hzの周波数の交流電圧A1がこの周波数
判別回路に加えられた場合には、ゲート回路８が
開成している期間中において基準周波数信号Ｅの
瞬時値Ｂより50Hzの周波数の交流電圧A1の瞬時
値の方が大きい時があるため、比較器７の出力が
アンドゲート８ｃから出る。つぎに60Hzの周波数
の交流電圧A2がこの周波数判別回路に加えられ
た場合には、ゲート回路８が開成している期間中
において基準周波数信号Ｅの瞬時値Ｂより60Hzの
周波数の交流電圧A2の振幅の方が常に小さいた
め、比較器７の出力がなく、したがつてアンドゲ
ート８ｃの出力もない。なお、所定時間T1の選
び方によつてゲート回路８の出力状態が上述の説
明と逆になる場合もある。 The operation of this frequency discrimination circuit will be explained with reference to FIG. 2, taking as an example the case of discriminating between 50 Hz and 60 Hz.
First, when AC voltage A 1 with a frequency of 50 Hz is applied to this frequency discrimination circuit, the AC voltage A with a frequency of 50 Hz is lower than the instantaneous value B of the reference frequency signal E during the period when the gate circuit 8 is open. Since the instantaneous value of 1 is sometimes larger, the output of comparator 7 is output from AND gate 8c. Next, when an AC voltage A 2 with a frequency of 60 Hz is applied to this frequency discrimination circuit, the AC voltage A with a frequency of 60 Hz is lower than the instantaneous value B of the reference frequency signal E during the period when the gate circuit 8 is open. Since the amplitude of signal 2 is always smaller, there is no output from comparator 7, and therefore there is no output from AND gate 8c. Note that depending on how the predetermined time T 1 is selected, the output state of the gate circuit 8 may be opposite to that described above.
この実施例によれば、零点検出回路４がパルス
を発生した後所定時間T1が経過した時の基準周
波数信号Ｅの瞬時値Ｂと被判別信号Ａとを比較器
７で比較し、この比較器７の出力を、零点検出回
路４がパルスを発生した後所定時間T1が経過し
た時にゲート回路８を通過させる構成であるた
め、交流電源１の周波数が50Hzか60Hzかを簡単な
構成で判別することができる。しかも交流電圧１
の電圧波高値がいくら変化しても周波数さえ一定
であれば正確に判別することができる。また、こ
の実施例では、第６図に示すように、零点から
T1時間だけ経過した時刻t0における交流電圧の瞬
時値を基準電圧Ｂと比較するようにしている。 According to this embodiment, the comparator 7 compares the instantaneous value B of the reference frequency signal E and the signal A to be determined when a predetermined time T1 has elapsed after the zero point detection circuit 4 generates a pulse. Since the output of the generator 7 is configured to pass through the gate circuit 8 when a predetermined time T1 has elapsed after the zero point detection circuit 4 generates a pulse, it is possible to determine whether the frequency of the AC power source 1 is 50Hz or 60Hz with a simple configuration. can be determined. Moreover, AC voltage 1
No matter how much the voltage peak value changes, as long as the frequency is constant, it can be accurately determined. In addition, in this embodiment, as shown in FIG.
The instantaneous value of the AC voltage at time t 0 after T 1 hour has elapsed is compared with reference voltage B.
このように、所定の時刻t0の交流電圧の瞬時値
と基準電圧Ｂとを比較するように構成すると、周
波数が50Hzの場合の交流電圧A1の時刻t0の瞬時値
P1と60Hzの場合の交流電圧A2の時刻t0の瞬時値P2
との差D1が大きくなるため、瞬時値P1，P2間の
電圧に設定する必要がある基準電圧Ｂの設定範囲
が広くなり、基準電圧Ｂの設定が容易である。 In this way, when the instantaneous value of the AC voltage at a predetermined time t 0 is compared with the reference voltage B, the instantaneous value of the AC voltage A 1 at the time t 0 when the frequency is 50 Hz is obtained.
P 1 and the instantaneous value of AC voltage A 2 at time t 0 in the case of 60 Hz P 2
Since the difference D 1 between the instantaneous values P 1 and P 2 becomes larger, the setting range of the reference voltage B that needs to be set to a voltage between the instantaneous values P 1 and P 2 becomes wider, and the setting of the reference voltage B becomes easier.
この発明の第２の実施例を第３図ないし第５図
に基づいて説明する。この周波数判別回路は、第
３図に示すように、被判別信号Ａの零点を検出し
てパルスを発生する零点検出回路４と、前記被判
別信号Ａを積分する積分回路９と、前記零点検出
回路４がパルスを発生した後所定時間T2が経過
した時の基準周波数信号Ｅの積分信号Ｆの瞬時値
Ｄと前記積分回路９の出力Ｃの瞬時値とを比較し
て前記積分回路９の出力Ｃの瞬時値が大きいとき
に出力を発生する比較器７と、この比較器７の出
力を前記零点検出回路４がパルスを発生した後前
記所定時間T2が経過した時に通過させるゲート
回路８′とを備えている。 A second embodiment of the invention will be explained based on FIGS. 3 to 5. As shown in FIG. 3, this frequency discrimination circuit includes a zero point detection circuit 4 that detects the zero point of the signal A to be discriminated and generates a pulse, an integration circuit 9 that integrates the signal A to be discriminated, and a zero point detection circuit 4 that detects the zero point of the signal A to be discriminated and generates a pulse. The instantaneous value D of the integral signal F of the reference frequency signal E when a predetermined time T2 has elapsed after the circuit 4 generates a pulse is compared with the instantaneous value of the output C of the integrating circuit 9. A comparator 7 that generates an output when the instantaneous value of the output C is large, and a gate circuit 8 that allows the output of the comparator 7 to pass when the predetermined time T2 has elapsed after the zero point detection circuit 4 generates a pulse. ′.
この場合、被判別信号Ａは、第１図の実施例と
同様にして作り、零点検出回路４は、全波整流器
３の出力の零点を検出してパルスを発生すること
になり、積分回路９は全波整流器３の出力を積分
することになる。 In this case, the signal to be determined A is generated in the same manner as in the embodiment shown in FIG. will integrate the output of the full-wave rectifier 3.
また、ゲート回路８′は単安定マルチバイブレ
ータ８ａおよびアンドゲート８ｃからなり、単安
定マルチバイブレータ８ａは、零点検出回路４の
出力パルスによりトリガされ、パルス幅が所定時
間T1に等しいパルスを発生し、アンドゲート８
ｃは単安定マルチバイブレータ８ａの出力により
単安定マルチバイブレータ８ａの動作期間中開成
状態となる。 Further, the gate circuit 8' consists of a monostable multivibrator 8a and an AND gate 8c, and the monostable multivibrator 8a is triggered by the output pulse of the zero point detection circuit 4 and generates a pulse whose pulse width is equal to the predetermined time T1 . , and gate 8
c is in an open state during the operation period of the monostable multivibrator 8a due to the output of the monostable multivibrator 8a.
この周波数判別回路の動作を50Hzと60Hzを判別
する場合を例にとり第４図および第５図を参照し
て説明する。まず、50Hzの周波数の交流電圧A1
がこの周波数判別回路に加えられた場合には、ゲ
ート回路８′が開成している期間中において基準
周波数信号Ｅの積分電圧Ｆの瞬時値Ｄより積分回
路９の出力C1の瞬時値の方が常に小さいため、
比較器７の出力がなく、したがつて、アンドゲー
ト８ｃの出力もない。つぎに、60Hzの周波数の交
流電圧A2がこの周波数判別回路に加えられた場
合には、ゲート回路８′が開成している期間中に
おいて基準周波数信号Ｅの積分電圧Ｆの瞬時値Ｄ
より積分回路９の出力C2の瞬時値の方が大きい
時があるため、比較器７の出力がアンドゲート８
ｃから出る。 The operation of this frequency discrimination circuit will be explained with reference to FIGS. 4 and 5, taking as an example the case of discriminating between 50 Hz and 60 Hz. First, the alternating voltage A 1 with a frequency of 50Hz
is applied to this frequency discrimination circuit, the instantaneous value of the output C1 of the integrating circuit 9 is higher than the instantaneous value D of the integrated voltage F of the reference frequency signal E during the period when the gate circuit 8' is open. is always small, so
There is no output from comparator 7, and therefore there is no output from AND gate 8c. Next, when an AC voltage A 2 with a frequency of 60 Hz is applied to this frequency discrimination circuit, the instantaneous value D of the integrated voltage F of the reference frequency signal E is obtained during the period when the gate circuit 8' is open.
Since the instantaneous value of the output C2 of the integrator circuit 9 is sometimes larger, the output of the comparator 7 is
Exit from c.
この実施例は前述の実施例と同様の効果があ
り、特に波形が歪んでいる場合にも正確に判別で
きる。 This embodiment has the same effect as the previous embodiment, and can accurately discriminate even when the waveform is particularly distorted.
第１の発明の周波数判別回路によれば、被判別
信号の零点を検出してパルスを発生する零点検出
回路と、この零点検出回路がパルスを発生した後
所定時間経過した時の基準周波数信号の瞬時値と
前記被判別信号の瞬時値とを比較して前記被判別
信号の瞬時値が大きいときに出力を発生する比較
器と、この比較器の出力を前記零点検出回路がパ
ルスを発生した後前記所定時間経過した時に通過
させるゲート回路とを備えているので、高い周波
数および低い周波数の被判別信号の瞬時値の差が
基準電圧との比較時において大きくなり、両瞬時
値の間の電圧に設定する必要がある基準電圧の設
定範囲を広くでき、基準電圧の設定が容易にな
る。
According to the frequency discrimination circuit of the first invention, there is a zero point detection circuit that detects the zero point of the signal to be discriminated and generates a pulse, and a reference frequency signal detection circuit that detects the zero point of the signal to be discriminated and generates a pulse. a comparator that compares an instantaneous value with the instantaneous value of the signal to be determined and generates an output when the instantaneous value of the signal to be determined is large; and a comparator that outputs the output of the comparator after the zero point detection circuit generates a pulse. Since the gate circuit is provided with a gate circuit that allows the signal to pass when the predetermined time has elapsed, the difference between the instantaneous values of the high-frequency and low-frequency signals to be determined becomes large when compared with the reference voltage, and the voltage between the two instantaneous values increases. The setting range of the reference voltage that needs to be set can be widened, and the setting of the reference voltage becomes easy.
また、第２の発明の周波数判別回路によれば、
被判別信号の零点を検出してパルスを発生する零
点検出回路と、前記被判別信号を積分する積分回
路と、前記零点検出回路がパルスを発生した後所
定時間経過した時の基準周波数信号の積分信号の
瞬時値と前記積分回路の出力瞬時値とを比較して
前記積分回路の出力瞬時値が大きいときに出力を
発生する比較器と、この比較器の出力を前記零点
検出回路がパルスを発生した後前記所定時間経過
した時に通過させるゲート回路とを備えているの
で、第１発明の効果に加え、波形の歪に影響され
ることなくきわめて正確に周波数を判別できると
いう効果がある。 Further, according to the frequency discrimination circuit of the second invention,
a zero point detection circuit that detects the zero point of the signal to be discriminated and generates a pulse; an integrating circuit that integrates the signal to be discriminated; and an integration of the reference frequency signal when a predetermined time has elapsed after the zero point detection circuit generates the pulse. a comparator that compares the instantaneous value of the signal with the instantaneous output value of the integrating circuit and generates an output when the instantaneous output value of the integrating circuit is large; and the zero point detection circuit generates a pulse based on the output of the comparator. In addition to the effect of the first invention, there is an effect that the frequency can be determined very accurately without being affected by waveform distortion.
第１図はこの発明の第１の実施例の回路図、第
２図はその動作説明図、第３図はこの発明の第２
の実施例の回路図、第４図および第５図はそれぞ
れその動作説明図、第６図は実施例の効果の説明
図、第７図は従来例の欠点の説明図である。
１……交流電源、２……トランス、３……全波
整流器、４……零点検出回路、６……フリツプフ
ロツプ、７……比較器、８，８′……ゲート回
路、９……積分回路。
Fig. 1 is a circuit diagram of the first embodiment of the present invention, Fig. 2 is an explanatory diagram of its operation, and Fig. 3 is a circuit diagram of the first embodiment of the invention.
FIGS. 4 and 5 are circuit diagrams of the embodiment, respectively. FIGS. 4 and 5 are diagrams for explaining the operation thereof, FIG. 6 is a diagram for explaining the effects of the embodiment, and FIG. 7 is a diagram for explaining the drawbacks of the conventional example. 1... AC power supply, 2... Transformer, 3... Full wave rectifier, 4... Zero point detection circuit, 6... Flip-flop, 7... Comparator, 8, 8'... Gate circuit, 9... Integrating circuit .
Claims (1)
る零点検出回路と、この零点検出回路がパルスを
発生した後所定時間経過した時の基準周波数信号
の瞬時値と前記被判別信号の瞬時値とを比較して
前記被判別信号の瞬時値が大きいときに出力を発
生する比較器と、この比較器の出力を前記零点検
出回路がパルスを発生した後前記所定時間経過し
た時に通過させるゲート回路とを備えた周波数判
別回路。 ２ 被判別信号の零点を検出してパルスを発生す
る零点検出回路と、前記被判別信号を積分する積
分回路と、前記零点検出回路がパルスを発生した
後所定時間経過した時の基準周波数信号の積分信
号の瞬時値と前記積分回路の出力瞬時値とを比較
して前記積分回路の出力瞬時値が大きいときに出
力を発生する比較器と、この比較器の出力を前記
零点検出回路がパルスを発生した後前記所定時間
経過した時に通過させるゲート回路とを備えた周
波数判別回路。[Claims] 1. A zero point detection circuit that detects a zero point of a signal to be determined and generates a pulse, and an instantaneous value of a reference frequency signal when a predetermined time has elapsed after this zero point detection circuit generates a pulse, and the instantaneous value of the reference frequency signal and the a comparator that compares the instantaneous value of the discrimination signal with an instantaneous value of the signal to be discriminated and generates an output when the instantaneous value of the signal to be discriminated is large; and a comparator that generates an output when the instantaneous value of the signal to be discriminated is large; A frequency discrimination circuit including a gate circuit that allows the signal to pass through at certain times. 2. A zero point detection circuit that detects the zero point of the signal to be discriminated and generates a pulse, an integrating circuit that integrates the signal to be discriminated, and a reference frequency signal that is detected when a predetermined time has elapsed after the zero point detection circuit generates a pulse. a comparator that compares the instantaneous value of the integral signal with the instantaneous output value of the integral circuit and generates an output when the instantaneous output value of the integral circuit is large; and a gate circuit that allows the frequency to pass when the predetermined time has elapsed after the occurrence of the frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12218678A JPS5547458A (en) | 1978-09-30 | 1978-09-30 | Frequency discriminator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12218678A JPS5547458A (en) | 1978-09-30 | 1978-09-30 | Frequency discriminator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5547458A JPS5547458A (en) | 1980-04-03 |
| JPS6148666B2 true JPS6148666B2 (en) | 1986-10-25 |
Family
ID=14829697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12218678A Granted JPS5547458A (en) | 1978-09-30 | 1978-09-30 | Frequency discriminator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5547458A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126630U (en) * | 1981-01-31 | 1982-08-06 | ||
| JP2595171B2 (en) * | 1992-08-19 | 1997-03-26 | 鹿島建設株式会社 | Resonance prevention device of position measuring device for underground wall excavator |
-
1978
- 1978-09-30 JP JP12218678A patent/JPS5547458A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5547458A (en) | 1980-04-03 |
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