JPS6149033B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a welding current balance monitoring device for monitoring the balance between positive and negative welding currents in a resistance welding machine or the like.

Generally, in the case of a resistance welding machine, such as a seam welding machine, the welding current is turned on and off at intervals of several cycles. A welding current balance monitoring device is used to detect when the welding current has collapsed or to cause one-sided ignition, and to stop the current supply to protect the main thyristor for controlling the welding output, as well as to prevent welding defects. ing.

Conventionally, as such a welding current balance monitoring device, one using a meter relay as shown in FIG. 1 has been used. In FIG. 1, 1 is a meter relay, and lines 2 and 3 are connected to a shunt for detecting welding current. 4 is a control block for this meter relay 1, and when the current balance is disrupted, the relay 5 operates and its contact 5a
becomes open, and power supply etc. stops. 6 is a reset push button switch.

However, since the meter relay 1 is mechanical, it has poor response.
It takes several cycles to operate after detecting that the balance has been lost, and the detection accuracy is low.
Moreover, it is not possible to adjust the accuracy arbitrarily,
There was also large variation in accuracy. Furthermore, it was expensive and had poor reliability.

The present invention is intended to solve these conventional drawbacks, and aims to provide fast response, high detection accuracy, and the ability to arbitrarily set the accuracy.

2 to 4 show a welding current balance monitoring device for a resistance welding machine according to an embodiment of the present invention, and FIG. 2 shows an amplifier circuit, a sample hold circuit,
A window comparator circuit for detecting upper and lower limits, a display circuit section, FIG. 3 shows a sampling circuit and a synchronization circuit section, and FIG. 4 shows a set/reset circuit section in case of imbalance.

In FIG. 2, 10 is a welding transformer;
Main thyristors 11 and 12 and a shunt 13 are connected to the primary side of this welding transformer 10, and the shunt 13 can detect the positive magnitude and negative magnitude of the welding current.

14 is a current differential type Norton type operational amplifier (hereinafter referred to as an operational amplifier), and the detection voltage detected by the shunt 13 is input to an inverting input terminal and a non-inverting input terminal of this operational amplifier 14. 14 to 20 are resistors for input, output, and bias of this operational amplifier 14; 21 is a capacitor;
20 and a capacitor 21 constitute an amplifier circuit.

22 is a capacitor that holds the positive magnitude of the amplified voltage obtained from the operational amplifier 14; 23;
is a capacitor that similarly holds a negative magnitude, and the capacitors 22 and 23 have diodes 24 and 25, and the cathode of the diode 24 is on the capacitor 22 side, and the diode 2
5 are connected with their anodes on the capacitor 23 side, and diodes 24 and 25 are connected.
The other ends are commonly connected and connected via an analog switch 26 to a resistor 20 at the output end of the operational amplifier 14. In addition, the capacitors 22 and 23 are connected to resistors 27 and 28 and analog switches 29 and 3.
0 series circuits are connected in parallel.
That is, analog switch 26 controls charging of capacitors 22 and 23, and analog switches 29 and 30 control discharging of capacitors 22 and 23.

31 and 32 are voltage follower operational amplifiers, and the terminal voltages of the capacitors 22 and 23 are input to non-inverting input terminals of the operational amplifiers 31 and 32, respectively. Reference numeral 33 denotes an operational amplifier to which the outputs of the operational amplifiers 31 and 32 are inputted to an inverting input terminal via resistors 34 and 35, and an amplifier circuit is constituted by this operational amplifier 33 and the resistors 34 to 36.

30 and 38 are operational amplifiers in which the output of the operational amplifier 33 is inputted to the non-inverting input terminal and the inverting input terminal via the analog switch 39 and the resistor 40;
5, variable resistors 46 to 47 and diode 48,
Together with 49, it constitutes a window comparator circuit that detects the upper and lower limits. The output of this window comparator circuit is inverted only when the input voltage is in the middle range between the two reference voltages obtained from variable resistors 46 and 47, and the input voltage is set by V _IN and variable resistor 46. .
Assuming that the reference voltage is V _S1 and the reference voltage set by the variable resistor 47 is V _S2 , the output of the AND gate 50 becomes high level only when V _S1 <V _IN <V _S2 . On the other hand, when V _IN <V _S1 , the output of the operational amplifier 37 becomes a low level, and when V _S2 <V _IN , the output of the operational amplifier 38 becomes a low level. Further, the variable resistors 46 and 47 can be changed in conjunction with each other, and are, for example, two variable resistors. The analog switch 39 is used to control the input to the window comparator circuit which determines whether the balance between the positive magnitude and the negative magnitude of the current is normal. Reference numeral 51 denotes an operational amplifier, and since the operational amplifier 51 is supplied with V _DD and V _SS as power supplies for the analog switch 39, it is used for signal level shifting.

52 and 53 are input resistors of the operational amplifier 51. 54, 55, the outputs of the operational amplifiers 37, 38 are connected to inverters 56, 57 and resistors 58, 59.
The voltage of V _DD is input to the non-inverting input terminals of the operational amplifiers 54 and 55 via resistors 60 and 61.

62 is an AND gate to which the output of the AND gate 50 is input to one input terminal; 63 is the above-mentioned AND gate;
AND gate 6 in which the output of AND gate 50 is input to one input terminal via inverter 64;
Reference numeral 5 designates an operational amplifier in which the output of the AND gate 62 is inputted to an inverting input terminal via a resistor 66, and a voltage of V _DD is inputted to a non-inverting input terminal of this operational amplifier 65 via a resistor 67. 6
8 to 70 are light emitting diodes connected to the output terminals of the operational amplifiers 54, 55, and 56 via resistors 71 to 73, and these light emitting diodes 68 to 70
A voltage of V _DD is inputted to the anode of the circuit via a diode 74 . That is, when the output of the AND gate 50 becomes high level, the output of the operational amplifier 65 becomes low level, the light emitting diode 68 lights up, and when the output of the operational amplifier 37 becomes low level, the output of the operational amplifier 54 becomes low level, The light emitting diode 69 lights up,
Further, when the output of the operational amplifier 38 becomes low level, the output of the operational amplifier 55 becomes low level, and the light emitting diode 70 lights up.

75-77 are capacitors connected between the cathode of the diode 74 and the outputs of the operational amplifiers 54, 55, and 56 via resistors 78-80, respectively.
The light emitting diodes 68 to 7 are connected in series with 80.
0 is lit for a long time. In other words, since the outputs of the operational amplifiers 54, 55, and 65 are at low level for only a few milliseconds during one cycle,
After reaching the high level, the charges in the capacitors 75 to 77 flow to the light emitting diodes 68 to 70, so that they can be visually confirmed and discriminated.
Further, the diode 74 is connected to the operational amplifier 54,
This is to prevent the discharge through the power supply line when the outputs of the capacitors 55 and 65 become low level and the charges in the capacitors 75 to 77 are discharged.

In addition, in Fig. 3, A to E are A to E in Fig. 2.
It corresponds to E.

In FIG. 3, reference numerals 81 and 82 refer to operational amplifiers to which the output of the operational amplifier 14 is input to the non-inverting input terminal and the inverting input terminal, 83 to 89 refer to resistors for input and bias of the operational amplifiers 81 and 82, and 90
is an AND gate, and this AND gate 90 is
Connect one terminal to buffer 91 and diode 92
The other terminal is connected to the output of the buffer 91 via an inverter 95 and an integrating circuit consisting of a resistor 93 and a capacitor 94 . A narrow pulse is obtained from the output terminal of this AND gate 90,
The level of the signal is converted by the operational amplifier 96, and the output of the operational amplifier 96 is taken out as the control input of the analog switches 29 and 30 in FIG.
Further, the output of the operational amplifier 97, to which the output of the operational amplifier 96 is input to the inverting input terminal, is taken out as a control input of the analog switch 26. 98~
101 is a resistance.

102 is a light emitting diode for checking circuit operation that lights up when a positive or negative current flows; the anode of this light emitting diode 102 is connected to the buffer 10;
3 and diodes 104, 105 to the output terminals of the operational amplifiers 81, 82, and its cathode is grounded via a resistor 106.

107 has one terminal connected to the output terminal of the operational amplifier 82 via a diode 108.
NAND gate, 109 is diode 104, 10
A resistor 110 is connected between the diode 108 and the ground.

111 is a timer IC, and this timer IC
The trigger terminal Tr of 111 is connected to the output terminal of the buffer 91 via a buffer 112, a resistor 113, and a capacitor 114, and the output terminal O is connected to a capacitor 115, a resistor 116, and an inverter 11.
The reset terminal R is connected to the set terminal S of the flip-flop 118 via a _resistor 119, a capacitor 120, and an analog switch 121. The analog switch 121 also includes an inverter 122, a diode 123, and a resistor 12.
4. Timer input via buffer 125
The timer IC 126 is triggered by the output of an operational amplifier 127 to which a full-wave rectified output synchronized with the welding power source is input. That is, in the case of 50Hz, the analog switch 121 is closed and the capacitor 120 is connected in parallel to the capacitor 128, so that it can be used even in the 50Hz area.

129 is an AND gate, and one terminal of this AND gate 129 is connected to the flip-flop 11.
The other terminal is connected to the cathode of a diode 105 which is connected to the output terminal of the operational amplifier 82. Also, this
The output of the AND gate 129 is input to the non-inverting input terminal of the operational amplifier 51 in FIG.
It is input to the input terminals of AND gates 62 and 63, and the period during which the output of this AND gate 129 is at a high level is the period when the light emitting diodes 68 and 6 in FIG.
The lighting time will be 9.70.

In FIG. 4, F corresponds to F in FIG. 130 connects the set terminal S to the output terminal of the AND gate 63 in FIG.
This flip-flop is connected to the output terminal of the NAND gate 131.
The output terminal Q of is connected to bias resistors 132 and 133.
When a set signal is input to this flip-flop 130, the transistor 134 is turned on, the relay 135 is operated, the contact 135a is opened, and the current flow is stopped. . 136 is a push button switch for reset, and this push button switch 1
36 is a capacitor 13 charged with the voltage of V _DD
7 in parallel via a resistor 138, and the connection point between the capacitor 137 and the resistor 138 is a NAND
It is connected to one terminal of the gate 131. 1
39 is a diode connected in parallel to the relay 135.

FIGS. 5 a to d show voltage waveforms at parts a to d in FIG. 2, and as is clear from FIGS. When the welding voltage is taken out, the capacitor 22 receives a wave-like voltage as shown in FIG.
The capacitors 23 are each charged with a voltage having a waveform as shown in FIG. 5c, and the operational amplifier 33
A voltage having a waveform as shown in FIG. 5d is taken out from the output terminal of the . In addition, in FIGS. 5a to 5d,
T ₁ is 16.7msec for 60Hz and 16.7msec for 50Hz.
It is 20msec.

6a to 6n show the voltage waveforms of parts a to n of FIG. 3. In other words, in the circuit of FIG. When the welding voltage is applied, the operational amplifier 8
At the output terminals 1 and 82, voltages as shown in FIG. 6b and c are obtained. A voltage as shown in FIG. 6d is applied to the output side of the diode 92, a voltage as shown in FIG. 6e is applied to the output side of the diode 108, and a voltage as shown in FIG.
The respective voltages shown in Figure f are obtained. Further, due to the voltage obtained at the output side of the diode 92, voltages as shown in FIG. 6g and h are obtained at the output terminals of the operational amplifiers 96 and 97.

On the other hand, the trigger terminal Tr of the timer IC 111 receives the signal shown in Fig. 6i, and the output terminal O receives the signal shown in Fig. 6j.
The signals shown in FIG. 6 are obtained at the set terminal S of the flip-flop 118, the signal shown in FIG. The signals shown in are obtained respectively. Then, the signal shown in FIG. 6n is obtained at the output terminal of the AND gate 129.

Here, in the signal obtained at the output terminal O of the timer IC 111 shown in FIG. 6j, T ₂ is determined by the time constant of the resistor 119 and the capacitor 128, and the output terminal of the AND gate 129 shown in FIG. In the signal obtained in , the period T ₃ is the lighting time of the light emitting diodes 68 to 70 in FIG.

As is clear from the above description, in the welding current balance monitoring device of the present invention, the positive peak value and negative peak value of the welding current are held by a sample hold circuit using capacitors 22 and 23. The output level of the positive and negative balanced state of the welding current is input to the window comparator circuit that detects the upper and lower limits using operational amplifiers 37 and 38 only during an extremely short period of time just before the end of one cycle of the welding current. However, the upper and lower reference values of the window comparator circuit are set by mutually interlocking variable resistors 46 and 47 for comparison with a reference value, and the following advantages can be obtained.

(1) Since the balance state is monitored every positive and negative cycle of the welding current, accurate monitoring can be performed even when the welding current is used in a short cycle of only one cycle.

(2) Even if the energization time is several tens of cycles,
It is accurate because it monitors each cycle, rather than monitoring the average current balance over several dozen cycles.

(3) Variable resistors 46 and 4 that interlock the upper and lower reference value settings of the window comparator circuit.
7, it can be easily carried out without using a measuring instrument such as an oscilloscope and without causing variations in detection accuracy. That is, in order to change the detection level of an unbalanced state, the upper and lower limit reference values are set using the variable resistors 46 and 47, but if the variable resistors 46 and 47 are independent from each other, the positive current and In order to make the detection level of negative current the same, it must be adjusted each time using a measuring device such as an oscilloscope.Also, if you set it only with the scale of the variable resistor without using a measuring device such as an oscilloscope, the positive However, according to the present invention, such inconvenience can be solved.

As described above, according to the present invention, it is possible not only to eliminate the conventional drawbacks, but also to easily set the detection level of the positive and negative unbalance of the welding current. By removing the resistor from the printed circuit board and making it adjustable from the outside, it is possible to monitor the balance between positive and negative welding current depending on the welding state.
In other words, depending on the energization method, main thyristor rating, etc., if the current is to be energized for a short time, for example, 1 to 2 cycles, or if there is not enough margin in the main thyristor rating, the unbalance detection level should be lowered and monitoring should be stricter. Can be set.

Furthermore, in the above embodiment, if the outputs of the variable resistors 46 and 47 for setting the upper and lower reference values of the window comparator circuit are displayed by a level meter formed by arranging a plurality of light emitting diodes, The degree of monitoring can be visually confirmed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional welding current balance monitoring device, FIGS. 2 to 4 are circuit diagrams showing a welding current balance monitoring device according to an embodiment of the present invention, and FIGS. Signal waveform diagrams at sections a to d in FIG. 2, and a to n in FIG. 6 are signal waveform diagrams at sections a to n in FIG. 3. 10... Welding transformer, 11, 12... Main thyristor, 13... Shunt, 22, 23... Capacitor, 24, 25, 48, 49... Diode, 27, 28, 40, 41, 42, 43, 4
4, 45... Resistor, 29, 30... Analog switch, 37, 38... Operational amplifier, 46, 47...
...variable resistance.

Claims (1)

[Claims] 1 Detect the magnitude of welding current using shunt etc.
A welding current balance monitoring device that monitors the balance state of the positive magnitude and negative magnitude of the welding current includes an amplifier circuit that amplifies a voltage obtained from a shunt or the like that detects the welding current, and an output of the amplifier circuit. A sample and hold circuit that performs sample and hold, a window comparator circuit that detects the upper and lower limits of the sample and hold circuit, a display circuit that displays the output state of the window comparator circuit, and the sample and hold circuit, the window comparator circuit, and the display circuit. The window comparator circuit is equipped with a sampling circuit that generates an opening/closing operation control signal for the window comparator circuit, a synchronization circuit synchronized with the welding current to obtain the operation timing of the sampling circuit, and a set/reset circuit in case of imbalance. In order to determine the upper limit and lower limit reference values, variable resistors are used that are interlocked with each other, and when the output of the sample hold circuit becomes other than the reference value of the window comparator circuit, the welding current is controlled by the window comparator circuit. A welding current balance monitoring device characterized in that it outputs an unbalance signal indicating that the balance between the positive magnitude and the negative magnitude of the welding current has been disrupted.