JPS6149704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation device for a virtual storage type information processing device.

In a virtual memory type information processing device, the logical address space is set larger than the real address space of the main memory unit (hereinafter referred to as MMU), and only the logical addresses that are currently actually needed are expanded into the real address space in the MMU. The other logical addresses are stored in desk memory, etc., which has a large capacity and requires a relatively long access time. When an access request occurs to a logical address that does not exist as a real address in the MMU, a series of addresses including that logical address is read out from the disk device as one page or one segment, and it is stored in the current address in the MMU. A real address space that is not in use or has a low usage priority is selected and expanded there for use. In this case, if the original contents of the real address space have been written to and have changed since the last time they were read from the disk, the contents of the disk must be updated and then the MMU can be used for the actual contents. After saving a portion of the address space to the corresponding disk address, the logical address is expanded to the real address space of the MMU.

In a device with such a configuration, when a certain logical address is given, that logical address and MMU
The correspondence between the logical address and the real address and the current existence of the logical address in the real address space change as the program to be processed progresses and are not univocally determined. Generally, processing programs are written using logical addresses, and therefore, when executing the program, the logical addresses designated by the program must be converted into real addresses at the current time. To accomplish this, conventional processing devices use an address translation device and an address management program to perform the translation.

In such conventional processing devices, when the central processing unit (hereinafter referred to as CPU) instructs a channel device to execute a certain process, the CPU creates a channel program to be executed by the channel device in the MMU and starts it. Directs the address to the channel device to begin its execution. The channel device sequentially reads the instructed channel program from the MMU, decodes it, converts it into individual commands to be specifically executed by the channel device, and executes the commands. At this stage of execution, some of the commands in the channel program include, for example:
When a logical address of a data buffer to be used by this channel device appears, the channel device converts this data buffer into a real address using the address conversion device and secures its use as a buffer with a real address in the MMU. do. However, when a channel device performs real addressing, if we allow the correspondence between real addresses and logical addresses to be freely changed for each logical address used by a large number of channel devices, as in the case of a CPU. The control becomes extremely complicated. For this reason, conventionally, a logical address once converted into a real address by a channel device in a certain channel program is fixed as a real address under the management of the address management program mentioned above. A method is used in which the address management program fixes the address only when the end signal of the channel program is issued. However, this fixation of real addresses has the following problems. In other words, since the operation of the channel device is generally slower than that of the CPU,
The real address of the data buffer fixed for a certain channel device occupies the allocated memory area in the MMU for a much longer period than the CPU uses, and it is not until after the above real address conversion that the address is actually used. It has the disadvantage that even if there is a long waiting time before it is used, the memory area cannot be used effectively by the CPU or other channel devices. SUMMARY OF THE INVENTION An object of the present invention is to provide an address translation device for a virtual storage type information processing device that eliminates the above-mentioned drawbacks.

The device of the present invention includes a register file including registers corresponding to each real page in an address conversion device for a virtual storage type information processing device, and usage conditions of this converted page in converting a logical page to the real page address. means for writing information including information and information identifying a device that has requested conversion into a real address into the register corresponding to the real page;
means for specifying the real page and reading the written information; and, in response to the ejection of the logical page converted into a real address, requesting the conversion into a real address corresponding to the evicted logical page. and means for modifying information for identifying a device so that when the modification information is read, it can be identified that the page has been evicted.

Next, the present invention will be explained in detail using the drawings. FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 1 indicates an address translation device. This address translation device 1 includes a page management register file (hereinafter referred to as file) 11 and a control section 12. The logical addresses are divided into blocks of the same size and these are called pages. If the entire real address space to be used includes n+1 pages from "0" to "n", the file 11 should also have one unit register corresponding to each real page, and n+1 registers. will be included. 1st
In the figure, the address of main memory unit (MMU) 3 is
The total capacity of the MMU 3 is divided into page sizes, real page numbers are assigned in order, and each real page is shown in correspondence with a register indicating the same real page of the file 11. Each horizontal row in the figure corresponds to a real address for one page. The file 11
As shown in FIG. 2, each register consists of a device bit field S that specifies the device that has requested real address translation, and a control field F that contains data for controlling the real address translation. For the field S, a 1-bit field is allocated for each device issuing a request for address translation.
For example, when a logical page of the fifth channel device 6 is converted into an R page of real addresses, the fifth bit of the field S of the register corresponding to the real R page is set to "1". The field F is further divided into a change display field C and another field K. Said field C
Displays whether or not the contents of the logical page currently written to this real page have been changed after being read from the disk device 7 and expanded to this real address of the MMU 3.
That is, when a change is made to the contents of a certain real page, the change display field C of the corresponding page is set to "1". Therefore, if this field is "1", it means that a change has been made to that page, and when expanding a new logical page to this real page, the contents of the original page will be copied to the disk. 7 to the corresponding logical page, update the disk contents of that logical page, and then develop a new logical page. The process of invalidating the original page content and developing a new logical page therein in accordance with the content of field C is called expelling the original page. In other words, change display bit C
If you want to eject this page and deploy a new logical page to its real address, you need to write the contents of the original page to disk before doing so, but even if you do not do this and deploy the new logical page immediately. There is a bit that indicates whether it is good or not. Next, if the logical page for which the access request occurred does not exist among the real addresses and all the real addresses are occupied by already read logical pages, one of those existing pages is evicted, A newly requested logical page must be developed there, and in this case, the other field K stores information regarding the priority with which this selection should be made.

Using the address translation device 1 described above, for example, when the fifth channel device 6 converts a logical page L into a real address for use as a data buffer, the process is performed as follows.

(P-1) The control unit 12 examines the K field of each register in the file 11 and selects the page with the lowest priority (this is referred to as page M).

(P-2) If the C field of the real page M is “1”, the contents of one page of the real page M of the MMU 3 are transferred to the logical page written in the current real page M of the disk device 7. Save to the location containing the .

(P-3) The field S of the register corresponding to the real page M of the file 11 corresponds to the channel device 5 (assuming this is the second channel device) that has been using this real page until now. Reset the second bit.

(P-4) Read the logical page L from the disk 7 and expand and store it in the real page M of the MMU 3.

(P-5) Set the fifth bit in the field S of the register corresponding to the real page M of the file 11 (the bit corresponding to the fifth channel device that is the request source of this page) to "1". ”.

The above is the real addressing process. Next, using this process, the operation when the CPU 2 instructs the fifth channel device 6 to execute a certain process will be explained. As mentioned above, CPU2 is first
A program to be executed by the channel device 6 is created in the MMU 3, and its start address is instructed to the channel device 6 to start its execution. The channel device 6 sequentially reads out the channel program instructed in this way from the MMU 3, decodes it, converts it into individual instructions that the channel device 6 should specifically execute, and executes it. When a logical address (page) of the data buffer used by the channel device 6 appears, the channel device 6 converts the page into a real address according to the process of P-1 to P-5 described above. In this case, the above P-1~
The P-5 process uses a device that performs real addressing.
The process is exactly the same whether it is the CPU 2 or other channel devices, and no distinction is made as mentioned in the description of the conventional device. In other words, even if the device that performs real addressing is a channel device, the real address is not fixed as in the past, but the CPU and other devices use the real address according to the priority rules determined. be free to do so. In this state, when the channel device 6 executes an instruction (this is a fragmented instruction that appears as a result of decoding the command of the channel program) that actually uses the page that has been converted into a real address, , the field S of the real page of the file 11 is read by giving a real address via the control unit 12. If the bit corresponding to that device is set, this indicates that the page that has been converted into a real address by that channel device 6 remains without being evicted, so the above instruction is executed and the channel program continues as is. do. If the bit corresponding to that device 6 in the corresponding field S has been reset, at that point either the page is real addressed again or the channel program terminates abnormally at that point.
It is possible to take a method such as reporting this to the CPU 2 and requesting the CPU 2 to recreate the channel program thereafter.

In the above embodiment, when a certain channel device actually uses a page converted into a real address of that channel device, information is obtained as to whether the page has already been evicted or remains without being evicted. However, the device bit field of that page of the file 11 is read out via the control section 12, and the bits corresponding to the device are set and reset.Another embodiment for this is shown in FIG. Shown below. In this embodiment, the allocation status storage unit (hereinafter referred to as storage unit) 13
is added to the file 11 and control section 12 to perform the following operations. The storage unit 13
As shown in FIG. 3, it consists of a gate circuit 131, an allocation status display register 132, an execution device number register 133, and a selector 134. and the aforementioned fifth channel device 6.
(FIG. 1) assumes that in the processes P-1 to P-5 for converting the L page into a real address, each of the constituent circuits of the storage section 13 performs the following operations.

(Q-1) In the process of P-3, when the second bit of the S field of the file 11 corresponding to the second channel device 5 (FIG. 1) is reset, the allocation status display register (hereinafter referred to as The corresponding second bit of display register 132 is reset.

(Q-2) In the process of P-5, when the fifth bit of the S field of the page management register file 11 corresponding to the fifth channel device 6 (FIG. 1) is set, the display register The corresponding fifth bit of 132 is set.

Under the control of Q-1 and Q-2 above, if all the pages converted into real addresses of a certain channel device exist without being evicted, they correspond to that channel device in the allocation status display register 132. bit is set. This is constantly updated according to changes in page allocation within the MMU3. By setting the number of an arbitrary channel device in the execution device number register (hereinafter referred to as number register) 133, the contents of the display register 132 can read out the bits corresponding to that channel device to the output of the selector 134. Therefore, before a channel device executes an instruction that uses said real addressed page, it reads that page of said file and checks whether the bit corresponding to said channel device in said field S is set. Instead of checking, by setting the channel number in the number register 133, it is possible to immediately obtain information from the output of the selector 134 as to whether or not all pages converted into real addresses by the channel device remain without being evicted. I can do it. Therefore, based on this output, the control section 12 controls subsequent processes in the same manner as described above.

As another example, some conventional methods do not perform real addressing at all on the channel device side. In this method, when the CPU instructs a channel device to perform a certain process, it first creates a channel program, and before instructing the channel device to execute it, the CPU converts the logical address of the channel program into a real address, and then , fixes the real address using an address management program, and then instructs the channel device to execute the channel program. Even in this case, the present invention can be applied as follows.

That is, when the CPU converts a logical address (page) in a channel program into a real address, it uses the address conversion device (hereinafter referred to as conversion device) of the present invention and converts it according to the processes P-1 to P-5 described above. Instead of fixing pages with real addresses as in the past. Further, as the conversion device, for example, the device shown in FIG. By setting this, it is read whether or not the page with the real address has been evicted at the present time, and accordingly it is determined whether to continue execution as described above or to report it to the CPU as abnormal termination.

As described above, in conventional virtual memory type information processing devices, the real address in the MMU used by a channel device must be fixed until the channel program for that channel device is completed. Therefore, even when the channel device is not actually using the real address, it monopolizes that memory part and cannot make it available to the CPU or other channel devices that could use it effectively. There are drawbacks. By using the present invention, the above-mentioned drawbacks are eliminated by allowing the real addresses assigned to channel devices to be freely removed, thereby making it possible to use the information processing device as a whole effectively. In addition, from a program perspective, processing for converting channel devices to real addresses and processing for converting CPU to real addresses can be handled in the same way, making it unnecessary to fix the real addresses used by channel devices. This can greatly reduce the load on the program.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing the format of fields of each register in a page management register file, and FIG. 3 is a diagram showing another embodiment. In the figure, 1... address translation device, 2... central processing unit (CPU), 3... main storage device, 4... first channel device, 5... second channel device, 6... 5th channel device, 7... Disk device, 11... Page management register file, 12... Control unit, 13... Allocation status storage unit, 131... Gate circuit, 132... Status display register, 133... ...Execution device number register, 134...Selector.

Claims (1)

[Claims] 1. In an address translation device for a virtual memory type information processing device, a register file containing registers corresponding to each real page, information including usage conditions of this converted page in the conversion of a logical page to the real page address, and its implementation. means for writing information identifying a device that has requested addressing into the register corresponding to the real page; means for specifying the real page and reading the written information; and means for reading out the written information by specifying the real page; When the page is evicted when, in response to the ejection of the logical page that has been evicted, the information identifying the device that requested the real addressing corresponding to the evicted logical page is modified and the qualified information is read. 1. An address translation device characterized by comprising: means for identifying that a person is present.