JPS6149756B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a magnetic bubble memory device, and in particular, a plurality of minor loops in which magnetic bubbles for a plurality of n bits exist are connected to a common major loop via transfer gates, and are connected to the minor loop and a CPU (computer main body) through the major loops. ) This magnetic bubble memory device has a medium/minal loop configuration for exchanging data with the device, and is suitable for use as a standard pattern memory for pattern recognition devices, for example, with the aim of speeding up access. It is related to. FIG. 1 shows the configuration of a magnetic bubble memory to which the present invention is applied. FIG. 1 shows a bubble memory chip with a major/minor loop configuration, where 101 is a minor loop, 102 is a major loop, 103 is a transfer gate, 104 is a replicator, 1
05 is a generator, and 106 is a detector.
In addition to the major/minor loop type magnetic bubble memory device shown in Figure 1, there are all-serial type magnetic bubble memory devices, but the latter type has a slow access speed, so it is not suitable for pattern recognition devices. It is unsuitable for memories that require high-speed access, such as The configuration and operation of the major/minor loop bubble memory will be described below with reference to FIG. In the initial state, the contents of the bubble memory are set to zero by a permanent magnet, that is, the bubbles are in an extinguished state. Data is written to the bubble by a control signal 201 sent from a control device (not shown) in the CPU to the generator 105 on the medial loop.
and generates bubbles in the medial loop 102 according to the contents of the data 200. That is, data 2
A bubble is generated only when 00 is "1" at the logic level. When a bubble corresponding to 129 bits of data is prepared in the major loop 102, the bubble in the major loop 102 becomes the minor loop 10.
1 via the transfer gate 103. In other words, in this bubble memory, 129 minor loops numbered 1 to 129 are divided from 1 word to 129.
It corresponds to a word, and when there are multiple chips, specifically 16 chips, as shown in FIG. 1, it becomes 129 words x 16 bits. In the minor loop, . This can be thought of as the concept of sector in magnetic disk memory being replaced by block. In other words, 1 sent from the CPU control device side.
129 words of data corresponding to a block are written in bit serial to the major loop, and then transferred to the minor loop. Also, when reading data, for example, by selecting a block address in the minor loop,
Bubbles for 129 words of the 0th block are transferred from the minor loop 101 to the major loop 102 via the transfer gate 103. There are 129 words worth of bubbles in the media loop 102, which are sequentially sent to the detector 106 for detection and sent back to the CPU control device as binary data. The replicator 104 reproduces the bubbles sent on the major loop 102 by dividing them into the detector side and the major loop side. The continuous block reading means of the present invention is described in Japanese Patent Laid-Open No. 53-69545. An object of the present invention is to speed up access to the magnetic bubble memory as described above, and the feature of the present invention is to employ the following configuration to achieve this object. That is, the addressing of the magnetic bubbles for a plurality of n bits in the minor loop is done in the order of block addresses, . At the same time, when accessing data stored in the minor loop, specify the first block address and read successive block addresses sequentially, for example →→... In a magnetic bubble memory device with a medium/minor loop configuration, which is equipped with a means for transmitting and receiving data between the minor loop and the control device via the medium loop, when data is transferred from the minor loop to the control device, the specified first block address is Accordingly, a structure is adopted in which blank reading means is provided for not transferring data at a designated block address of the data read by the continuous block reading means to the control device. First, referring to FIG. 2, addressing of the bubble memory by continuous block reading means will be explained, and referring to FIG. 3, addressing according to the conventional general system will be explained.
The addressing of the bubbles in the minor loop 101 according to FIG. 2 is as follows:
, ......〓〓, and the block address is from the block address, the block address is from the block address, ......, and the block address is at a position moved half a turn from the block address〓〓 on the minor loop. Configure it as follows. Also,
In FIG. 2, the minor loop 101 actually has 535 bits, of which 512 bits are necessary and the remaining 23 bits are redundant, which are divided into two and assigned to corners a and b. Therefore, the next address is 268 bits away. The reason why bubbles are not placed at the corners is to increase the operating margin, and this is a well-known technique. That is, when the power is turned off, it is necessary to stop the address on the transfer gate 103 side for the next time the power is turned on and accessed, and at this time, if a bubble comes to the corner, the margin decreases. The addressing according to the structure shown in FIG. 2 is effective during continuous block transfer. Hereinafter, taking reading as an example, continuous transfer of two blocks from address → will be explained. First, the 129 word bubble at the block address is the minor loop 1.
01 to the medium loop 102 via the transfer gate 103. Bubbles are sequentially sent on the medial loop and data is guided to the detector 106. When all 129 words of the block address are read out to the CPU side via the detector 106,
The address reproduced on the medium loop 102 by the replicator 104 for data rewriting.
Bubbles for 129 words are moved and lined up on the loop line on the opposite side of the transfer gate 103 on the major loop 102, and at this time, in the minor loop 101, the address is placed directly below the transfer gate 103 with the address at the top. ,
,,......, 〓〓 block bubble is coming. Therefore, immediately block address 129
Word bubbles can be transferred from the minor loop 101 to the memory on the CPU side via the transfer gate 103 and the major loop 102. When all 129 words of the block address are read out to the CPU side via the detector 106,
The bubble for 129 words of the address reproduced on the medium loop 102 by the replicator 104 is
Transfer gate 10 on medium loop 102
The bubble on the loop line opposite to 3 and the 129 words of the address is the major loop 102.
It has moved onto the loop line directly below (directly above in the illustration) the transfer gate 103 at the top. Moreover, at this time, in the minor loop 101, there are bubbles of blocks with addresses . Thereby, the data at the address on the major loop 102 can be rewritten immediately back to the minor loop 101 side via the transfer gate 103. That is, during continuous block transfer, two blocks of bubbles exist on the medium loop 102 at the same time. As described above, by configuring the block addressing of bubbles on the minor loop 101 as shown in FIG. 2, it is possible to shorten the time required for continuous access. On the other hand, according to the general block addressing method shown in FIG. 3 which is not equipped with a continuous block reading means, considering the case where two blocks from the address → are transferred consecutively in the same way as described above, the block address 129 is When all the words have been read out to the CPU side via the detector 106, the bubbles for 129 words at the address reproduced on the major loop 102 by the replicator 104 are transferred to the loop line on the opposite side from the transfer gate 103 on the major loop 102. The fact that they are moved upward and lined up is the same as in the case of FIG. 2, but at this time, in the minor loop 101, the transfer gate 10
Directly below 3, there are 256 bubbles with addresses 〓〓, 〓〓,……〓〓 with the bubble with address 〓〓 on top. Therefore, both the minor loop 101 and the major loop 102 are moved by another half turn, the data at the address on the major loop 102 is returned to the minor loop 101, and after this data rewriting is completed, the data at the address on the minor loop 101 is read out. have to move. As described above, when addressing is not based on the continuous block read method shown in Figure 3, the time required for continuous access is longer than when using address assignment based on the continuous block read method shown in Figure 2. . In the present invention, an apparatus equipped with a continuous block reading means is provided with an idle reading means as described below to achieve even faster access. The idle reading means means that when data is transferred from the minor loop to the control device, the data at the specified block address of the data read by the continuous block reading means according to the specified first block address is sent to the control device. Means a means of non-transfer. When accessing bubble memory, data stored in consecutive block addresses is not necessarily accessed, but blocks are often accessed intermittently. Such a situation often occurs particularly when a standard pattern group is read out in a pattern recognition device. Access examples are shown in Tables 1 and 2. Table 1
When accessing consecutive blocks as shown in (1), it is sufficient to simply read the consecutive blocks as shown in Table 2 (1). However, if there is a gap in the middle as shown in Tables 1 (2) to (4), if only the method of specifying and accessing the beginning of continuous block transfer each time is adopted, the time required for access will be longer.

【table】

[Table] In other words, once you specify the first block address,
When transferring continuously, it can be transferred in the required time of (1 block transfer time) x (number of blocks) + (block address access time), but when accessing intermittently, blocks are locally consecutive. The above relationship holds true in the area, but for example, in the first
When accessing as shown in table (2), −−,
-- When accessing as two groups, the required transfer time is 2.times.(1 block transfer time).times.(number of blocks)+(block access time)].
In this case, (number of blocks) is 3. On the other hand, as shown in Table 2 (2), if blocks are accessed continuously and blocks are read blankly, the required transfer time is (one block transfer time) x (number of blocks) + (block address access). time). In this case, (number of blocks) is 7. Therefore, in the latter method, data can be transferred faster than in the former method by the amount that one block transfer time is subtracted from the block address access time. In reality, the block access time is more than twice the one-block transfer time (compared at maximum values), so it is better to use a combination of continuous block reading and empty reading until the jump is up to two blocks. . FIG. 4 shows a flowchart of idle reading control employed in the present invention, and FIG. 5 shows its control circuit. Idle reading control is specifically based on a microprogram, and as shown in Figure 4, when the program is started, either read or write is executed.
It enters the search routine, and since it is a read in this case, it enters the read routine. In the read routine, a process 40 for determining “idle reading or not?”
, it is checked whether or not it is an empty read, and if it is not an empty read, the process proceeds to the "N" side, a process of reading data from the bubble is performed in a process 41, and a direct memory access process is performed in a DMA process 42. , data is sent to the CPU's memory one word at a time, and data continues to be transferred from the bubble to the memory until one block end is reached. When it is confirmed in process 45 that one block has reached the end, it is checked in process 50 whether or not all block transfers have been completed. If not, the process advances to the "N" side and returns to blank reading process 40 again. Move to next block transfer. At this point, a check is made as to whether or not it is an empty reading, and the process moves on to the next step. If the check result in the blank reading process 40 is blank reading, proceed to the "Y" side and proceed to the process 46.
In step 47, a process of reading data from the bubble is performed, but the read data is not sent to the memory of the CPU, but continues to be transferred until the check in process 47 reaches the end of one block. When it is confirmed in process 47 that one block has reached the end, it is checked in process 50 whether or not all block transfers have been completed. The same process is repeated thereafter. In FIG. 5, 300 is a ROM (read-on memory), 301 is an address register, 302 is an instruction register, 303 is a test condition register, 304 is a test multiplexer, 30
5 is bubble read, write control logic, 306 is
Interface with the CPU, 307 and 308 are registers for writing to the bubble, 310 and 309 are registers for reading from the bubble, and 311 is an empty reading register. The flow shown in FIG. 4 is achieved by the circuit shown in FIG. 5. The control circuit shown in FIG. 5 is activated by a device number 400, an order 401, a stroke 402, etc. sent from a CPU (not shown), and an interface 306 generates signals to control each section. For example, when reading from a bubble, a signal is output from output terminal a of the interface 306 and sent to the test multiplexer 304. The ROM 300 is sending a read or write test condition to the test condition register 303, and the signal a
The condition is met by the occurrence of , address branch output 410 is sent from the test multiplexer 304, and the process jumps to the read routine. When jumping to the read routine, ROM300 is the instruction register 3
02, drives the bubble read/write control logic 305, and sends a control signal 40 to the bubble.
6. Specifically, read-enable, write-enable, etc. are sent. Also, prior to that, the empty read register 311
Set the data from the CPU and specify the block to be read blankly. For example, to idle read the third and fourth blocks, the idle read register 311
It is sufficient to set the logic level "1" to the third and fourth bits of the block, and by checking the output Z of the blank reading register 311 using the blank reading determination instruction, the third and fourth blocks are "1". So I read it blankly,
Since the other blocks are "0", DMA processing is performed. The write register 307 is written by the CPU when writing.
The data 404 is set by
In a DMA process under the control of the controller, command signals 408 from the command register 302 sequentially move data to the write register 308 in order to write the data into the bubble. Read register 309, 31
0 works in the same way as write registers 307 and 308 above when reading. As described above, according to the present invention, it is possible to control idle reading using simple hardware and speed up data transfer from bubbles when performing continuous block transfer intermittently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a magnetic bubble memory to which the present invention is applied, FIG. 2 is an explanatory diagram of address assignment of a bubble memory using a continuous block read method, and FIG. 3 is a conventional general address diagram that does not use a continuous block read method. The attached explanatory diagram, FIG. 4 is a flowchart of idle reading control in the present invention, and FIG. 5 is a control circuit diagram thereof. Explanation of symbols, 101...Minor loop, 102
... Mediya loop, 103 ... Transfer gate, 104 ... Replicator, 105 ... Generator, 106 ... Detector, 300 ...
ROM, 302...Instruction register, 306...Interface, 307, 308...Write register, 309, 310...Read register.

Claims (1)

[Claims] 1. A plurality of minor loops in which magnetic bubbles for a plurality of n bits exist are each connected to a common major loop via a transfer gate, and the addressing of the magnetic bubbles for the n bits in the minor loop is assigned to an arbitrary block address and the following block address. Continuous block reading means for reading the block address so that the block address is at a position shifted by half a turn on the minor loop, and specifying the first block address when accessing the data stored in the minor loop and sequentially reading out the block addresses following it. In a magnetic bubble memory device with a medium/minor loop configuration, which is equipped with the above-mentioned medium loop and sends and receives data between the minor loop and the control device, when data is transferred from the minor loop to the control device, the data is transferred according to the specified first block address. 2. A magnetic bubble memory device characterized in that a blank reading means is provided for not transferring data at a designated block address among the data read by the continuous block reading means to a control device.