JPS6149822B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an imaging device, and particularly to a semiconductor imaging device.

Although there are various types of imaging devices, an all-solid-state imaging device that does not require high voltage, vacuum, etc. has been proposed using a charge transfer element. Charge transfer devices have the advantage of having a simple structure and high integration density, but the charges that form the output signal are carriers that are ionized by light and accumulated in MOS capacitors, etc., and there is no charge leakage during transfer. becomes a problem.

An imaging device using a MOS transistor as a photodetector has also been proposed, but the photodetection uses a pn junction in the source region as a photodiode, which poses problems in terms of sensitivity and the like.

An object of the present invention is to provide a semiconductor imaging device using a novel static induction transistor structure.

A junction type static induction transistor has a pn junction between a gate region and a channel region, and can be used as a photodetector with an amplification effect when operated as a photocell and the gate region is used as an accumulation region. An insulated gate static induction transistor in which a depletion layer is formed under the gate electrode also has a similar function.

The present invention will be explained below with reference to the drawings.

FIG. 1a is a partial cross-sectional view of a semiconductor imaging device using a static induction transistor, showing one imaging element forming a transistor structure. p-type substrate 1
An n ⁺ -type drain region 3 surrounded by an n ^- -type region 2 is formed thereon, and an n ^- -type epitaxial layer 4 is formed thereon. A P ⁺ type gate region 5 and an N ⁺ type source region 6 are formed in the epitaxial layer 4,
A source electrode 7 is formed on the source region 6 . The surface of the epitaxial layer 4 is covered with a transparent insulating film 8, and a gate electrode 9 is formed on a portion of the gate region 5 via the insulating film 8, as shown in FIG. 1B. That is, the gate structure is formed from the electrode 9, the insulating film 8, and the gate region 5.
In the present invention, this structure is referred to as an insulated junction gate.
The impurity density of the n ^- type region 4 is selected to be sufficiently low, so that when a predetermined reverse bias (including zero bias) is applied between the source electrode 7 and the gate electrode 8, the channel is pinched off, creating a potential barrier, and the drain This potential barrier is also controlled by voltage. That is, a static induction transistor is formed. The thickness of the insulating film 8 between the gate electrode 9 and the gate region 5 is set so that the capacitance C ₁ formed in this MIS structure is not too small compared to the capacitance C ₂ between the gate region 5 and the source region 6. choose. If the formed capacitor C ₁ is too small, most of the voltage applied to the gate electrode will be applied to both ends of this capacitor C ₁ , and the component effectively applied between the gate and the channel will become small.

On the other hand, the potential fluctuation ΔV in the gate region 5 due to the charge ΔQ accumulated in the gate region due to photoionization depends on the total capacitance C=C ₁ +C ₂ of the gate region, so the total capacitance C should not become too large. Make it.

Briefly explain the operation. A predetermined positive voltage is applied to the gate electrode while keeping the drain and source at the same potential. The p ⁺ type gate region 5 is biased in the forward direction, and if excess electrons are accumulated, they are ejected outside the gate region and the gate region becomes a predetermined state (clear state). Next, a predetermined negative voltage (or a predetermined positive voltage of the source electrode 7) is applied to the gate electrode 9 to bias the gate region 5 in the reverse direction. At this time, gate region 5 and n ^- region 4 form a diode biased in opposite directions. The light incident on this diode through the transparent insulating film 8 generates electrons and
When hole pairs are generated, the holes flow into the gate region 5 and are accumulated. The potential V of the gate region changes by ΔV=ΔQ/C due to the accumulated charge ΔQ. Next, when a predetermined positive voltage is applied to the drain electrode 7, a drain current flows due to the gate potential.

The current-voltage characteristics of the static induction transistor when the channel is in a pinched-off state due to the gate voltage basically follow an exponential law.
Therefore, the change in gate voltage due to the amount of light irradiation △
The change in drain current with respect to Q/C is very large, allowing for highly sensitive detection. Of course, in the final step, if it is desired to extract the signal as a signal intensity proportional to the amount of incident light again, the signal can be passed through an amplifier having current-voltage characteristics that are exactly opposite to those of the electrostatic induction transistor. Since the static induction transistor can have a small gate capacitance C and a large conversion conductance, a large output signal can be obtained. When the drain voltage is returned to the source voltage and a predetermined positive voltage is applied to the gate electrode 9, the gate region 5 returns to the clear state. By repeating this cycle, the amount of incident light can be continuously detected.

The potential of the gate region 5 is a voltage △ due to a component due to an external reverse bias voltage and a component due to accumulated charges.
Q/C, and the sum of both cannot exceed the diffusion potential. Therefore, in order to widen the dynamic range, it is better to increase the reverse bias. If the design is designed to increase the voltage amplification factor, applying a reverse voltage (positive potential for n-type) to the source will have the same effect as applying a reverse voltage (negative voltage for p-type) to the gate. have

The clear state can be a neutral state, a positively charged state, or a negatively charged state as long as it is a constant state, but if it is in a carrier-deficient state, it has the same effect as a reverse bias, so it is not a dynamic state. To widen the range, if the gate region is p(n) type,
It is preferable to bring it into a negatively (positively) charged state or a neutral state. It is preferable that the spacing between the gate regions (width of the channel) is selected so that the channel is sufficiently pinched off in the clear state.

FIG. 2 shows a schematic diagram of an example of a two-dimensional imaging device in which the elements shown in FIG. 1 are arranged in a matrix in a plane. A plurality of row lines a1, a2, a3, . . . and a plurality of column lines b1, b2, b3, . The sources of the elements are connected to the corresponding row lines, and the drains of the elements are connected to the corresponding column lines. Furthermore, the clear lines c1, c2, c3...... are the column lines b1, b2, b
3... are arranged in parallel and connected to the gate electrode.

To read image information, for example, while keeping the row line a1 at zero potential, apply a positive voltage to prevent reading to the other row lines a2, a3, and then apply a positive voltage to the column lines b1,
A read positive voltage pulse is sequentially applied to b2, b3, . . ., and the current flowing to the row line a1 is detected. Following the read pulse, an erase positive voltage pulse is applied to the clear lines c1, c2, c3, . . . to sequentially clear the elements that have been read. Since positive voltage is applied to the sources of the elements in the other rows, they are neither read nor cleared. After reading and clearing the first line, perform the same operation on the second line. After sequential reading and reading up to the last row, the first row is read again. It may also be read out in interlace. In order to detect low-illuminance areas with good sensitivity, the voltage of the read pulse may be increased. The reverse bias can also be strengthened by increasing the voltage of the clear pulse and the voltage for preventing reading. The voltage of the read pulse is selected to provide sufficient accuracy in the operating region of use. When reading at a high speed, the pulse width of the read pulse may be shortened to speed up scanning, and the clear pulse having a relatively wide pulse width may follow the read pulse. In this case, before the clear pulse applied to one element ends, the clear pulse is applied to the next element.

FIG. 3 shows an insulated gate type image sensor. An n ⁺ type drain region 3 surrounded by an n ^- type region 2 is formed on a p-type substrate 1, and a channel is formed thereon.
An n ^- type region 4 is formed. The area around the channel is cut out and the channel part protrudes. An n ⁺ type source region 6 is provided at the top portion, and a source electrode 7 is formed thereon. A gate electrode 9 is formed with an insulating layer 8 interposed therebetween. If the insulating layer under the gate electrode 9 is given a negative charge and an inversion layer is formed on the surface, the transistor operates in the same way as the insulated junction type static induction transistor shown in FIGS. 1a and 1b. A bias voltage may be always applied to the gate electrode 9. In the configuration shown in FIG. 3, the light-receiving surface is provided on the lower surface, making it a back-illuminated type.

FIG. 4 is a modification of the embodiment shown in FIGS. 1a and 1b, in which the gate electrode is omitted and a switching bipolar transistor is provided. The gate region 5 is used as an emitter, the base region 11 and the collector region 12
A base electrode 13 is provided on the base region 11, and a collector electrode 14 is provided on the collector region 12. Although the base region 11 is shown as a separate region from the channel region 4, they may be the same region. Since clearing is performed through a bipolar transistor, it has the advantage of high-speed operation.

Although the embodiments have been described above, the present invention is not limited thereto. All conductivity types can be reversed, semiconductor materials can be selected, the configurations of each embodiment can be combined, and various structures known in the semiconductor device art can be incorporated.

[Brief explanation of the drawing]

1A and 1B are partial sectional views of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the solid-state imaging device of FIGS. 1A and 1B, and FIGS. FIG. 3 is a partial cross-sectional view of the embodiment.

Claims (1)

[Claims] 1 Consisting of one main electrode, the other main electrode, a channel disposed between both electrodes, and a control electrode structure forming a pn junction between the channels and functioning as a photocell, The channel creates a potential barrier by applying a predetermined reverse bias, including zero, between the one main electrode and the control electrode structure, and the potential barrier is created by the voltage of the other main electrode. A semiconductor imaging device is used in which a plurality of controlled electrostatic induction transistors are arranged in a matrix, optical carriers are accumulated by light irradiation on the pn junction, and a voltage is applied between one main electrode and the other main electrode. A semiconductor imaging device characterized in that the magnitude of the signal between one main electrode and the other main electrode changes according to the optical carrier charge accumulated in the pn junction, thereby obtaining a signal corresponding to the irradiated light. . 2. The semiconductor imaging device according to claim 1, comprising one main electrode connected to a row line at an intersection of the matrix and the other main electrode connected to a column line. . 3. The semiconductor imaging device according to claim 2, wherein the control electrode structure includes a clear line connected thereto. 4. The control electrode structure includes a gate region of a conductivity type opposite to that of the channel region, an insulator layer disposed on the gate region, and a gate region disposed on the insulator layer and connected to a clear line. 3. The semiconductor imaging device according to claim 2, further comprising a gate electrode having a gate electrode. 5. The control electrode structure includes the channel region, an insulating layer disposed on the channel region, and a gate electrode disposed on the insulating layer and connected to a clear line. A semiconductor imaging device according to claim 2.