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JPS6149859B2 - - Google Patents
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JPS6149859B2 - - Google Patents

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Publication number
JPS6149859B2
JPS6149859B2 JP4217777A JP4217777A JPS6149859B2 JP S6149859 B2 JPS6149859 B2 JP S6149859B2 JP 4217777 A JP4217777 A JP 4217777A JP 4217777 A JP4217777 A JP 4217777A JP S6149859 B2 JPS6149859 B2 JP S6149859B2
Authority
JP
Japan
Prior art keywords
signal
circuit
latch
received signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4217777A
Other languages
Japanese (ja)
Other versions
JPS53127221A (en
Inventor
Takeo Fukuda
Kazuaki Kawabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP4217777A priority Critical patent/JPS53127221A/en
Publication of JPS53127221A publication Critical patent/JPS53127221A/en
Publication of JPS6149859B2 publication Critical patent/JPS6149859B2/ja
Granted legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 この発明は、信号の漏洩による悪影響を除去し
た二線式全二重データ伝送装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-wire full-duplex data transmission device that eliminates the adverse effects of signal leakage.

二線式全二重データ伝送方式は、従来の四線式
データ伝送方式に比較して、その伝送線路数が半
減し、経済的であるという利点がある。この二線
式全二重データ伝送方式は第1図に示すように構
成されている。即ち、データ送信部1から出力さ
れるデータはハイブリツド回路2を介して伝送線
路3へ送出される。またこの伝送線路3を介して
伝送されたデータは前記ハイブリツド回路2を介
して抽出されデータ受信部4に供給され、受信さ
れる。しかして、二線式全二重データ伝送装置で
は主局から伝送され、受信された信号に含まれる
クロツク成分を検出してクロツク信号を抽出再生
し、このクロツク信号に従つて受信信号中からデ
ータを受信再生すると共に、上記クロツク信号に
従つて送信データを符号化して送信している。と
ころが、ハイブリツド回路2から見た伝送線路3
の回路インピーダンスは純抵抗ではない。この為
に、前記送信部1から出力されたデータがハイブ
リツド回路2を介して前記受信部4へ漏洩する場
合がある。この信号漏洩は、上記装置におけるク
ロツク信号の抽出再生に著しい悪影響を与え、誤
つたクロツク信号によるデータの受信再生の誤り
や、送信データの誤つた符号化を招来する。これ
を防止する為に図中5に示す整合器をハイブリツ
ド回路2を介して伝送線路3に接続し、回路イン
ピーダンスの平衡をとるようにしている。しか
し、上記伝送線路3の回路インピーダンスは、そ
の線路長によつて大きく変化するものである。こ
の為、前記整合器5の平衡調整が難しく、また整
合器5自体の設計も非常に困難であつた。
The two-wire full-duplex data transmission system has the advantage that the number of transmission lines is halved and is economical compared to the conventional four-wire data transmission system. This two-wire full-duplex data transmission system is constructed as shown in FIG. That is, data output from the data transmitter 1 is sent to the transmission line 3 via the hybrid circuit 2. Further, the data transmitted via the transmission line 3 is extracted via the hybrid circuit 2 and supplied to the data receiving section 4, where it is received. In a two-wire full-duplex data transmission device, the clock component contained in the signal transmitted from the main station and received is detected, the clock signal is extracted and reproduced, and the data is extracted from the received signal according to this clock signal. It receives and reproduces the data, and also encodes and transmits the transmitted data according to the clock signal. However, the transmission line 3 seen from the hybrid circuit 2
The circuit impedance of is not pure resistance. For this reason, data output from the transmitter 1 may leak to the receiver 4 via the hybrid circuit 2. This signal leakage has a significant adverse effect on the extraction and reproduction of the clock signal in the above device, leading to errors in data reception and reproduction due to the erroneous clock signal and erroneous encoding of transmitted data. In order to prevent this, a matching box shown at 5 in the figure is connected to the transmission line 3 via the hybrid circuit 2 to balance the circuit impedance. However, the circuit impedance of the transmission line 3 varies greatly depending on the line length. For this reason, it is difficult to adjust the balance of the matching box 5, and it is also very difficult to design the matching box 5 itself.

本発明はこのような事情を考慮してなされたも
ので、その目的とするところは、簡単な構成で経
済性がよく、しかもデータの漏洩による悪影響を
招くことのない二線式全二重データ伝送装置を提
供することにある。
The present invention was made in consideration of these circumstances, and its purpose is to provide two-wire full-duplex data that has a simple configuration, is economical, and does not cause any adverse effects due to data leakage. The purpose is to provide transmission equipment.

本発明の概要は、ラツチ信号の非印加時には受
信信号を通過させ、ラツチ信号の印加時にはその
直前の受信信号を所定時間(ラツチ信号の時間
幅)だけラツチ保持させるラツチ回路を介して受
信信号を取込み、このラツチ回路の出力信号から
クロツク信号を再生抽出することにより、ハイブ
リツド回路からの信号漏洩成分の受信部への入力
を阻止するようにしたものである。これにより整
合器の複雑な設計及び調整を不要とし、結局装置
の簡単化及び経済性の向上をはかつている。
The outline of the present invention is to pass the received signal when the latch signal is not applied, and to latch the previous received signal for a predetermined time (time width of the latch signal) when the latch signal is applied. By taking in the clock signal and reproducing and extracting the clock signal from the output signal of this latch circuit, input of the signal leakage component from the hybrid circuit to the receiving section is prevented. This eliminates the need for complicated design and adjustment of a matching box, resulting in a simpler and more economical device.

本発明は受信信号のパルス幅が、送信信号の漏
洩時間に比して長いことに着目してなされたもの
で、以下、第2図及び第3図を参照して本発明装
置の一実施例を説明する。
The present invention was made by focusing on the fact that the pulse width of the received signal is longer than the leakage time of the transmitted signal.Hereinafter, with reference to FIGS. 2 and 3, one embodiment of the device of the present invention will be described. Explain.

第2図は同実施例の装置の概略構成図で、図中
11は伝送線路である。この伝送線路11はハイ
ブリツド回路12に接続され、送受信されるデー
タを伝送している。このハイブリツド回路12の
送信端12aにはデータ送信部のエンコーダ回路
13が接続されている。このエンコーダ回路13
は後述する同期信号に基づいて送信データをエン
コードして前記伝送線路11に送出している。一
方、前記ハイブリツド回路12の受信端12bに
はデータ受信部のデコーダ回路14が接続される
と共にラツチ回路15が接続されている。このラ
ツチ回路15は、後述するラツチ信号を受けて、
ラツチ信号印加直前の受信信号をラツチし、ラツ
チ信号の印加期間これを保持すると共に、ラツチ
信号の非印加時には受信信号をそのまま通過させ
るもので、所謂サンプル・ホールド型のラツチ回
路として知られるものである。このラツチ回路1
5の出力端には同期抽出回路16が接続され、受
信信号中から同期信号を抽出している。即ち、こ
の同期抽出回路16は、例えば前記ラツチ回路1
5の出力信号である受信信号を微分し、その微分
波形の立上りおよび立下り信号に対応したパルス
信号を発生してこのパルス信号によりフリツプフ
ロツプを反転させる等して、前記受信信号に含ま
れる同期信号、即ちクロツク成分を抽出するもの
である。
FIG. 2 is a schematic configuration diagram of the device of the same embodiment, and numeral 11 in the figure is a transmission line. This transmission line 11 is connected to a hybrid circuit 12 and transmits data to be sent and received. An encoder circuit 13 of a data transmitting section is connected to a transmitting end 12a of this hybrid circuit 12. This encoder circuit 13
encodes transmission data based on a synchronization signal, which will be described later, and sends it to the transmission line 11. On the other hand, the receiving end 12b of the hybrid circuit 12 is connected to a decoder circuit 14 of a data receiving section and a latch circuit 15. This latch circuit 15 receives a latch signal, which will be described later, and
This circuit latches the received signal just before the latch signal is applied, holds it while the latch signal is applied, and passes the received signal as is when the latch signal is not applied, and is known as a sample-and-hold type latch circuit. be. This latch circuit 1
A synchronization extracting circuit 16 is connected to the output end of the signal generator 5, and extracts a synchronization signal from the received signal. That is, this synchronization extraction circuit 16 is, for example, the latch circuit 1.
By differentiating the received signal which is the output signal of 5, generating pulse signals corresponding to the rising and falling signals of the differentiated waveform, and inverting the flip-flop by this pulse signal, the synchronizing signal included in the received signal is generated. , that is, the clock component is extracted.

そして抽出された同期信号は前記エンコーダ回
路13及びデコーダ回路14に供給されると共
に、単安定マルチバイブレータ17に供給されて
いる。この単安定マルチバイブレータ17は上記
抽出された同期信号の立上り、及び立下りエツジ
にそれぞれ対応して所定時間幅のパルス信号を出
力し、これをラツチ信号として前記ラツチ回路1
5に印加している。尚、上記パルス信号の所定時
間幅は、前記抽出された同期信号の周期より短
く、且つ送信側からの信号の漏洩が生じる期間を
十分に含む期間に定められる。ラツチ回路15は
例えばこのパルス信号の立上りエツジによつてそ
の直前の入力データ、即ち受信信号をラツチし、
上記パルス信号がHIGHレベルの期間中、上記し
たラツチした信号を保持するものである。また上
記パルス信号が印加されないとき、つまりパルス
信号がLOWレベルのときには、前記受信信号は
ラツチ回路15をそのまま通過して、前記同期抽
出回路16に与えられる。つまり、パルス信号の
印加期間のみ受信信号が一時記憶されている。こ
のラツチ回路15、同期抽出回路16及び単安定
マルチバイブレータ17によつて信号検出回路が
構成されている。しかして前記伝送線路11を介
して伝送された信号は上記抽出された同期信号に
基づいてデコーダ回路14にてデコードされ、受
信信号中のデータが受信再生されて所定の機器に
出力される。なお図中18はハイブリツド回路1
2を介して伝送線路11に接続された整合器であ
る。
The extracted synchronization signal is supplied to the encoder circuit 13 and decoder circuit 14 as well as to the monostable multivibrator 17. This monostable multivibrator 17 outputs a pulse signal of a predetermined time width in response to the rising and falling edges of the extracted synchronization signal, and uses this as a latch signal to connect the latch circuit 1 to the latch circuit 1.
5 is applied. Note that the predetermined time width of the pulse signal is set to a period that is shorter than the period of the extracted synchronization signal and that sufficiently includes a period in which signal leakage from the transmitting side occurs. The latch circuit 15 latches the immediately preceding input data, that is, the received signal, by the rising edge of this pulse signal, for example,
The latched signal is held while the pulse signal is at HIGH level. Further, when the pulse signal is not applied, that is, when the pulse signal is at the LOW level, the received signal passes through the latch circuit 15 as it is and is applied to the synchronization extraction circuit 16. In other words, the received signal is temporarily stored only during the application period of the pulse signal. The latch circuit 15, the synchronization extraction circuit 16, and the monostable multivibrator 17 constitute a signal detection circuit. The signal transmitted via the transmission line 11 is decoded by the decoder circuit 14 based on the extracted synchronization signal, and the data in the received signal is received and reproduced and output to a predetermined device. In addition, 18 in the figure is the hybrid circuit 1
This is a matching box connected to the transmission line 11 via 2.

このように構成された装置の作用を第3図に示
す信号波形図を参照して説明する。
The operation of the device configured in this way will be explained with reference to the signal waveform diagram shown in FIG.

今、主局から伝送されたクロツク成分を含む第
3図aの実線で示す如き波形のバイポーラ型の信
号が受信されたとき、この信号はラツチ回路15
を介して同期抽出回路16に供給される。このよ
うなバイポーラ型の信号を受信した同期抽出回路
16は、上記信号の正負のユニポーラ成分をそれ
ぞれ検出し、各ユニポーラ成分の微分信号を求め
る等しい上記信号中から同期信号を第3図bに示
すように抽出している。前記デコーダ回路14
は、上記同期信号に従つて前記バイポーラ型の受
信信号の信号位相変化を検出する等して、バイポ
ーラ・ユニポーラ変換を行い、第3図aに示す受
信信号中から同図cに示すようにデータを受信再
生している。一方、エンコーダ回路13は、上記
同期信号に基づいて第3図dに示す送信データを
第3図eに示すように符号化して送信している。
この送信データの符号化は、例えば主局が伝送信
号に対するクロツク成分を有していることから、
ユニポーラ信号を上記抽出された同期信号に従つ
て単にバイポーラ化することにより行われる。こ
のようにして符号化されて送信される信号が先に
説明したようにハイブリツド回路12を介して受
信部への漏洩して受信側へ悪影響を及ぼす。即
ち、この漏洩信号は、あたかも送出信号を微分し
た如き波形として受信信号に重畳する。この為、
受信側にて受信される信号には前記第3図aの破
線で示すような、所謂ひげが生じる。このひげ
は、受信信号の微分処理等による同期抽出処理に
おいて、第3図bの破線で示すような擬同期信号
の発生を招くものである。この擬同期信号によつ
て装置の同期が乱され、誤つた信号処理が生じる
等の悪影響が生じていたのである。
Now, when a bipolar signal with a waveform as shown by the solid line in FIG. 3a, which includes a clock component transmitted from the main station, is received, this signal is
The signal is supplied to the synchronization extraction circuit 16 via. Upon receiving such a bipolar signal, the synchronization extraction circuit 16 detects the positive and negative unipolar components of the signal, and calculates the differential signal of each unipolar component.The synchronization extraction circuit 16 extracts the synchronization signal from the equal signals as shown in FIG. 3b. It is extracted as follows. The decoder circuit 14
performs bipolar-unipolar conversion by detecting the signal phase change of the bipolar received signal according to the synchronization signal, and converts the received signal shown in FIG. 3a to data as shown in FIG. 3c. are receiving and playing. On the other hand, the encoder circuit 13 encodes the transmission data shown in FIG. 3d as shown in FIG. 3e based on the synchronization signal and transmits the encoded data.
This encoding of the transmission data is done because, for example, the main station has a clock component for the transmission signal.
This is done by simply converting the unipolar signal into bipolar according to the extracted synchronization signal. The signal encoded and transmitted in this manner leaks to the receiving section via the hybrid circuit 12, as described above, and has an adverse effect on the receiving side. That is, this leakage signal is superimposed on the received signal as a waveform as if the transmitted signal was differentiated. For this reason,
A so-called whisker occurs in the signal received at the receiving side, as shown by the broken line in FIG. 3a. This whisker causes the generation of a pseudo-synchronization signal as shown by the broken line in FIG. 3b during synchronization extraction processing such as differential processing of the received signal. This pseudo-synchronization signal disrupts the synchronization of the device, causing adverse effects such as erroneous signal processing.

然るに、本装置では、前記抽出された同期信号
の立上り、及び立下りエツジによつて単安定マル
チバイブレータ17が作動し、第3図fに示すよ
うな所定の時間、HIGHレベルのパルス信号が出
力されてラツチ回路15が駆動される。尚、この
パルス信号の上記所定時間幅は、前述したように
前記同期信号のパルス幅に比して短かく、且つ前
記信号漏洩時間に比して十分長いものである。従
つてラツチ回路15はこのパルス信号の立上りエ
ツジによつてその直前の受信信号をラツチし、前
記したようにこのラツチした信号をパルス信号が
印加されている所定の時間保持する。従つて前記
第3図aに示した信号の漏洩成分はラツチ回路1
5でその通過が阻止され、同期抽出回路16に供
給されることがない。つまり、ラツチ回路15に
よつて第3図gに示す期間、漏洩信号の通過が阻
止される。従つて、同期抽出回路16には、第3
図aの実線で示す、本来の受信信号成分のみが供
給されることになる。
However, in this device, the monostable multivibrator 17 is activated by the rising and falling edges of the extracted synchronization signal, and a HIGH level pulse signal is output for a predetermined period of time as shown in FIG. As a result, the latch circuit 15 is driven. Note that the predetermined time width of this pulse signal is shorter than the pulse width of the synchronizing signal and sufficiently longer than the signal leakage time, as described above. Therefore, the latch circuit 15 latches the immediately preceding received signal by the rising edge of this pulse signal, and holds this latched signal for a predetermined period of time during which the pulse signal is applied, as described above. Therefore, the leakage component of the signal shown in FIG.
5, its passage is blocked and it is not supplied to the synchronization extraction circuit 16. That is, the latch circuit 15 prevents the leakage signal from passing during the period shown in FIG. 3g. Therefore, the synchronization extraction circuit 16 includes a third
Only the original received signal component shown by the solid line in Figure a will be supplied.

かくして本装置によれば従来装置のように漏洩
信号による悪影響が生じることがなく、良好なデ
ータ送受を行うことができる。また特に整合器1
8を微細に調整しなくても漏洩信号による悪影響
を除去することができ、整合器18の複雑な調整
や、厳密な設計を要すことがない。従つて装置の
簡素化をはかることが可能である。更に受信信号
をラツチして漏洩信号を阻止すると言う簡単な構
成で、しかもデジタル回路等で容易に実現するこ
とができ、装置として非常に経済的である。また
回線の接続切換によつて回線の回路インピーダン
スが大幅に変化した場合でも殆んど不都合を招く
ことがない。
Thus, according to the present device, unlike conventional devices, there is no adverse effect caused by leaked signals, and data can be transmitted and received favorably. Also, especially matching box 1
The negative influence of the leakage signal can be removed without finely adjusting the matching box 18, and no complicated adjustment or strict design of the matching box 18 is required. Therefore, it is possible to simplify the device. Furthermore, it has a simple configuration in which the received signal is latched to prevent leakage signals, and it can be easily realized using a digital circuit or the like, making the device extremely economical. Further, even if the circuit impedance of the line changes significantly due to connection switching of the line, there is almost no problem.

なお本発明は上記実施例に限定されるものでは
ない。例えば伝送信号の形態が、上記説明のバイ
ポーラ型ではなく、ユニポーラ型であつてもよ
い。また同期信号の抽出手段や、所定時間の生成
手段等は、その仕様や用途に応じて設定すればよ
いものである。更にデコーダ回路14に供給する
信号は、第2図中破線で示すようにラツチ回路1
5の出力から得るようにしてもよい。またこの装
置を介して伝送される信号の種類も、例えば符号
化音声信号とか計算機のデータ信号とかに限定さ
れないことは勿論である。要するに、本発明は、
その要旨を逸脱しない範囲で種々変形して実施す
ることができる。
Note that the present invention is not limited to the above embodiments. For example, the form of the transmission signal may be a unipolar type instead of the bipolar type described above. Further, the means for extracting a synchronization signal, the means for generating a predetermined time, etc. may be set according to the specifications and uses thereof. Furthermore, the signal supplied to the decoder circuit 14 is supplied to the latch circuit 1 as shown by the broken line in FIG.
It may be obtained from the output of 5. Furthermore, it goes without saying that the type of signal transmitted via this device is not limited to, for example, a coded audio signal or a computer data signal. In short, the present invention:
Various modifications can be made without departing from the gist of the invention.

以上詳述したように本発明に係る装置は送信信
号の送信時直前の受信信号を所定時間づつラツチ
保持することによつて、漏洩信号の流れ込みを阻
止するようにしたものである。従つて本発明によ
れば整合器の精密な調整や、厳密な設計を全く要
することなく装置の簡略化及び経済性の向上をは
かることができ、しかも信号の漏洩による悪影響
の発生を効果的に除去した良好なデータの送受が
できる等の種々格別の利点を有する二線式全二重
データ伝送装置を提供することができる。
As described in detail above, the apparatus according to the present invention prevents leakage signals from flowing in by holding the received signal immediately before the transmission of the transmitted signal for a predetermined period of time. Therefore, according to the present invention, it is possible to simplify the device and improve its economical efficiency without requiring precise adjustment of the matching box or strict design at all, and moreover, it is possible to effectively prevent the occurrence of adverse effects due to signal leakage. It is possible to provide a two-wire full-duplex data transmission device that has various special advantages, such as being able to transmit and receive data with improved quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は二線式全二重データ伝送装置の概略
図、第2図は本発明装置の一実施例を示す概略構
成図、第3図は同実施例の作用を説明する為の信
号波形図である。 11…伝送線路、12…ハイブリツド回路、1
3…エンコーダ回路(データ送信部)、14…デ
コーダ回路(データ受信部)、15…ラツチ回
路、16…同期抽出回路、17…単安定マルチバ
イブレータ。
Fig. 1 is a schematic diagram of a two-wire full-duplex data transmission device, Fig. 2 is a schematic configuration diagram showing an embodiment of the device of the present invention, and Fig. 3 is a signal waveform for explaining the operation of the embodiment. It is a diagram. 11...Transmission line, 12...Hybrid circuit, 1
3... Encoder circuit (data transmitting section), 14... Decoder circuit (data receiving section), 15... Latch circuit, 16... Synchronization extraction circuit, 17... Monostable multivibrator.

Claims (1)

【特許請求の範囲】[Claims] 1 二線式全二重データ伝送線路にハイブリツド
回路を介して接続され、主局からのクロツク成分
を含む受信信号からクロツク信号を抽出し、この
クロツク信号に従つて上記受信信号中のデータを
受信再生すると共に、上記クロツク信号に従つて
送信データを符号化して送信する二線式全二重デ
ータ伝送装置において、受信部は、ラツチ信号の
非印加時に受信信号を通過させると共に、上記ラ
ツチ信号のトレーリングエツジにおける受信信号
をラツチ信号印加期間保持してなるラツチ回路の
出力信号から受信信号中のクロツク信号を抽出
し、この抽出したクロツク信号に従つてクロツク
信号周期より短い所定時間幅の前記ラツチ信号を
生成してなることを特徴とする二線式全二重デー
タ伝送装置。
1 Connected to a two-wire full-duplex data transmission line via a hybrid circuit, extracts a clock signal from a received signal containing a clock component from the main station, and receives data in the received signal according to this clock signal. In a two-wire full-duplex data transmission device that encodes and transmits transmission data in accordance with the clock signal, the receiving section passes the received signal when the latch signal is not applied, and also transmits the received signal when the latch signal is not applied. The clock signal in the received signal is extracted from the output signal of a latch circuit that holds the received signal at the trailing edge for a latch signal application period, and the latch is activated in accordance with the extracted clock signal with a predetermined time width shorter than the clock signal period. A two-wire full-duplex data transmission device characterized by generating signals.
JP4217777A 1977-04-13 1977-04-13 Full duplex data transmission unit of two wire type Granted JPS53127221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4217777A JPS53127221A (en) 1977-04-13 1977-04-13 Full duplex data transmission unit of two wire type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4217777A JPS53127221A (en) 1977-04-13 1977-04-13 Full duplex data transmission unit of two wire type

Publications (2)

Publication Number Publication Date
JPS53127221A JPS53127221A (en) 1978-11-07
JPS6149859B2 true JPS6149859B2 (en) 1986-10-31

Family

ID=12628693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4217777A Granted JPS53127221A (en) 1977-04-13 1977-04-13 Full duplex data transmission unit of two wire type

Country Status (1)

Country Link
JP (1) JPS53127221A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63181612U (en) * 1987-05-15 1988-11-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63181612U (en) * 1987-05-15 1988-11-24

Also Published As

Publication number Publication date
JPS53127221A (en) 1978-11-07

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