JPS6150258B2 - - Google Patents

Description

[Detailed Description of the Invention] A window comparator that detects whether the wave height of a signal falls within a desired voltage range has conventionally been implemented using a pair of operational amplifiers or a circuit consisting of one operational amplifier and two diodes. It was used. However, such a window comparator using an analog amplifier is expensive and requires a complicated circuit to obtain a reference voltage for comparison.
Furthermore, when a diode is used, it is affected by its temperature characteristics, so it has drawbacks such as not being able to perform stable operation. The present invention relates to logic circuits, particularly C. Moss. By using an integrated logic circuit using transistors, it can be manufactured extremely easily and at low cost.
Moreover, the present invention provides a window comparator that operates stably and reliably and whose detection reference voltage can be easily adjusted.

FIG. 1 shows a circuit according to an embodiment of the present invention.
A DC voltage source is connected to terminal E, a detected signal is applied to terminal I, and an output signal is taken out from terminal O. Although not shown, the power supply connected to terminal E is also used as a power supply for logic circuit L, and each element is connected to C. Moss. It is composed of transistors and has a threshold voltage of one half of the power supply voltage E. Power supply terminal E has voltage dividing resistors R1, R2,
Connect R3 in series and tap t at the connection.
1, t2 are the two input terminals T1,
T2 respectively, and a resistor R to tap t2.
0 and a capacitor C0, a bypass capacitor C1 is inserted between taps t1 and t2, and a capacitor C2 for removing high frequency noise voltage is connected to tap t2. be. Furthermore, the logic circuit L is configured as one integrated circuit, and the NAND gate A
The two input terminals of NAND gate A1 and A2 are short-circuited and connected to input terminals T1 and T2, respectively, and the output terminal of NAND gate A1 is connected to the two input terminals of NAND gate A3, and the output terminal of NAND gate A4 is connected to the output terminal of NAND gate A3 and A2. The two input terminals are connected to each other, and the output terminal of this NAND gate A4 is connected to the terminal O.

Figure 2 shows the circuit of Figure 1 with p, q and a, b,
This shows the waveforms of each part shown in c and d, and when half of the power supply voltage, that is, the threshold voltage of each element in the logic circuit L, is represented by the chain line e,
The input terminals T1 and T2 are shown as (e+
The voltages given by α) and (e−β) are applied. Therefore, the signals "1" and "0" are applied to the two input terminals of the NAND gates A1 and A2, respectively, and the output signal of the terminal O becomes "0". However, if a signal with an arbitrary waveform, for example a sine wave voltage, is applied to input terminal I, the voltages at terminals T1 and T2 will change as shown by p and q in Figure 2, and this voltage will become the threshold. When the voltage e is exceeded, the outputs of the NAND gates A1 and A2 are inverted. Therefore, the signals at portions a, b, c, and d in FIG. 1 change as indicated by the same reference numerals in FIG. 2. That is, assuming that the impedances of capacitors C0, C1 and resistor R0 are sufficiently low, when a signal voltage higher than +α or lower than -β is applied to input terminal I, a signal "1" is sent from output terminal O.
When the input signal voltage is between -β and +α, a signal “0” is sent out.

In addition, in FIG. 3, the input terminal I is connected to tap t1 of the voltage dividing resistor in FIG. 1 via a capacitor C0 and a resistor R0, and in FIG.
Divide the resistor R2 in the figure into R2 ₁ and R2 ₂ , connect the input terminal I to the tap t0 between them, and connect the input terminal I to the tap t0 between them.
0 and taps t1 and t2.
₁ , C1, _{and 2} are inserted, and even in such a circuit, the operation is exactly the same as that shown in FIG. Furthermore, FIG. 5 shows that the NAND gates A1, A2, A3 in the logic circuit L of FIG. 1 are replaced with NAND gates B1, B2,
B3 is replaced, and the same operation as in FIG. 1 is performed. In other words, since the NAND gate or NOR gate described above both performs the function of a logical NOT circuit, they can be converted into a NOT circuit N as shown in FIG.
1, N2, and N3. Furthermore, since the effects of the negative circuits N1 and N3 in FIG. 6 cancel each other out, it is also possible to omit them and configure as shown in FIG. A similar output signal can also be obtained by connecting an inverting circuit N4 to and replacing the NAND gate A4 with an OR gate B4. Note that the logic circuits L described above are all designed to send out a signal "1" when the input signal voltage occurs +α or -β, but conversely, they send out a signal "1" when the input signal voltage is within the above range. In order to send out a signal "0" when this range is exceeded, the logic operation circuit A4 or B4 at the output end in each figure is replaced with an AND gate and a NOR gate, respectively.

As explained above with respect to the embodiments, the present invention configures a window comparator using a logic circuit and a voltage dividing circuit, and does not use an analog amplifier or the like, so it operates extremely reliably and stably, and the circuit configuration is also simple. It's easy. Especially as a logic circuit, CMOS
By using an integrated circuit using transistors, it can be manufactured at extremely low cost and power consumption can be extremely reduced. Further, since a logic circuit is used, the temperature characteristics are good, and the detection range can be easily changed by adjusting the voltage dividing circuit, so adjustment is easy.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, and Fig. 2 is a circuit diagram of an embodiment of the present invention.
Waveform diagram for explaining the operation of the device shown in Figure 3.
Figures 4, 5, 6, 7 and 8
Each figure shows a part of other circuit examples in FIG. 1. In the figure, I is the input terminal of the detected signal, O is the output terminal, E is the power supply terminal, A1, A2,
A3, A4 are NAND gates, B1, B2, B3 are Noah gates, B4 is OR gates, N1, N2, N
3, N4 is a negative circuit.

Claims (1)

[Claims] 1. A logic circuit that adds signals from two input terminals to a two-input logic operation circuit in which one input terminal is connected to a logic negation circuit that is an integer number more than the other input terminal, and a voltage dividing resistor connected to a DC voltage source. A voltage divider circuit in which the two taps are connected to the two input terminals of the logic circuit, and the threshold voltage of the logic circuit is located between the two tap voltages, and a capacitor is connected to any tap in the voltage divider circuit. A window comparator characterized in that an input terminal of a detected signal is connected via a.