JPS6151266B2 - - Google Patents
Info
- Publication number
- JPS6151266B2 JPS6151266B2 JP52053286A JP5328677A JPS6151266B2 JP S6151266 B2 JPS6151266 B2 JP S6151266B2 JP 52053286 A JP52053286 A JP 52053286A JP 5328677 A JP5328677 A JP 5328677A JP S6151266 B2 JPS6151266 B2 JP S6151266B2
- Authority
- JP
- Japan
- Prior art keywords
- square
- difference
- biparabolic
- multiplier
- sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
- G01R21/10—Arrangements for measuring electric power or power factor by using square-law characteristics of circuit elements, e.g. diodes, to measure power absorbed by loads of known impedance
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
- G01R21/133—Arrangements for measuring electric power or power factor by using digital technique
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division
- G06G7/164—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division using means for evaluating powers, e.g. quarter square multiplier
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Measurement Of Current Or Voltage (AREA)
- Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
Description
【発明の詳細な説明】
この発明は電気エネルギーあるいは出力測定の
ための二放物線掛算器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a biparabolic multiplier for measuring electrical energy or power.
静的な手段で電気エネルギーあるいは出力を測
定するための多くの方法が知られている。このた
め必要な電圧と電流の積は数式
(u+i)2−(u−i)2=4ui
を用いた二放物線掛算器を利用してつくられる。
ここでuは電圧の瞬時値を、iは電流の瞬時値を
意味する。変数uとiの和と差の二乗を形成する
ために多角形線により必要な二乗特性を近似した
二乗特性素子の利用することができる。また半導
体素子の二乗特性を近似的に利用することも知ら
れている。さらに二乗特性素子として熱変換器と
実効値変換器を利用することができる。 Many methods are known for measuring electrical energy or power by static means. Therefore, the required product of voltage and current is created using a biparabolic multiplier using the formula (u+i) 2 -(u-i) 2 =4ui.
Here, u means the instantaneous value of voltage, and i means the instantaneous value of current. In order to form the square of the sum and difference of variables u and i, it is possible to use a square characteristic element that approximates the necessary square characteristic by a polygonal line. It is also known to approximately utilize the square-law characteristic of semiconductor elements. Furthermore, a heat converter and an effective value converter can be used as square characteristic elements.
この二放物線による方法は二つの値の差から掛
け算結果が形成されるという点で根本的な欠点が
ある。例えば電源電圧が有限の値を有し負荷電流
が0ならば二放物線掛算器は差u2−u2=0を形成
する。しかし両方の二乗特性素子の放物線関数は
実際上同一ではないので大きな測定誤差が生じ
る。 This biparabolic method has a fundamental drawback in that the multiplication result is formed from the difference between two values. For example, if the supply voltage has a finite value and the load current is zero, the biparabolic multiplier forms the difference u 2 −u 2 =0. However, the parabolic functions of both square characteristic elements are not practically identical, resulting in large measurement errors.
また二乗特性素子を一つだけ用いた放物線掛算
器も知られており、この二乗特性素子には、ダイ
オード回路を用いて変数の和と差、詳しくは電源
電圧の正の半波期間の和と負の半波期間の差がそ
れぞれ交互に印加される。この場合ダイオード回
路のダイオードにおける電圧降下は、顕著な測定
誤差の原因となりうる。特にダイオードの非対称
は零点誤差を引き起こす。さらにまた電源電圧と
電源電流における高調波は正しく測定されない。 A parabolic multiplier using only one square characteristic element is also known, and this square characteristic element uses a diode circuit to calculate the sum and difference of variables, more specifically, the sum and difference of the positive half-wave period of the power supply voltage. Each negative half-wave period difference is applied alternately. In this case, voltage drops across the diodes of the diode circuit can cause significant measurement errors. In particular, diode asymmetry causes zero point errors. Furthermore, harmonics in the supply voltage and current are not measured correctly.
本発明はこれら欠点を克服するもので、零点誤
差を有しない二放物線掛算器を提供することを目
的とする。 The present invention overcomes these drawbacks and aims to provide a biparabolic multiplier without zero point errors.
次に本発明の二つの実施例を添付図面を参照し
て詳細に説明する。 Next, two embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第1図において1は変流器を示し、その一次巻
線には負荷電流が流れ、また、その二次巻線は
リード線2,3を介して二乗特性素子5′と5″の
入力4′と4″に接続される。入力4′と4″は抵抗
6′と6″を介して電源電圧Uに接続される。二乗
特性素子5′と5″の出力7′と7″はリード線8,
9を介して減算器12の入力10,11に接続さ
れる。リード線2,3には極性切換スイツチ13
が、リード線8,9には極性切換スイツチ14が
接続される。たとえばCMOS−アナログ・スイツ
チから構成されるこの極性切換スイツチは、クロ
ツク発生器15により制御される。クロツク発生
器15はクロツク周波数ftと同じ長さの半サイ
クルTaとTbを有する対称な矩形パルス列を発生
する。 In FIG. 1, 1 indicates a current transformer, the load current flows through its primary winding, and the input 4 of the square characteristic elements 5' and 5'' flows through the secondary winding through lead wires 2 and 3. ' and 4''. Inputs 4' and 4'' are connected to the supply voltage U via resistors 6' and 6''. The outputs 7' and 7'' of the square characteristic elements 5' and 5'' are connected to the lead wire 8,
9 to the inputs 10, 11 of the subtractor 12. A polarity switch 13 is attached to the lead wires 2 and 3.
However, a polarity changeover switch 14 is connected to the lead wires 8 and 9. This polarity switch, which may consist of a CMOS-analog switch, for example, is controlled by a clock generator 15. Clock generator 15 generates a symmetrical rectangular pulse train having half cycles T a and T b of the same length as the clock frequency f t .
変流器1と抵抗6′と6″は加算器と減算器を構
成する。 Current transformer 1 and resistors 6' and 6'' constitute an adder and a subtracter.
半サイクルTa間では、二乗特性素子5′の入力
4′における入力電流Ie1と二乗特性素子5″の入
力4″における入力電流Ie2に対してそれぞれ
Ie1a=Iu+Ii
Ie2a=Iu−Ii
が成り立つ。ただしIuは抵抗6′または6″にお
ける電流をIiは変流器1の二次巻線における電
流を意味する。 During the half cycle T a , for the input current I e1 at the input 4' of the square characteristic element 5' and the input current I e2 at the input 4'' of the square characteristic element 5'', I e1a = I u + I i I e2a = I u −I i holds true. where I u means the current in the resistor 6' or 6'', and I i means the current in the secondary winding of the current transformer 1.
二乗特性素子5′と5″は入力電流Ie1ないしI
e2の二乗に比例する出力電流Ia1を発生する。 The square characteristic elements 5' and 5'' are connected to the input current I e1 to I
Generates an output current I a1 proportional to the square of e2 .
Ia1a=k1・Ie1a 2=k1(Iu+Ii)2 Ia2a=k2・Ie2a 2=k2(Iu−Ii)2 ただしk1とk2は定数を意味する。I a1a = k 1・I e1a 2 = k 1 (I u + I i ) 2 I a2a = k 2・I e2a 2 = k 2 (I u −I i ) 2 However, k 1 and k 2 mean constants .
減算器12の出力におけける電圧Uaに対して
は、
Uaa=k3(Ia1a−Ia2a)
=k3〔k1(Iu+Ii)2−k2(Iu−Ii)2〕
が成り立つ。ただしk3もまた定数である。 For the voltage U a at the output of the subtractor 12, U aa = k 3 (I a1a - I a2a ) = k 3 [k 1 (I u + I i ) 2 - k 2 (I u - I i ) 2 ] holds true. However, k 3 is also a constant.
一方半サイクルTb間では両方の二乗特性素子
5′と5″は機能的に互いに入れ換るので
Ie1b=Iu−Ii
Ie2b=Iu+Ii
Ia1b=k1(Iu−Ii)2
Ia2b=k2(Iu+Ii)2
Uab=k3〔k2(Iu+Ii)2−k1(Iu−Ii)2〕
が成り立つ。 On the other hand, during half-cycle T b , both square-law characteristic elements 5' and 5'' functionally replace each other, so I e1b = I u - I i I e2b = I u + I i I a1b = k 1 (I u - I i ) 2 I a2b =k 2 (I u +I i ) 2 U ab =k 3 [k 2 (I u +I i ) 2 −k 1 (I u −I i ) 2 ] holds.
電圧Uaの時間的な平均値aはa =Uaa+Uab/2=2k3(k1+k2)・Iu・Ii になる。 The temporal average value a of the voltage U a is a = U aa + U ab /2 = 2k 3 (k 1 + k 2 )·I u ·I i .
電流IuとIiは電源電圧Uと消費電流Iの瞬時
値に相当する。したがつて、a
=2k3(k1+k2)・〓/R・U・I・cos
となる。ただしU¨は変粒器1の変圧比、Rは抵抗
6′,6″の抵抗値、cosは位相角を示す。 Currents I u and I i correspond to instantaneous values of power supply voltage U and current consumption I. Therefore, a = 2k 3 (k 1 +k 2 )·〓/R·U·I·cos. However, U¨ is the transformation ratio of the granule transformer 1, R is the resistance value of the resistors 6' and 6'', and cos is the phase angle.
二乗特性素子5′,5″が周期的に入れ換るので
測定結果には零点誤差は発生しない。クロツク周
波数ftの選択には特別の条件はなく、電源周波
数より大きくても小さくてもよい。各時点におい
て変数の和の二乗と差の二乗が形成されるので電
源高調波の測定は正しく行われる。 Since the square characteristic elements 5' and 5'' are periodically exchanged, no zero point error occurs in the measurement results. There are no special conditions for selecting the clock frequency f t , and it may be greater or less than the power supply frequency. .The measurement of power supply harmonics is performed correctly because at each point in time, the square of the sum and the square of the difference of the variables are formed.
第2図において第1図の参照番号と同じ参照番
号は同じ部分を示している。二乗特性素子として
ここでは制御入力17′と17″と出力18′と1
8″を有する制御可能な発振器16′と16″が用
いられる。これらの出力は極性切換スイツチ14
を介して減算器として作動する可逆カウンター2
1の後進カウント入力19と前進カウント入力2
0に接続される。 In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same parts. Here, control inputs 17' and 17'' and outputs 18' and 1 are used as square characteristic elements.
Controllable oscillators 16' and 16'' with 8'' are used. These outputs are connected to the polarity switch 14.
Reversible counter 2 that operates as a subtractor through
1 backward count input 19 and forward count input 2
Connected to 0.
制御可能な発振器16′と16″はパルス列を発
生しそのパルス周波数fa1またはfa2は制御信号
Ie1またはIe2の二乗に関係する。このような発
振器はよく知られているのでここでは詳細に説明
しない。例えば時分割掛算器において、しばしば
マーク・スペース変調器として用いられる発振器
を利用することができる。そしてその関係は、
fa=f0〔1−Ie/Ir)2〕
を満たす。ただしf0はIe=0でのパルス周波数
をIrは定数を意味する。 Controllable oscillators 16' and 16'' generate a pulse train whose pulse frequency f a1 or f a2 is related to the square of the control signal I e1 or I e2 . Such oscillators are well known and will not be described in detail here. For example, in a time-sharing multiplier, an oscillator often used as a mark-space modulator can be used, and the relationship f a = f 0 [1-I e /I r ) 2 ] However, f 0 means the pulse frequency at I e =0, and I r means a constant.
この種の発振器を利用す場合、半サイクルTa
間では、
fa1a=f01〔1−(Iu+Ii)2/Iri 2〕
fa2a=f02〔1−(Iu−Ii)2/Ir2 2〕
が成り立つ。 When using this kind of oscillator, half cycle T a
In between, f a1a =f 01 [1-(I u +I i ) 2 /I ri 2 ] f a2a = f 02 [1-(I u -I i ) 2 /I r2 2 ] holds.
可逆カウンター21は分周比Nで分周された両
パルス周波数fa2とfa1の差を形成する。可逆カ
ウンターの出力にはパルス周波数sのパルス列
が発生し半サイクルTa間に対しては
fsa=fa2a−fa1a/N
が成り立つ。一方半サイクルTb間では、発振器
16′と16″は機能的には互いに入れ換えるの
で、今度は
fa1b=f01〔1−(Iu−Ii)2/Ir1 2〕
fa2b=f02〔1−(Iu+Ii)2/Ir2 2〕
fsb=fa1b−fa2b/N
が成り立つ。 The reversible counter 21 forms the difference between the two pulse frequencies f a2 and f a1 divided by the frequency division ratio N. A pulse train of pulse frequency s is generated at the output of the reversible counter, and f sa = f a2a - f a1a /N holds true for half cycle T a . On the other hand, during the half cycle T b , the oscillators 16' and 16'' functionally replace each other, so now f a1b = f 01 [1-(I u - I i ) 2 /I r1 2 ] f a2b = f 02 [1-(I u +I i ) 2 /I r2 2 ] f sb = f a1b - f a2b /N holds true.
パルス周波数fsの平均値fsはs
=fsa+fsb/2=2/N(f01/Ir1 2
+f02/Ir2 2)・Iu・Ii
になり、これには実効電力の尺度を表わし、一方
可逆カウンター21のその時々のカウント状態は
電気出力に相当する。この場合もまた測定結果に
は零点誤差が生じないことがわかる。 The average value f s of the pulse frequency f s is s = f sa + f sb /2 = 2/N (f 01 /I r1 2
+f 02 /I r2 2 )·I u ·I i , which represents a measure of the effective power, while the current counting state of the reversible counter 21 corresponds to the electrical output. It can be seen that in this case as well, no zero point error occurs in the measurement results.
第1図は本発明の一実施例による電圧出力を有
する二放物線掛算器の回路図、第2図は本発明の
他の実施例による周波数出力を有する二放物線掛
算器の回路図である。
1……変流器、5′,5″,16′,16……二
乗特性素子、13,14……切換スイツチ、15
……クロツク発生器、21……可逆カウンター。
FIG. 1 is a circuit diagram of a biparabolic multiplier with a voltage output according to one embodiment of the present invention, and FIG. 2 is a circuit diagram of a biparabolic multiplier with a frequency output according to another embodiment of the present invention. 1... Current transformer, 5', 5'', 16', 16... Square characteristic element, 13, 14... Changeover switch, 15
...Clock generator, 21...Reversible counter.
Claims (1)
数の和と差を形成するための加算器と減算器と、
この変数の和の二乗と差の二乗を形成するための
二つの二乗特性素子を有し、さらにこの変数の和
の二乗と差の二乗の差を形成するための減算器を
有する二放物線掛算器において、クロツク発生器
15により制御されるスイツチ13,14を設け
前記両二乗特性素子5′,5″,16′,16″を機
能上周期的に入れ替えるようにしたことを特徴と
する電気エネルギーあるいは出力測定のための二
放物線掛算器。 2 特許請求の範囲第1項に記載の二放物線掛算
器において、スイツチ13,14は二乗特性素子
5′,5″,16′,16″の入力4′,4″,1
7′,17″と出力7′,7″,18′,18″に接続
された極性切換スイツチであることを特徴とする
前記の二放物線掛算器。[Claims] 1. An adder and a subtracter for forming the sum and difference of two variables proportional to power supply voltage or current consumption;
A biparabolic multiplier having two square characteristic elements for forming the square of the sum and the square of the difference of this variable, and further having a subtractor for forming the difference of the square of the sum and the square of the difference of this variable. , characterized in that switches 13 and 14 controlled by a clock generator 15 are provided to periodically replace the double-square characteristic elements 5', 5'', 16', and 16'' functionally. Biparabolic multiplier for output measurement. 2. In the biparabolic multiplier according to claim 1, the switches 13 and 14 are connected to the inputs 4', 4'', 1 of the square characteristic elements 5', 5'', 16', 16''.
7', 17'' and a polarity changeover switch connected to outputs 7', 7'', 18', 18''.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH763176A CH607038A5 (en) | 1976-06-15 | 1976-06-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52153780A JPS52153780A (en) | 1977-12-21 |
| JPS6151266B2 true JPS6151266B2 (en) | 1986-11-07 |
Family
ID=4328127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5328677A Granted JPS52153780A (en) | 1976-06-15 | 1977-05-11 | Dual parabola multiplier for measuring electric energy or output |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS52153780A (en) |
| CH (1) | CH607038A5 (en) |
| DE (1) | DE2632192C2 (en) |
| FR (1) | FR2355297A1 (en) |
| NL (1) | NL7608157A (en) |
-
1976
- 1976-06-15 CH CH763176A patent/CH607038A5/xx not_active IP Right Cessation
- 1976-07-16 DE DE19762632192 patent/DE2632192C2/en not_active Expired
- 1976-07-22 NL NL7608157A patent/NL7608157A/en not_active Application Discontinuation
-
1977
- 1977-05-11 JP JP5328677A patent/JPS52153780A/en active Granted
- 1977-06-13 FR FR7718047A patent/FR2355297A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52153780A (en) | 1977-12-21 |
| DE2632192C2 (en) | 1977-11-24 |
| CH607038A5 (en) | 1978-11-30 |
| FR2355297A1 (en) | 1978-01-13 |
| DE2632192B1 (en) | 1977-03-31 |
| NL7608157A (en) | 1977-12-19 |
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