JPS6151396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a light control device that controls the lighting phase of a lighting load using lighting phase control data stored in a memory.

Generally, lighting load dimmer devices used for stage lighting, showroom lighting, etc. have a dimming range of 0 to 100%, allowing any desired lighting intensity to be obtained, but the lighting intensity can also be reversed. That is, if a lighting load with an illumination intensity of about Z% can be changed to an illumination intensity of about (100-Z)% by a switching signal, an effective presentation effect may be obtained.
For example, if you simultaneously invert the illumination intensity of two lighting loads placed on the left and right, the illuminance distribution will be reversed and the shadows will change.
By reversing the lighting intensity of each lighting load (blue), it is possible to provide lighting with completely different hues.
Complementary color lighting can also be easily realized, and a wide range of production effects can be obtained.

However, conventionally, as this type of light control device,
The lighting phase control data stored in the main memory is written to the buffer memory during the H level period of the power synchronization signal which becomes H level near the zero cross point of the AC power supply, and the lighting phase control data is read from the buffer memory during the L level period of the power synchronization signal. In some conventional examples, lighting phase control data for inverting the lighting load must be stored in the main memory to perform the above-mentioned lighting intensity operation. It is necessary to separately store the lighting phase control data in addition to the lighting phase control data for normal operation, and there are problems in that the capacity of the main memory is doubled, and the writing and reading circuits of the main memory are complicated, making it uneconomical.

The present invention aims to solve the above problems.

Examples will be described below using figures. 1st
Figures 5 to 5 show a light control device that can adjust the brightness of eight lighting loads _{80 to 87} in 64 levels _. The outputs of the dimming level setting faders ₁₀ to ₁₇ are sequentially input to the A/D converter 3 through the multiplexer 2, and the lighting phase control data digitized by the A/D converter 3 is stored in the main memory 4. Stored in addresses corresponding to the lighting loads ₈₀ to ₈₇ ,
The lighting phase control data stored in the main memory 4 is transmitted to each of the lighting loads 8 ₀ to 8 ₇ via the switch 5 during the H level period It is designed to write to the corresponding bits of each register L ₀ to L ₇ of the provided buffer memory 6, and each bit of this register L ₀ to _{L 7} divides the L level period Y of the power synchronization signal into n pieces. The lighting phase control section corresponds to each lighting phase control section. The lighting phase control data written in the buffer memory 6 in this manner is read out from the buffer memory 6 by the read counter 12 during the L level period Y of the power synchronization signal and is applied to the switching element T of the drive circuit ₇ of the lighting loads ₈₀ to 87. In addition to controlling each firing phase of ₀ to _T7 , the buffer memory 6 is cleared immediately after the lighting phase control data is read out. The width and number n of the lighting phase control sections are set by the clock frequency and count number input to the read counter 12. Figure 2 shows a specific example of a power synchronization signal generation circuit, in which the pulsating voltage obtained by step-down rectifying the AC power supply AC with a transformer Tr and diode bridge D is input to the terminal of the operational amplifier OP.
When this pulsating voltage is smaller than the reference voltage Vs applied to the terminals of the operational amplifier OP, the output of the operational amplifier OP becomes H level, and as shown in Figure 6, it becomes H level near the zero cross point of the AC power supply AC. A power supply synchronization signal that becomes the level can be obtained. FIG. 8 shows a specific example of the control circuit 10, in which an oscillation circuit PG operates at the rise and fall of a power synchronization signal, and a clock signal B is generated by slightly delaying the output A of this oscillation circuit PG by a delay circuit CR. , B' is at the H level of the power synchronization signal, write counter 1
1, when the power synchronization signal is at L level, it is input to the read counter 12, and the respective counters 11, 1
After 2 has counted a predetermined number of counts, the operation of the oscillation circuit PG is stopped by a carry output, and the same operation is repeated with the next power synchronization signal. FIG. 7 shows a time chart of each signal A to F. By the way, as shown in FIG. 5, the read counter 12 is equipped with an output switching circuit 12b consisting of exclusive OR circuits ₀₀ to ₀₇ corresponding to the respective outputs of the counter circuit 12a and a changeover switch SW. The output is a positive logic output when the changeover switch SW is switched to the a side.
When the selector switch SW is switched to the b side, a negative logic output is obtained.

The operation of the embodiment will be explained below. When writing the lighting phase control data to the main memory 4, by setting each fader at a predetermined position, the setting data of each fader ₁₀ to ₁₇ is sequentially written to A by the multiplexer 2 controlled by the write counter 11. /D converter 3, and this A/D
The lighting phase control data digitized by the converter 3 is written into the main memory 4 at addresses corresponding to the respective lighting loads 8 ₀ to 8 ₇ by the write signal F. Next, when the switch 5 switches from the main memory 4 to the buffer memory 6 due to the rise of the power synchronization signal, the write counter 11 operates at the same time, and the lighting phase control data stored in the main memory 4 is sequentially transferred to the buffer memory 6. Written to the corresponding bit of each register _L0 - _L7 . For example, when all outputs of the write counter 11 are at L level, the lighting phase control data "60" stored at address 0 of the main memory 4 is read out and the 60th bit of the 0th register _L0 of the buffer memory 6 is read out. At this time, the power synchronization signal applied to the data input terminals of registers L ₀ to L ₇ is at H level, so _the 1st
is written, and the lighting phase control data stored in addresses 1 to 7 of the main memory 4 are similarly written to the corresponding registers _L1 to _L7 , respectively. Next, when the power synchronization signal becomes L level, the switch 5 switches from the read counter 12 to the buffer memory 6, and the read counter 12 operates, and each bit of the buffer memory 6 is sequentially addressed by the output of the read counter 12. The lighting phase control data is read out and the width increasing transistor Q ₀ ~
Pulse transformer P ₀ ~ inserted in the collector of Q ₇
The ignition phase of each of the lighting load switching elements T ₀ to _{T 7} consisting of triacs is controlled via P ₇ . In the readout circuit of the buffer memory 6, the lower 3 bits of the 9-bit output of the readout counter 12 are transferred to the buffer memory 6.
The high-order 6 bits are the bit addresses of each register _L0 to _L7 , and the read counter 12 is used for the period Y during which the power synchronization signal is at L level.
It is designed to count 512 (64 x 8) clock signals per day. Therefore, the changeover switch
Read counter 1 when SW is switched to side a
Since a positive logic output is obtained from 2, for example, if 1 is stored in the 60th bit of register _L0 at address 0 of buffer memory 6, as shown in FIG.
When the 60th bit of the address register _L0 is addressed, that is, when the counter circuit 12a counts 473 clock signals [(59×8+1)], the output of the 0th register _L0 becomes 1 and the 0th register The ignition pulse PT is applied to the switching element T ₀ of the lighting load ₈₀ corresponding to L ₀ and the lighting load ₈₀ is turned on. On the other hand, when the changeover switch SW is switched to the b side, the read counter 1
Since a negative logic output is obtained from 0, the reading order of each bit in the buffer memory 6 is reversed, and the
The time when the 60th register _L0 is addressed is when the counter circuit 12a has counted 32 (4×8) clock signals, and at this time the lighting load _L0 is turned on by the ignition pulse PT'. do.
Therefore, the lighting phase of the lighting load ₈₀ changes significantly compared to when the output of the read counter 12 is a positive logic output, and the lighting intensity is reversed. In addition, when the width of the lighting phase control section is equal and the lighting load is lit with an AC power source as in the example, inversion in the strict sense [Z%→(100−Z)
%] operation is not performed, but a change in illumination intensity comparable to an inversion operation can be obtained. Further, in the light control device in which the lighting phase of the lighting loads ₈₀ to ₈₇ is controlled by the lighting phase control data stored in the main memory 4 and the lighting phase control data read out from the buffer memory 6 in this way, the buffer memory Since the lighting phase control data written in 6 needs to be cleared every half cycle of the AC power supply, in the present invention, the above-mentioned control circuit 10 clears each register L ₀ to
The write signal E of the buffer memory 6 is generated by the address signals B, C, D of _L7 and the output A of the oscillation circuit PG.
The buffer memory 6 is cleared by this write signal E. That is, when the write signal E is applied to each register _L0 to _L7 , each register _L0 to _L7
Since the power synchronization signal applied to the data input terminal of is at L level, 1 of each register L ₀ to _{L 7}
Immediately after reading one bit, 0 is written to that bit to clear it.

As described above, the present invention writes the lighting control data stored in the main memory into the corresponding bit of the buffer memory during the H level period of the power synchronization signal which becomes H level near the zero-crossing point of the AC power supply, and writes the lighting control data stored in the main memory into the corresponding bit of the buffer memory. In a dimming device that controls a lighting load by reading lighting phase control data from a buffer memory during a period, it is possible to change the order of reading from the buffer memory by providing an output switching circuit that switches the output of a read counter to a positive logic output or a negative logic output. It is reversible, and by appropriately selecting the output of the read counter as positive logic or negative logic, the lighting load can be lit in two different phases using the same lighting phase control data stored in the buffer memory. Because of its structure, the lighting intensity of the lighting load can be changed over a wide range with a simple circuit configuration without increasing the storage capacity of the main memory, and it has the advantage of realizing a wide range of production effects. It is.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIGS. 2 to 5 are circuit diagrams of the same main parts, and FIG.
8 to 8 are explanatory views of the same operation as above. 4 is main memory, 6 is buffer memory, 8 ₀
~8 ₇ is the lighting load, 12 is the read counter, 12b
is an output switching circuit, and _L0 to _L7 are registers.

Claims (1)

[Claims] 1. Divide the L level period of the power synchronization signal which becomes H level near the zero-crossing point of the AC power source into n lighting phase control sections, and provide a buffer memory in which a plurality of n-bit registers corresponding to the control sections are arranged in parallel. Writing the lighting phase control data of a plurality of lighting loads stored in the main memory into the corresponding bits of the buffer memory during the H level period of the power synchronization signal, and reading each output of the read counter operating during the L level period of the power synchronization signal. In a light control device, each bit is connected to an address data terminal of a buffer memory, each bit of the buffer memory is sequentially read out, and when lighting phase control data is obtained, a switching element of a corresponding lighting load is ignited.
A light control device characterized in that the readout order of each bit of a buffer memory is made reversible by providing an output switching circuit that switches each output of a readout counter to a positive logic output or a negative logic output.