JPS6151464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a synchronization separation circuit for a television receiver.

As is well known, in television receivers, it is necessary to separate and extract horizontal and vertical synchronizing signals using a synchronization separation circuit through amplitude discrimination operations.

FIG. 1 shows the waveform of the composite synchronization signal input to the synchronization separation circuit near the vertical retrace period. In the figure, equivalent pulses and the like have been deleted for the sake of simplification of the figure.

FIG. 2 is a circuit diagram showing a conventional synchronous separation circuit. In the same figure, Q1 is a synchronous isolation transistor, R
1 and R2 are emitter resistors, _C1 is an emitter capacitor, R3 is a collector load resistor, R4 and C2 are resistors and capacitors that constitute an integrator for vertical synchronization signal integration, 1 is a horizontal deflection circuit; 2 is a vertical deflection circuit It is.

Now, the drawbacks of the synchronous separation circuit in the prior art will be described below using the waveform example shown in FIG. FIG. 3A shows the output waveform of the synchronous separation circuit (collector voltage waveform of transistor Q1). As you can see from the figure,
There were problems in that the trailing edge of the vertical synchronizing signal was missing and the pulse height of the horizontal synchronizing signal immediately following the vertical synchronizing signal was insufficient. For this reason, there is a drawback that the image at the top of the screen is curved in the horizontal direction on the playback screen. The above drawbacks were not noticeable when normal signals were being received, but they became noticeable when playing back stills from VCRs (video cassette recorders), which have recently become popular, or when the input synchronization signal is subject to compression distortion. was considered a problem.

The above disadvantage is that the charging period of the capacitor C1 differs depending on the horizontal synchronizing signal period and the vertical synchronizing signal period, so as shown in FIG. 3B, the charging voltage of the capacitor C1 increases during the vertical synchronizing signal period, and the emitter of the transistor Q1 This is because the waveform of the voltage at the connection point between the resistors R1 and R2 is lowered by the vertical synchronizing signal, and as a result, the slice level changes as shown by the dotted line in FIG.

Therefore, an easy way to improve this is to increase the value of the emitter capacitor C1 shown in FIG. 2. In this case, the steady-state operating performance is improved, but on the other hand, the responsiveness deteriorates in transient characteristics such as when the power is turned on or when switching reception channels, and the quality of the product is significantly degraded.

Therefore, the conventional technology has been forced to adopt a compromising design, which tends to expose its shortcomings when playing back VCR stills.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the prior art described above and provide a synchronization separation circuit that operates stably.

In order to achieve the above object, the present invention is characterized in that the retrace pulse from the vertical deflection circuit is fed back to the input side of the synchronous separation circuit to temporarily stop the operation of the synchronous separation circuit.

The present invention will be explained below with reference to FIGS. 4 and 5.

FIG. 4 is a circuit diagram showing an embodiment of the present invention.
The block indicated by 3 in the figure is the essential part of the invention, and its output is fed back to the input side (base side or emitter side) of the synchronous separation transistor Q1. In this embodiment, for convenience of polarity, it is returned to the base side.

A specific circuit layout example of the feedback circuit 3 includes a diode D11 and resistors R11 and R1 shown in the figure.
2. A network including capacitor C12 is used.

A parallel circuit consisting of a capacitor C12 and a resistor R12 is a bias generation circuit for extracting only the vertical retrace pulse, and a battery can be used instead. The resistor R11 is for selecting the magnitude of the pulsed current to be fed back. 1S2076 (silicon diode) is used as diode D11, and the values of resistors R11 and R12 are as follows:
12KΩ, 1MΩ, as the value of capacitor C12
If 0.033 μF is selected, a pulse current of about 4 mA can be supplied over a vertical retrace width of about 400 μS.

An example of operating waveforms in this case is shown in FIG. FIG. 5A shows the synchronous separation output waveform (collector voltage of transistor Q1). Figure 5b shows the capacitor
This is the charging voltage waveform of Ci. Further, FIG. 5c shows the waveform of the decoded synchronization signal input (base voltage of transistor Q1) corrected by the action of the feedback circuit 3.

In FIG. 5A, the duration of the vertical synchronization signal is reduced, but this is not a problem. This is because, just before the time marked t _p in the same figure,
This is because the subsequent vertical oscillators have already entered the retrace period.

In FIG. 5B, the output no-signal state continues for a period of about 400 μS, and during this period, the subsequent horizontal oscillator continues to oscillate freely. Even if its free oscillation frequency is slightly off, this will not reproduce the image. Since this is an event within the vertical retrace line, it does not pose any problem.

What should be noted in Figure 5B is that approximately 400μ
After the above-mentioned rest period of S, the correct horizontal synchronization signal output is fully available with its amplitude of 100%. This fact means that the drawbacks of the prior art shown in FIG. 3 can be overcome. That is, since the transistor Q1 is in the cut-off state for a while after the start of the vertical retrace period, the voltage of the capacitor C1 hardly changes as is clear from FIG. 5B.

According to the present invention, the performance of the synchronization separation circuit can be greatly improved, and a stable synchronization signal can always be obtained not only under good reception conditions but also under poor reception conditions, and therefore more stable. You can play back images.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing the waveform of a composite synchronization signal near the vertical retrace period, FIG. 2 is a conventional synchronization separation circuit, and FIGS. 3A and B are voltage waveform diagrams of its main parts.
FIG. 4 is a circuit diagram showing one embodiment of the present invention, and FIGS. 5A to 5C are voltage waveform diagrams of the main parts thereof. 3...Feedback circuit, D11...Diode, R1
1, R12...Resistor, C12...Capacitor.

Claims (1)

[Claims] 1. A synchronous separation transistor connected to a time constant circuit consisting of a capacitor and a resistor, and a vertical deflection circuit driven by a vertical synchronous signal obtained from a synchronous signal output from the synchronous separation transistor. and supply means for supplying a vertical retrace pulse output from the vertical deflection circuit to a synchronous separation transistor with a polarity that causes the synchronous separation transistor to be cut off. 2. The synchronous separation circuit according to claim 1, wherein the supply means comprises a parallel circuit comprising another capacitor and another resistor, and a diode connected in series with this parallel circuit.