JPS6152497B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit in a data processing device, and more particularly, to a synchronous polyphase clock control sequential logic circuit that can be suitably applied to a functional test of a synchronous polyphase clock control sequential circuit.

In order to efficiently perform a functional test of a synchronous sequential circuit, the internal state of the synchronous sequential circuit can be directly controlled and observed from an external terminal during a functional test.
A synchronous sequential circuit has been proposed in which all memory elements inside the circuit are configured so that they can be handled as shift registers.

In a synchronous sequential circuit designed in this way, the internal state of the circuit can be controlled and observed directly from an external terminal at any time, making it possible to transform the synchronous sequential circuit into a pseudo combinational circuit and handle it. This made it possible to greatly simplify functional testing.

Here, the conventional technology will be explained using figures.

FIG. 1 is a diagram showing a synchronous sequential circuit in a data processing device. This circuit consists of register 30
0, combinational circuits 100, 200, external input terminal group 20, clock terminal 30, external output terminal group 6
Consists of 0. During normal operation, each memory element constituting register 300 receives clock signal 3.
000, receives signals from the signal line group 6001, drives the circuit using the signal line group 6003, and operates as a sequential circuit. During a functional test, by controlling the external input terminal group 20, each memory element constituting the register 300 is controlled by the clock signal 3000, and functions as a shift register in which the signal line 1000 is used as a shift-in signal and the signal line 7000 is used as a shift-out signal. It is also configured to work.

That is, during a functional test, test data and control data are applied to the external input terminal group 20, the test data is shifted into the register 300 from the external input terminal 10 under the control of the clock terminal 30, and the combinational circuits 100 and 200 are driven in normal operation. After that, by observing the output value at the external output terminal group 60 and the output value of the register 300 obtained by shifting out the data value of the register 300 from the external output terminal 70 under the control of the clock terminal 30, We were able to convert a synchronous sequential circuit into a pseudo combinational circuit and perform a functional test.

However, the synchronous sequential circuits generally used in data processing devices are not limited to single-phase clock control; polyphase clock control circuits may be used.

Generally, in the case of a multiphase clock control circuit, the operation of the circuit depends on the order in which the clock signals are controlled, and it is not possible to simply configure the registers inside the circuit as shift registers for functional testing. There was a problem that it was not possible to conduct the test.

The object of the present invention is to eliminate the above-mentioned drawbacks by making it possible to control all registers inside the circuit with a single clock signal in a synchronous multiphase clock control sequential circuit used in a data processing device.
An object of the present invention is to provide a synchronous multiphase clock controlled sequential logic circuit that can be tested as a pseudo combinational circuit during a functional test.

In order to achieve the above object, a logic circuit according to the present invention connects a group of registers controlled by a plurality of independent clock signals in a synchronous multiphase clock control sequential circuit so that they can be treated as one serial shift register. an external input terminal and an external output terminal capable of shifting data in and out of the serially connected shift registers, and means for controlling all register groups with a clock signal of the same phase. It is configured.

According to the above configuration, the object of the present invention can be completely achieved.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 shows a first embodiment of the circuit according to the invention. The illustrated synchronous two-phase clock control sequential circuit according to the present invention includes an external input terminal group 20, internal register groups 300 and 400, and a combinational circuit 1.
00, 200, an external output terminal group 60, external clock input terminals 30, 40, an external test clock input terminal 50, an external shift input terminal 10, and an external shift output terminal 70. In this synchronous two-phase clock control sequential circuit, internal registers 300, 400 use external clock input terminals 30, 40 as two-phase clocks, control signal lines 3000, 4000 as two-phase clock signals, and signal line groups 6001, 400 as two-phase clock signals during normal operation. 6002 operates as a data signal line group. During a functional test, by controlling the external input terminal group 20, the external shift input terminal 10 is used as a shift input terminal, and for the register 300, the signal line 1000 is used as a shift input signal, the signal line 2000 is used as a shift output signal, and the register 400 is
For the registers 300 and 400, the signal line 2000 is used as a shift input signal, the signal line 7000 is used as a shift output signal, the external shift output terminal 70 is used as a shift output terminal, and a clock is applied to the test external clock input terminal 50. Operates as a single serial shift register.

That is, when testing the functionality of this circuit, arbitrary test data is applied to the external input terminal group 20, the external input terminal group 20 is further controlled, and a clock signal is applied to the test external clock input terminal 50, thereby generating an external shift signal. Register 30 from input terminal 10
Any test data within 0,400 can be applied. The output values of the combinational circuits 100 and 200 driven by the above test data are determined by the external output terminal group 60 and the signal line groups 6001 and 6002.
The signal values output to the external output terminal group 60 can be directly observed, but the signal values output to the signal line group 6001,
The signal value on 6002 cannot be directly observed. Therefore, by controlling the external input terminal group 20, a clock is applied to the test external clock input terminal.
By simultaneously capturing the signal values on the signal line groups 6001 and 6002 into the registers 300 and 400, and then serially shifting out the contents of the registers via the external shift output terminal 70, the signal values on the signal line groups 6001 and 6002 are The signal value becomes observable. In other words, a test external clock terminal 50 and a clock signal line 5 that control all internal registers simultaneously in a synchronous two-phase clock control sequential circuit are provided.
By adding 000, it becomes possible to test this circuit as a pseudo combinational circuit. Note that in the above operation, the internal register 30
0,400 operates as a shift register, it is of course also possible to use the external clock input terminals 30, 40 as shift clock signals. Further, a case where the number of clock phases is three or more can be realized with a similar configuration.

Next, a second embodiment of the present invention will be described using FIG. 3. 3A is exactly the same as FIG. 2 except for the external clock input terminals 30, 40, the test control terminal 80, and the control circuit 500, so only the operations of the different parts will be described.

In FIG. 3A, external clock input terminal 30,
40 is a two-phase clock, and a test control terminal 80 is used as a switching signal for operating the internal registers 300, 400 as normal registers or as shift registers.

By controlling the test control terminal 80, the control circuit 500 drives the output signals 3000 and 4000 as two-phase clock signals or as in-phase clock signals. Such a control circuit can be easily realized using known logic elements. One embodiment is shown in FIG. 3B. That is, when the test control signal 8001 is at a high level (logic "1"), the output signal 3000 is a one-phase clock signal, the output signal 4000 is a two-phase clock signal, and the control signal 8001 is at a low level (logic "0"). ”), a one-phase clock signal is supplied to both output signals 3000 and 4000.

The configuration described above allows all registers in the circuit to operate with the same phase clock during normal operation of this circuit, making it possible to test this circuit as a pseudo combinational circuit during functional testing. Become. The same applies when this circuit has three or more phases. Furthermore, the control circuit does not need to be mounted inside the circuit, and can of course be mounted outside the circuit.

As explained above, the present invention is achieved by configuring all internal registers of a synchronous multiphase clock control sequential circuit to operate with the same phase clock.
This has the advantage that it can be tested as a pseudo combinational circuit during a functional test.

[Brief explanation of the drawing]

Figure 1 is a logical block diagram showing the conventional technology;
The figure is a logic block diagram showing one embodiment of the present invention, and FIG. 3 is a logic block diagram showing another embodiment of the invention. FIG. 3 is a circuit diagram of the control circuit used in FIG. A; 10...External shift input terminal, 20...External input terminal group, 30, 40...External clock input terminal, 50
...External clock input terminal for testing, 60... External output terminal group, 70... External shift output terminal, 80... Control terminal for testing, 100, 200... Combination circuit,
300, 400...internal register, 500...control circuit, 600,700...AND gate, 800...OR
Gate, 1000, 2000, 7000...Shift path signal, 3000, 3001, 4000, 40
01...Clock signal, 5000...Test clock signal, 6001, 6002, 6003, 6004
...Internal signal line group, 8001...Test control signal.

Claims (1)

[Claims] 1. Control means connectable so that a group of registers controlled by a plurality of independent clock signals can be treated as one serial shift register, and shifting data in and out of the serially connected registers. 1. A synchronous polyphase clock control sequential logic circuit comprising an external input terminal and an external output terminal capable of controlling the clock signal, and means capable of controlling all register groups by a clock signal of the same phase.