JPS6152503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control method for a data processing device.

Conventionally, when monitoring a data processing device, one way to measure the usage frequency of each instruction, the cumulative execution time within a certain period of time, the number of executions of a specific routine, the execution time, etc. is to monitor during the program. There is now a way to insert a program for . However, this method has the disadvantage that the monitoring program affects the system, making accurate measurement difficult. There is also a method of extracting various signals from the data processing system and measuring them using a measuring device independent of the data processing system. However, although accurate measurements are possible with this method, it is difficult to monitor the complex movements of the system because it is difficult to set various conditions.

The present invention has been made to solve this drawback, and by simply writing the monitor conditions and the monitor operation at that time into the memory corresponding to each instruction, the characteristics of the monitored program can be determined by the execution of the program. The purpose of the present invention is to provide a microprogram control method that allows accurate measurement without affecting the system in any way.

That is, the present invention provides a microprogram control method for a data processing device that includes a plurality of monitor circuits for monitoring the usage status of each microinstruction, and an instruction code corresponding to the microprogram address and monitor condition for each instruction. Each of the monitor circuits includes a monitor register for counting time, number of times, etc., and a mode register for specifying an operation mode of the register corresponding to the monitor register, The corresponding memory includes a map memory for storing a start address of a microprogram corresponding to each microinstruction, and a read/write monitor control memory corresponding to each word of the map memory,
The conditions for executing an instruction are set in the monitor control memory above, and when the instruction is executed, the time used to access the microprogram is read out and the conditions are compared, and the monitor register is updated in parallel with the execution of the instruction. A microprogram control method characterized by being configured to.

Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing an outline of an embodiment of the microprogram control system of the present invention. In the figure, the microprogram control system of the present invention includes an instruction code corresponding memory 1, a main memory 2, an arithmetic control circuit 3, a control circuit 4, a microprogram memory 5, and a monitor circuit 6. The instruction code corresponding memory 1 is provided with a map memory (microprogram memory) 1-1 and a monitor control memory 1-2, and the monitor circuit 6 is provided with a monitor register 6-1 and a mode register. 6-2 is provided.

The arithmetic control circuit 3 reads a macro instruction from the main memory 2, finds the address of the microprogram memory 5 corresponding to the instruction code using the map memory (MAP) 1-1, and executes the corresponding microprogram. This is the same as the conventional microprogram control method. In the present invention,
Furthermore, a monitor control memory (MCM) 1-2 that can be read and written corresponding to each word of the map memory 1-1 is provided.
has been established. In this memory 1-2, various monitoring conditions at the time of execution of each macro instruction are set by a dedicated write instruction.

When each macro instruction is executed, the map memory 1-1 is accessed by the arithmetic control circuit 3 in order to obtain the microprogram address.
At the same time, the monitor control memory 1-2 is also accessed, and the control circuit 4 makes a condition determination. The condition determination, for example, determines whether the value of the operand matches the value set in the monitor control memory 1-2.

If the determination is successful, the mode register 6-2 is set according to the operation recorded in the monitor control memory 1-2. In the monitor circuit 6, the monitor register 6-1 is updated according to the mode determined by the value of the mode register 6-2 in parallel with the normal instruction execution performed by the arithmetic control circuit 3.
Counts the number of executions of a specific command, the time from one condition to another, etc.

As described above, by programming monitor conditions such as the number of command executions and execution time in the monitor control memory 1-2, subsequent data collection can be performed with very little overhead for setting.
This can be done without affecting the actual program.

Next, the above embodiment will be explained in more detail.

FIG. 2 shows a part of the arithmetic control circuit 3 and the monitor control memory 1-2. The circuit 3 includes an accumulator (ACC1) 3-2, (ACC2) 3-3, an arithmetic and logic unit (ALU1) 3-4, and an instruction register (IR) 3-5. And bus 3
-15 to 3-17 connect these. In addition,
The program counter and map memory control circuit necessary for executing macro instructions are not shown here.

Data flow is performed by a microprogram. The data width of each bus 3-15 to 3-17 is 32 bits, and the data width of each bus 3-15 to 3-17 is 32 bits.
Since one word is 42 bits, it is written to monitor control memory 1-2 using two microinstruction cycles. The macro instruction for writing is in the format shown in Figure 3, 7-1, and writes the values of accumulators 3-2 and 3-3 shown in Figure 2 to the monitor control memory specified by the second word of the instruction code. Write in 1-2.

At this time, the microprogram that executes this macro instruction first opens the bus gate 3-2b by setting the bus gate signal 3-2a to "1", and transfers the data of the accumulator 3-2 to the bus 3-2.
Output to 17. Next, the data is transferred to branch bus 3-1.
7a, a write signal 1-2f is given to the monitor control memory 1-2. At this time, the address of the monitor control memory 1-2 is the address of the instruction register 3.
-5 is set by giving the target code.

Also, when executing a macro instruction, instruction register 3--
One of the instruction codes that entered 5 is signal line 3-6.
A is reached via the map memory 1-1 (see FIG. 1) which determines the starting address of the microprogram. The other one is monitor control memory 1-
2, the contents of memory 1-2 are read into latch registers 1-3. Latch signal 1-3a
is given when the read data from the monitor control memory 1-2 is finalized.

FIG. 4 is a block diagram showing an example of the monitor control memory 1-2 and the control circuit 4. As shown in FIG.

As shown in the figure, the monitor control memory 1-2 includes check bits (CHK) 1-2a, condition selection fields (COND) 1-2b, order fields (ORD) 1-2c when conditions are met, and data valid display. It consists of bits (V) 1-2d and operand comparison values (OC) 1-2e.

Check bit 1-2a is 1 bit and indicates whether checking of monitor control memory 1-2 is valid or invalid. If bits 1-2a are "0", the corresponding macro instruction is simply executed. or,
If it is "1", a monitor operation is performed in parallel with the instruction execution according to the contents of each field 1-2b to 1-2e. Condition selection field 1-2b is
4 bits indicate the condition. The condition compares the value of the mode register 6-2 shown in FIG. 5 with the specified number with the specified value. Data validity display bit 1-2d is 1 bit and indicates whether or not operand comparison value 1-2e is valid. When this bit is “1”, the operand comparison value 1-2e
is compared with the instruction's operand, and if they match, the condition is met.

Next, the control circuit 4 controls the multiplexer 4-
1. Match circuit 4-2, 4-4, operand switch register 4-3, AND gate 4-5, 4-6,
4-8, an OR gate 4-7, and a register number decoder 4-9.

The multiplexer 4-1 selects the condition selection field 1- from the plurality of mode registers 6-2.
The register specified by the condition represented by 2b is selected. The matching circuit 4-2 checks whether this matches the condition indicated in the field 1-2b. Further, if the data validity display bit 1-2d is "1", the matching circuit 4-4 checks whether the operand value and the operand comparison value 1-2e match. Operatuchi register 4-3
The value of the operand is set when the value of the operand is determined.

In the above AND gate 4-5, the matching circuit 4-4
The output of the data valid indicator bits 1-2d and the operand valid signal 4-5a are logically ANDed. Further, the AND gate 4-6 outputs the output of the matching circuit 4-2 and the data valid display bit 1-
The output of 2d is ANDed with the inverted signal. When the data valid display bits 1-2d are "1", the output of the AND gates 4-5 is output, and when the bits 1-2d are "0", the output of the AND gates 4-6 is output as an OR gate. It is input to AND gate 4-8 through 4-7.

The AND gate 4-8 performs a logical product of the output of the check bit 1-2a, the output of the OR gate 4-7, and the stop timing 4-8a. When the above check condition is satisfied and the strobe timing 4-8a is input, the condition fulfillment signal 4-8b is output from the AND gate 4-8.
becomes "1", and the operation of the register number decoder 4-9 becomes valid. This register number decoder 4
The number designation of the mode register in the order field 1-2c when the condition is satisfied is input to the input -9. The register number decoder 4-9 converts this number so that when the enable signal 4-9a is "1", one of the output lines 4-9 ₁ to 4-9n corresponding to the number becomes "1". Depending on this signal, one of the plurality of monitor circuits 6 ₁ to 6n is selected.

FIG. 5 is a block diagram showing one of the plurality of monitor circuits 6 ₁ -6n. The monitor circuit shown in the figure is composed of a monitor register (MNR) 6-1, a mode register (MR) 6-2, mode decode gates 6-3 to 6-8, and a data selector 6-9.

The mode register 6-2 becomes writable by the register enable signal 6-10d sent from the register number decoder 4-9.
Writing is performed when a write signal is applied to the load signal input 6-10c. Write data is sent from berth 3-17 shown in FIG. 2 via data input 6-1e and branch path 6-9b. A writing command word is prepared so that it can be set by a program, and its format is shown in FIG. 3, 7-3. Also, Figure 7-4 shows the contents of the accumulator 3-2 which is the input at that time, with the upper 3 bits containing the value of the mode register (MR) 6-2, and the lower 29 bits containing the value of the monitor register (MNR) 6-2. Set the value to 1.

The monitor register 6-1 is incremented by 1 each time a pulse arrives at the counter +1 mode input 6-1b, and is incremented by -1 each time a pulse arrives at the counter 1 mode input 6-1c. Also, data load signal input 6
When a signal comes to -1a, the register 6-1 has the following information:
The data of data input 6-1e is loaded.

Mode register 6-2 is monitor register 6-2.
1, and when the time count/condition fulfillment number designation output 6-2a in the upper 1 bit of the mode register 6-2 is "1", the monitor register 6-1 becomes the time mode, The time is measured by counting regularly spaced pulses input to the time counting clock input 6-10a in parallel with instruction execution. Further, when the output 6-2a is "0", the monitor register 6-1 becomes the counter mode, and the condition fulfillment signal 4 inputted to the condition fulfillment signal input 6-10b.
-8b (see Figure 4) match signals are counted in parallel with instruction execution. +1/ of mode register 6-2
The -1 designation output 6-2b specifies whether the monitor register 6-1 is used in subtraction mode or addition mode, depending on this bit. Also, the 0 detection latch output 6-2c is set to “0” when the monitor register 6-1 is set to “0”.
This bit becomes "1" when the register 6-1 becomes "0". These three signals become the condition signal 6-2d and are input to the multiplexer 4-1 shown in FIG. 4.

The data selector 6-9 transfers the data input of the mode register 6-2 to the path 3-- shown in FIG.
17 or based on the data in the monitor control memory 1-2 shown in FIG.

7-5 shown in FIG. 3 is the monitor register 6-1.
This is an instruction for reading the data of the monitor register 6-1, and when this instruction is executed after setting the register number in the accumulator 3-3, the data of the monitor register 6-1 is set in the accumulator 3-2. At this time, the monitor register 6-1 is enabled by the monitor register enable signal 6-1f, and the data output 6-1g is output to the path 3-15 shown in FIG. 2 and read into the accumulator 3-2.

In the above embodiment, the operand comparison value and the mode register are used as conditions, but other conditions within the data processing device may also be used.

Next, an example of actual use of the present invention will be described.

FIG. 6 8-1 shows the states of the map memory (MAP) and monitor control memory (MCM). Here, in 8-1a, the CHK bit is set for the INPUT instruction, the condition COND is unconditional, and the operand comparison value OC is set to 20. Furthermore, when a match occurs, the number 3 of the MNR is incremented by +1. This means counting the number of occurrences of the instruction INPUT20.

Also, when 8-1b receives a subroutine call instruction to address 100 called CALL1000, MNR
Set No. 1 to time counting mode, and set No. 1 of 8-1c to time counting mode.
Counting of MNR1 is stopped by the RETURN command. This calculates the execution time of the subroutine starting from address 1000.

Further, 8-1d and 8-1e are set so that MNR3 measures the processing time of the interrupt routine when MNR2 is in operation.

With this configuration, as shown in the time chart of FIG. 7, the time and number of executions of each independent event are measured. Note that although an interrupt does not have an instruction code, an instruction code is generated in a pseudo manner by the interrupt, and the map memory and monitor control memory are activated.

As explained above, the present invention sets the conditions for executing an instruction in the read/write monitor control memory provided for each instruction, and sets the conditions for executing the instruction.
By using the time to access the microprogram, reading it, comparing the conditions, and updating the monitor registers in parallel with instruction execution, there is no software overhead like in the past.
Furthermore, there is no lack of flexibility when using a hardware monitor, and the system usage status can be accurately monitored.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of one embodiment of the present invention, FIG. 2 is a block diagram showing a part of the arithmetic control circuit and monitor control memory used in the above embodiment, and FIG. 3 is a block diagram showing the outline of an embodiment of the present invention. 4 is a block diagram showing an example of the monitor control memory and control circuit, FIG. 5 is a block diagram showing details of one of the multiple monitor circuits, and FIG. 6 is the map memory. FIG. 7 is an explanatory diagram showing an example of the operating state of the monitor control memory, and FIG. 7 is a time chart of the above operation. 1... Instruction code corresponding memory, 1-1... Map memory, 1-2... Monitor control memory, 2...
Main memory, 3... Arithmetic control circuit, 3-2, 3-3...
...Accumulator, 3-5...Instruction register, 4
...Control circuit, 4-1...Multiplexer, 4-
2, 4-4... Matching circuit, 4-9... Register number decoder, 5... Micro program memory,
6...Monitor circuit, 6-1...Monitor register,
6-2...Mode register, 6-9...Data selector.

Claims (1)

[Claims] 1. In a microprogram control system in a data processing device, a plurality of monitor circuits for monitoring the usage status of each macro instruction, and an instruction code that stores the microprogram address and monitor conditions corresponding to each instruction. The monitor circuit includes a monitor register that counts time, number of times, etc., and a mode register that specifies an operation mode of the register in correspondence with the monitor register, and The code corresponding memory includes a map memory that stores the start address of the microprogram corresponding to each microinstruction;
It has a read/write monitor control memory that corresponds to each word in the map memory, and the conditions for executing an instruction are set in the monitor control memory, and when the instruction is executed, the microprogram is accessed. The microprogram control system is characterized in that the monitor register is updated in parallel with instruction execution by reading and comparing conditions using the time required to read the monitor register.