JPS6152566B2 - - Google Patents
Info
- Publication number
- JPS6152566B2 JPS6152566B2 JP54170022A JP17002279A JPS6152566B2 JP S6152566 B2 JPS6152566 B2 JP S6152566B2 JP 54170022 A JP54170022 A JP 54170022A JP 17002279 A JP17002279 A JP 17002279A JP S6152566 B2 JPS6152566 B2 JP S6152566B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist film
- substrate
- insulating film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
- H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に電
極窓と電極・配線とを自己整合(セルフアライ
ン)させて形成し得る半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an electrode window and an electrode/wiring can be formed by self-aligning.
半導体装置がICからLSI、超LSIと大規模化す
るにつれて集積度を高めるためLSI等の構成要素
であるトランジスタ等の素子の面積を極力小さく
することが重要な課題となつている。 As the scale of semiconductor devices increases from ICs to LSIs and VLSIs, it has become an important issue to minimize the area of elements such as transistors, which are components of LSIs, in order to increase the degree of integration.
位置合せのための余裕を必要としない自己整合
によりパターンを形成する方法は素子面積を小さ
くする有効な方法である。本発明はかかる観点か
ら電極窓と電極・配線の形成工程を自己整合化し
ようとするものである。 A method of forming a pattern by self-alignment that does not require a margin for alignment is an effective method for reducing the device area. From this point of view, the present invention attempts to achieve self-alignment in the process of forming electrode windows and electrodes/wirings.
従来電極・配線を形成するに当り、先ず第1図
aに示すごとく半導体基板1内に形成されたベー
ス領域2、エミツタ領域3等の表面を被覆する絶
縁膜4にベース電極窓5、エミツタ電極窓6等を
開口し、次いで同図bに示すようにアルミニウム
(Al)等電極金属層を蒸着法等により被着せし
め、これをパターニングしてベース電極7、エミ
ツタ電極8等を形成していた。 Conventionally, when forming electrodes and wiring, first, as shown in FIG. The window 6, etc. were opened, and then, as shown in Figure b, an electrode metal layer such as aluminum (Al) was deposited by vapor deposition, etc., and this was patterned to form the base electrode 7, emitter electrode 8, etc. .
このような方法では電極窓5,6間隔Dは、2
つの電極7,8の間隔D1に位置合せ余裕D2を加
算した付法とせねばならない。例えば電極間隔
D1が2〔μm〕なる微細パターンを形成する場
合位置合せ余裕D2は3〔μm〕〜4〔μm〕必
要とするため電極窓間隔Dは5〔μm〕〜6〔μ
m〕としなければならず、その分だけ素子面積が
大きくなる。その結果半導体装置の高密度化を妨
げるのみならず、不要面積が増大することにより
素子の電気的特性に対しても悪影響がある。 In such a method, the distance D between the electrode windows 5 and 6 is 2
The distance D 1 between the two electrodes 7 and 8 must be added to the alignment margin D 2 . For example, electrode spacing
When forming a fine pattern in which D 1 is 2 [μm], the alignment margin D 2 is required to be 3 [μm] to 4 [μm], so the electrode window interval D is 5 [μm] to 6 [μm].
m], and the element area increases accordingly. As a result, this not only hinders the increase in the density of semiconductor devices, but also has an adverse effect on the electrical characteristics of the device due to an increase in unnecessary area.
本発明の目的は上述の位置合せ余裕を必要とし
ない電極・配線の形成方法を提供することにあ
る。 An object of the present invention is to provide a method for forming electrodes and wiring that does not require the above-mentioned alignment margin.
本発明の半導体装置の製造方法の特徴は、被処
理基板表面を被覆する絶縁膜上にネガ型ホトレジ
スト膜を形成し、前記ネガ型ホトレジスト膜上に
ポジ型ホトレジスト膜を選択的に形成し、前記被
処理基板を減圧下で弗化水素雰囲気中にさらすこ
とにより前記露出せる、ネガ型ホトレジスト膜直
下の絶縁膜を除去して該絶縁膜に開口を形成し、
前記露出せるネガ型ホトレジスト膜を除去して前
記絶縁膜の開口部を被処理基板表面を露呈せし
め、前記ポジ型ホトレジスト膜表面を含む被処理
基板表面に金属膜を被着し、前記ポジ型ホトレジ
スト膜及び残留せるネガ型ホトレジスト膜を除去
して、前記絶縁膜の開口部において被処理基板と
接触し且つ前記絶縁膜上に導出された電極及び/
又は配線を形成する工程とを含むことにある。 The method for manufacturing a semiconductor device of the present invention is characterized by forming a negative photoresist film on an insulating film covering a surface of a substrate to be processed, selectively forming a positive photoresist film on the negative photoresist film, and forming a positive photoresist film on the negative photoresist film. forming an opening in the insulating film by removing the exposed insulating film directly under the negative photoresist film by exposing the substrate to be processed to a hydrogen fluoride atmosphere under reduced pressure;
removing the exposed negative photoresist film to expose the opening of the insulating film to the surface of the substrate to be processed; depositing a metal film on the surface of the substrate including the positive photoresist film; The film and the remaining negative photoresist film are removed, and the electrodes and/or electrodes are brought into contact with the substrate to be processed in the opening of the insulating film and are led out onto the insulating film.
or a step of forming wiring.
以下本発明の半導体装置の製造方法の実施例を
図面を用いて説明する。 Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.
第2図は本発明の実施例を工程の順に示す要部
断面図及び要部上面図である。 FIG. 2 is a sectional view and a top view of essential parts showing an embodiment of the present invention in the order of steps.
同図aにおいて、1はシリコン基板、2はベー
ス領域、3はエミツタ領域、4はシリコン基板表
面を被覆する二酸化シリコン(SiO2)膜、9はコ
レクタ領域、9′はコレクタ領域の埋込層、10
はコレクタ・コンタクト領域である。これに先ず
OMR83(東京応化工業社製)のようなポリイソ
プレン系ネガ型ホトレジストを約5000〔Å〕の厚
さに塗布し、所定のパターンに従つて選択的に残
留せしめ、ベース及びエミツタの電極窓を形成す
べき区域を被覆するネガ型ホトレジスト膜11及
びコレクタ電極窓を形成すべき区域を被覆するネ
ガ型ホトレジスト膜11″を形成する。このパタ
ーンを同図a′の上面図に示す。 In the figure a, 1 is a silicon substrate, 2 is a base region, 3 is an emitter region, 4 is a silicon dioxide (SiO 2 ) film covering the surface of the silicon substrate, 9 is a collector region, and 9' is a buried layer in the collector region. , 10
is the collector contact area. First of all
A polyisoprene-based negative photoresist such as OMR83 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to a thickness of approximately 5000 Å and left selectively in accordance with a predetermined pattern to form electrode windows for the base and emitter. A negative photoresist film 11 covering the area where the collector electrode window is to be formed and a negative photoresist film 11'' covering the area where the collector electrode window is to be formed are formed.This pattern is shown in the top view of a' in the same figure.
次いで同図b,b′に示すように、OFPR77(東
京応化工業社製)のようなノボラツク樹脂系ポジ
型ホトレジスト膜12を約2〔μm〕の厚さに選
択的に形成し、ベース、エミツタ及びコレクタの
電極及び配線を形成すべき部分に開口13,1
3′,13″を設ける。 Next, as shown in FIGS. b and b', a novolak resin-based positive photoresist film 12 such as OFPR77 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is selectively formed to a thickness of about 2 μm, and the base and emitter layers are Openings 13 and 1 are formed in the areas where collector electrodes and wiring are to be formed.
3', 13'' are provided.
次いで上記シリコン基板1を真空処理槽中に於
いて圧力約10〔Torr〕の弗化水素(HF)雰囲気
にさらし、凡そ120〔℃〕の温度で処理するいわ
ゆるドライ・オツクス(Dry ox)法を用いるこ
とにより、第2図cに示すように、前記ネガ型ホ
トレジスト膜11,11″の開口13,13′,1
3″部にあつて表面を露出せる部分直下のSiO2膜
が除去されて電極窓が形成される。 Next, the silicon substrate 1 is exposed to a hydrogen fluoride (HF) atmosphere at a pressure of about 10 [Torr] in a vacuum processing tank, and processed at a temperature of about 120 [°C] using the so-called dry ox method. As shown in FIG. 2c, openings 13, 13', 1
The SiO 2 film directly under the 3'' portion where the surface is exposed is removed to form an electrode window.
次いで該電極窓内に残留せるネガ型ホトレジス
ト膜11,11′,11″をプラズマアツシヤ法等
により除去する。この時ポジ型レジスト膜12は
ネガ型ホトレジスト膜11,11′,11″より遥
かに厚く形成されているので若干厚さを減じるの
みで、表面を露出せるネガ型ホトレジスト膜1
1,11′,11″のみが除去されて第2図d,
d′に示すごとく電極窓14,14′,14″部にお
いてシリコン基板表面が露呈する。 Next, the negative photoresist films 11, 11', 11'' remaining in the electrode windows are removed by plasma assembling. Since the negative photoresist film 1 is formed thickly, the surface can be exposed by only slightly reducing the thickness.
Only 1, 11', 11'' are removed and the figure 2d,
As shown in d', the surface of the silicon substrate is exposed at the electrode windows 14, 14', 14''.
既に明らかなように電極窓14,14′,1
4″をポジ型ホトレジスト12の開口13内にあ
り且つネガ型レジスト11,11′で被覆されて
いた部分であつて、この部分ではSiO2膜2が除
去され、シリコン基板1表面が露出する。また前
記開口13,13′,13″内にあり且つネガ型レ
ジスト膜が存在しない部分はSiO2膜4は除去さ
れず表面を露出して残留している。 As already clear, the electrode windows 14, 14', 1
4'' is a portion located within the opening 13 of the positive type photoresist 12 and covered with the negative type resists 11 and 11', where the SiO 2 film 2 is removed and the surface of the silicon substrate 1 is exposed. Further, in the portions which are within the openings 13, 13', 13'' and where no negative resist film is present, the SiO 2 film 4 is not removed and remains with the surface exposed.
このようにしたあとアルミニウム(Al)等を
蒸着法などを用いて前記シリコン基板1表面全面
に被着し、次いでホトレジスト剥離液に浸漬する
等の方法により前記ポジ型ホトレジスト膜12及
び残留せるネガ型ホトレジスト膜を除去して、前
記ポジ型ホトレジスト膜12上に被着せるアルミ
ニウム層を同時に除去する所謂リフトオフ法を用
いることにより第2図e,e′に示すようにベー
ス、エミツタ及びコレクタの電極・配線15,1
5′,15″を形成する。 After this, aluminum (Al) or the like is deposited on the entire surface of the silicon substrate 1 using a vapor deposition method or the like, and then the positive type photoresist film 12 and the remaining negative type are coated by a method such as immersion in a photoresist stripping solution. By using a so-called lift-off method in which the photoresist film is removed and the aluminum layer deposited on the positive photoresist film 12 is removed at the same time, the base, emitter, and collector electrodes and wiring are removed as shown in FIG. 2e and e'. 15,1
5', 15'' are formed.
該電極・配線15,15′,15″は電極窓1
4,14′,14″部においてシリコン基板1表面
にオーミツク接触をなし、且つSiO2膜4上に導
出されて配線が形成される。 The electrodes/wirings 15, 15', 15'' are electrode windows 1
4, 14', and 14'' portions make ohmic contact with the surface of the silicon substrate 1, and are led out onto the SiO 2 film 4 to form wiring.
本実施例では電極窓の形成に用いたホトレジス
ト膜パターンをそのまま用いて電極・配線を形成
するので、両者の相互位置関係は完全に自己整合
される。従つて位置合せ余裕D2が不要となり電
極窓間隔Dを電極間隔D1と等しくすることがで
き、素子面積を著しく小さくできる。 In this embodiment, the photoresist film pattern used to form the electrode window is used as it is to form the electrodes and wiring, so the mutual positional relationship between the two is completely self-aligned. Therefore, the alignment margin D 2 is not required, and the electrode window spacing D can be made equal to the electrode spacing D 1 , making it possible to significantly reduce the element area.
前記実施例では半導体基板表面に接触する電
極・配線を形成する方法につい説明したが、本発
明は更に多層配線を形成する場合にも用いること
ができる。 In the above embodiments, a method for forming electrodes and wiring in contact with the surface of a semiconductor substrate has been described, but the present invention can also be used for forming multilayer wiring.
即ち第3図の要部断面図に示すごとく、第1層
電極または配線16,16′上を被覆する絶縁膜
4に電極窓を開口し、該電極窓部において第1層
の電極または配線16,16′に接続し絶縁膜4
上に導出された第2層電極・配線17,17′を
形成する場合に本発明を実施し得る。このような
多層配線においては電極窓はスルーホールとな
る。なお第1層の電極・配線16,16′はバイ
ポーラ素子或いはMOS構造素子等の電極であつ
てもよく、或いは単に配線層であつてもよい。 That is, as shown in the cross-sectional view of the main part of FIG. , 16' and the insulating film 4
The present invention can be practiced when forming second layer electrodes/wirings 17, 17' led out above. In such multilayer wiring, the electrode window becomes a through hole. Note that the first layer electrodes/wirings 16, 16' may be electrodes of a bipolar element or a MOS structure element, or may simply be a wiring layer.
なお4′は被処理基板1表面を被覆する絶縁膜
である。 Note that 4' is an insulating film that covers the surface of the substrate 1 to be processed.
また前記実施例では被処理基板に半導体基板を
用いて説明したが、これは半導体基板に限定する
必要はなく、例えばハイブリツド回路基板等であ
つてもよい。 Further, in the above embodiments, a semiconductor substrate was used as the substrate to be processed, but this need not be limited to a semiconductor substrate; for example, a hybrid circuit board or the like may be used.
以上説明したごとく本発明の半導体装置の製造
方法によれば、電極・配線を電極窓と自己整合さ
せて形成することができるので位置合せ余裕が不
要となり、従つて素子面積を小さくできるので半
導体装置の集積度を高めることが可能となる。 As explained above, according to the method for manufacturing a semiconductor device of the present invention, electrodes and wiring can be formed in self-alignment with electrode windows, so alignment margins are not required, and the element area can be reduced, so that the semiconductor device It becomes possible to increase the degree of integration.
第1図は従来の電極・配線形成方法の説明に供
する要部断面図、第2図は本発明の実施例を工程
の順に示す要部断面図及び要部上面図、第3図は
本発明の変形例を示す要部断面図である。
1……被処理基板、2……ベース領域、3……
エミツタ領域、4……絶縁膜、10……コレク
タ・コンタクト領域、11,11′,11″……ネ
ガ型ホトレジスト膜、12……ポジ型ホトレジス
ト膜、13,13′,13″……ポジ型ホトレジス
ト膜の開口、14,14′,14″……電極窓、1
5,15′15″……電極・配線、16,16′…
…第1層電極・配線、17,17′……第2層電
極・配線。
FIG. 1 is a cross-sectional view of a main part to explain a conventional electrode/wiring forming method, FIG. 2 is a cross-sectional view and a top view of a main part showing an embodiment of the present invention in order of steps, and FIG. FIG. 3 is a cross-sectional view of a main part showing a modification example of FIG. 1...Substrate to be processed, 2...Base region, 3...
Emitter region, 4... Insulating film, 10... Collector contact area, 11, 11', 11''... Negative photoresist film, 12... Positive photoresist film, 13, 13', 13''... Positive type Opening of photoresist film, 14, 14', 14''...electrode window, 1
5,15'15''...electrode/wiring, 16,16'...
...First layer electrode/wiring, 17,17'...Second layer electrode/wiring.
Claims (1)
ホトレジスト膜を形成し、前記ネガ型ホトレジス
ト膜上にポジ型ホトレジスト膜を選択的に形成
し、前記被処理基板を減圧下で弗化水素雰囲気中
にさらすことにより前記露出せるネガ型ホトレジ
スト膜直下の絶縁膜を除去して該絶縁膜に開口を
形成し、前記露出せるネガ型ホトレジスト膜を除
去して前記絶縁膜の開口部の被処理基板表面を露
呈せしめ、前記ポジ型ホトレジスト膜表面を含む
被処理基板表面に導電膜を被着し、前記ポジ型ホ
トレジスト膜及び残留せるネガ型ホトレジスト膜
を除去して、前記絶縁膜の開口部において被処理
基板と接触し且つ前記絶縁膜上に導出された電極
及び/又は配線を形成する工程とを含むことを特
徴とする半導体装置の製造方法。1. A negative photoresist film is formed on an insulating film covering the surface of the substrate to be processed, a positive photoresist film is selectively formed on the negative photoresist film, and the substrate to be processed is placed in a hydrogen fluoride atmosphere under reduced pressure. The insulating film directly under the exposed negative photoresist film is removed by exposing the insulating film to form an opening in the insulating film, and the exposed negative photoresist film is removed to form a substrate to be processed in the opening of the insulating film. exposing the surface, depositing a conductive film on the surface of the substrate to be processed including the surface of the positive photoresist film, removing the positive photoresist film and the remaining negative photoresist film, and depositing the conductive film in the opening of the insulating film. A method for manufacturing a semiconductor device, comprising the step of forming an electrode and/or a wiring in contact with a processing substrate and led out on the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17002279A JPS5693316A (en) | 1979-12-26 | 1979-12-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17002279A JPS5693316A (en) | 1979-12-26 | 1979-12-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5693316A JPS5693316A (en) | 1981-07-28 |
| JPS6152566B2 true JPS6152566B2 (en) | 1986-11-13 |
Family
ID=15897141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17002279A Granted JPS5693316A (en) | 1979-12-26 | 1979-12-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5693316A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2279986T3 (en) * | 2004-01-13 | 2007-09-01 | Frape Behr S.A. | HOLDING DEVICE FOR AN EXPANSION VALVE OF AN AIR CONDITIONING INSTALLATION FOR A MOTOR VEHICLE. |
-
1979
- 1979-12-26 JP JP17002279A patent/JPS5693316A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5693316A (en) | 1981-07-28 |
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