JPS6152972B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device using an impurity doping method by ion implantation.

Recently, ion implantation has become widely used as a method for doping semiconductors with impurities and for manufacturing pn junctions. The ion implantation method is superior to the conventional diffusion method in terms of precision and uniformity of the amount of doped impurities, and the ability to dope the impurity from above the dielectric film to the semiconductor below this film. However, it also has drawbacks such as the occurrence of defects due to ion irradiation. For this purpose, high temperature annealing, high temperature deep drive-in re-diffusion in an oxidizing atmosphere, etc. have been used. Recently, shallow pn junctions have been desired from the viewpoint of increasing the frequency of bipolar devices and miniaturizing MOS devices. In such cases, heavy ions such as arsenic (As) or antimony (Sb) are used. However, As,
Since Sb is a heavy ion, its range and dispersion are small, but on the other hand, it also generates a large number of defects, and when annealing at 900 to 1100 degrees Celsius, this large amount of defects causes accelerated diffusion and has the effect of broadening the distribution. Ta.

On the other hand, from the viewpoint of semiconductor device fabrication, shallow pn junctions cause the following difficulties. Shallow doping with As or Sb near the surface of p-type silicon (Si) single crystal
For the electrode of the n ⁺ type layer, when aluminum (Al) is evaporated and sintered, the part of the n ⁺ type layer is
The Si dissolves, creating pit-like holes, and Al enters into these holes, penetrating into the p-type region and causing the pn junction to lose its rectifying properties. Difficulties on such devices and ion implantation into semiconductors
To avoid residual defects and deep re-diffusion of As and Sb,
The following methods have been devised. This method uses Si
Polycrystalline Si is deposited on a single crystal, and As is ion-implanted with an acceleration energy that distributes only within the polycrystal.
This is a method of diffusing it inside. In the method of diffusing As from As-doped polycrystalline Si to single-crystalline Si, the uniformity of the initial As concentration in polycrystalline Si is increased by ion implantation, and the problem of Al electrodes can be solved by increasing the thickness of polycrystalline Si. This can be solved by making it appropriately thick. However, high-temperature diffusion from within polycrystalline Si to single-crystalline Si is still required.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device in which a shallow junction with few defects can be formed and an electrode of an ion-implanted layer can be easily obtained.

That is, in this invention, polycrystalline Si is deposited on single-crystal Si, impurity ions are implanted so as to be distributed in both the polycrystalline silicon and the single-crystal, and the entire surface region of the silicon single crystal facing the polycrystalline silicon is implanted. This method of manufacturing a semiconductor device is characterized in that it is doped by 5 to 95% of the amount of doping, and then a first stage heat treatment is performed at 500 to 650°C.

Examples of the present invention will be described below.

First, a p-type Si single crystal that is in the (100) plane or tilted within 7° from this plane is used, and a SiO ₂ film of ~5000 Å is deposited on this single crystal by thermal oxidation or CVD. After this, a window is opened using a conventional photoetching method to expose the Si single crystal surface. Next, a polycrystalline Si layer of 1000 Å is deposited by thermal decomposition of SiH ₄ . A wafer with this structure
As ions are implanted at 200 KV at 3×10 ¹⁵ ions/cm ² .
This sample is heat treated in _N2 at 500°C for 80 minutes. This heat treatment recovers most of the defects caused by As ion implantation in the single crystal. That is, the amorphous layer turns into a single crystal, and at the same time, As recovers electrically.

This method was used to form the emitter of an npn transistor. That is, an n ⁺ type emitter part was formed in the base of a (100) epitaxial Si wafer with the base and collector junction located 4000 Å from the surface by the above method, and after the above heat treatment at 500°C for 80 minutes,
After heat treatment at 1000°C for 20 minutes in N ₂ , an Al electrode was deposited and sintered to form an npn transistor. Heat treatment at 1000℃ for 20 minutes removes As in the polycrystalline Si layer.
It is aimed at the activation of single-crystal Si and the recovery of residual defects in single-crystal Si. This emitter-based junction is 2000Å
The forward current-voltage characteristics are I~
It was expressed as exp(−qV/1.1×kT). Also, the noise figure of this transistor at 2GHz was 2dB. On the other hand, a similar polycrystalline Si layer was deposited on a similar epitaxial wafer, and the same ion implantation was performed.
When heat treatment was performed at ℃ for 20 minutes in N ₂ , the emitter-base junction was found to have a thickness of 2500 Å, and the base-collector junction was observed to have regressed to 4800 Å.
Its IV characteristic was I~qV/1.3×kT.
Also, the noise figure at 2G Hz increased to 2.5dB. In addition, 3×10 ¹⁵ ions/cm ² of As were ion-implanted into the polycrystalline Si layer at 30 kV, and then heat-treated at 1000°C for 50 minutes to transform the As into Si.
In the case of the one diffused into a single crystal, the collector-base junction retreated deep, and the high frequency cutoff frequency was reduced compared to the one of the present invention. Also, when using a (111) or (110) wafer, annealing at 550°C is performed for 2 hours after ion implantation, and for other (100) wafers.
Similar results were obtained using exactly the same process as for wafers.

In the example described above, the polycrystalline silicon layer is 1000
In the case of Å, arsenic ions are accelerated at 200 KV so that a portion of them is doped into single crystal silicon. However, without being limited to these, the amount of doping into single crystal silicon may be 5 to 95% of the amount of ion implantation.
%, a predetermined effect can be obtained. If the amount of ions implanted into single crystal silicon is less than 5%, excessive ions will be doped into polycrystalline silicon. Therefore, high temperature heat treatment is required to form a bond.
The impurity profile becomes difficult to control, making it impossible to create shallow junctions in single-crystal silicon. In addition, if the amount of implantation into single crystal silicon is more than 95% of the total amount, the number of ions doped into polycrystalline silicon will be extremely small, and the polycrystalline silicon will remain highly resistive, making it difficult to use it as an electrode. become unable.

Furthermore, in the above-mentioned embodiments, 500°C or 550°C was exemplified as the heat treatment temperature after ion implantation, but
The heat treatment temperature is not limited to this, but a predetermined effect can be obtained if the heat treatment temperature is 500 to 650°C. Here the heat treatment temperature is 500℃
If it is lower, the recovery of defects in the silicon single crystal will be insufficient. This causes accelerated diffusion during subsequent high-temperature annealing, resulting in a deeper bond. Furthermore, if the heat treatment temperature is higher than 650° C., impurities will diffuse deeply into the single crystal silicon, making it difficult to form shallow junctions.

In the above case, especially when the ion implantation amount is 5.
When the amount exceeds ×10 ¹⁵ ions/cm ² , high heat treatment is required to recover defects in single crystal silicon. In other words, the plane orientation of single crystal silicon is (100)
plane, or has an inclination within 7 degrees from the plane,
Approximately 550℃ is required as the heat treatment temperature, and if the plane orientation is (110) or (111) plane or has an inclination within 7 degrees from these planes, the heat treatment temperature is
It was confirmed that a temperature of about 650°C is required, and that at lower temperatures, defects in single-crystal syringe are not fully recovered.

In addition, in the present invention described above, the (100) plane,
The reason for using the (110) plane, the (111) plane, or a silicon single crystal plane within 7 degrees will be explained.
Crystal planes with the above plane indices have excellent crystallographic and electrical properties unique to them, but if the crystal plane is tilted from the above planes and exceeds an inclination of ±7 degrees, the crystal planes with the above plane indexes The properties of crystal planes become noticeable. Therefore, in the present invention, by using the above-mentioned (100) plane, (110) plane, or (111) plane, or a crystal plane having an inclination within ±7 degrees, the original excellent properties of each of these planes are utilized. It can be said that the method of the present invention described above provides a pn junction or an n ⁺ -n junction that has superior characteristics compared to conventional methods.

Claims (1)

[Claims] 1. A dielectric film is formed on a (100) plane, a (110) plane, a (111) plane, or a silicon single crystal plane having an inclination of 7 degrees or less from these planes, and this dielectric film is Selectively removing the film to expose the silicon single crystal, forming a polycrystalline silicon film at least on the exposed silicon single crystal surface, and implanting arsenic or antimony ions from above the polycrystalline silicon film, A method for manufacturing a semiconductor device, characterized in that the surface region of the silicon single crystal facing the polycrystalline silicon film is doped with 5 to 95% of the total amount of doping, and then heat treatment is performed at 500 to 650°C. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed for less than 2 hours. 3 Ion implantation dose is 5×10 ¹⁵ ions/cm ²
In the above, when the silicon single crystal has a (110) plane or an inclination within 7 degrees from the plane, the semiconductor device according to claim 1, characterized in that the heat treatment temperature is set to about 550°C. manufacturing method. 4 Ion implantation dose is 5×10 ¹⁵ ions/cm ²
Claim 1, characterized in that when the silicon single crystal has a (110) or (111) plane or an inclination within 7 degrees from these planes, the heat treatment temperature is set at about 650°C. A method for manufacturing a semiconductor device according to .