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JPS6152977B2 - - Google Patents
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JPS6152977B2 - - Google Patents

Info

Publication number
JPS6152977B2
JPS6152977B2 JP56027381A JP2738181A JPS6152977B2 JP S6152977 B2 JPS6152977 B2 JP S6152977B2 JP 56027381 A JP56027381 A JP 56027381A JP 2738181 A JP2738181 A JP 2738181A JP S6152977 B2 JPS6152977 B2 JP S6152977B2
Authority
JP
Japan
Prior art keywords
film substrate
pattern
electrode lead
fixing
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56027381A
Other languages
Japanese (ja)
Other versions
JPS57141947A (en
Inventor
Yoshio Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP56027381A priority Critical patent/JPS57141947A/en
Publication of JPS57141947A publication Critical patent/JPS57141947A/en
Publication of JPS6152977B2 publication Critical patent/JPS6152977B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/453Leadframes comprising flexible metallic tapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

従来の一般的な半導体装置の量産方法は金属薄
板のパンチングフレームを用いていた。しかしな
がら斯るフレームでは高々14連程度で区切られる
ため、連続してフレームを供給して行くことは不
可能であつた。この欠点を改善するために第1図
の如く、ポリイミド、ポリアミドイミド等の耐熱
性プラスチツク層1上に銅箔2を貼つたフレキシ
ブルフイルム基板3が提案された。しかしこのフ
レキシブルフイルム基板3は耐熱性プラスチツク
層1が極めて高価であり、半導体装置の量産方法
としては不適当であつた。
The conventional general mass production method for semiconductor devices has used a punching frame made of a thin metal plate. However, since such frames are divided into about 14 consecutive frames at most, it has been impossible to supply frames continuously. In order to improve this drawback, a flexible film substrate 3 has been proposed, as shown in FIG. 1, in which a copper foil 2 is pasted on a heat-resistant plastic layer 1 made of polyimide, polyamideimide, or the like. However, the heat-resistant plastic layer 1 of this flexible film substrate 3 is extremely expensive, and is therefore unsuitable for mass production of semiconductor devices.

本発明は斯点に鑑みてなされ、従来の欠点を除
去した半導体装置の製造方法を提供するものであ
る。以下に第2図乃至第8図を参照して本発明の
一実施例を詳述する。
The present invention has been made in view of this point, and provides a method for manufacturing a semiconductor device that eliminates the conventional drawbacks. An embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 8.

本発明の第1の工程は第2図および第3図に示
す如く、フレキシブルなフイルム基板10を形成
することにある。このフイルム基板10は二枚の
銅箔11,12を互いに熱硬化性樹脂の接着剤1
3で圧着して形成される。この二枚の銅箔11,
12はプリント基板等に用いられる約35μ厚の銅
箔を用い、一方あるいは両方の銅箔11,12の
一面にエポキシ樹脂等の熱硬化性樹脂から成る接
着剤13を塗布した後にローラーで圧着して二枚
の銅箔11,12を一体化してフイルム状にす
る。ここで用いられる熱硬化性樹脂としては例え
ば特公昭55−20394号公報に記載されたものを用
いれば良い。この様に二枚の銅箔は互いに約30μ
厚の薄い接着剤13で電気的に絶縁され、最低で
も600V、平均で約2500Vの絶縁耐圧が得られる。
The first step of the present invention is to form a flexible film substrate 10, as shown in FIGS. 2 and 3. This film substrate 10 is made by bonding two copper foils 11 and 12 together with a thermosetting resin adhesive 1.
It is formed by crimping with step 3. These two copper foils 11,
Reference numeral 12 uses a copper foil with a thickness of approximately 35μ, which is used for printed circuit boards, etc., and after applying an adhesive 13 made of a thermosetting resin such as epoxy resin to one surface of one or both of the copper foils 11 and 12, the adhesive 13 is pressed with a roller. The two copper foils 11 and 12 are integrated into a film. As the thermosetting resin used here, for example, those described in Japanese Patent Publication No. 55-20394 may be used. In this way, the two pieces of copper foil are approximately 30 μm apart from each other.
It is electrically insulated with a thin adhesive 13 and has a dielectric strength of at least 600V and on average about 2500V.

斯るフイルム基板10は所定の巾例えば50mm巾
に切断して帯状にして例えば長さ50m単位でカー
トリツジに巻き取り、製造に供する。この帯状の
フイルム基板10には第3図の如く所望の導電パ
ターンを設けない両端部分に一定間隔でインデツ
クス孔14を打抜いて形成し、以降の製造工程で
インデツクス孔14を用いて位置の割出しやフイ
ルム基板10の移送を行う。
The film substrate 10 is cut into strips having a predetermined width, for example, 50 mm, and is wound up into a cartridge in units of, for example, 50 m in length for manufacturing. As shown in FIG. 3, index holes 14 are punched out at regular intervals on both ends of the strip-shaped film substrate 10 where the desired conductive pattern is not provided, and the index holes 14 are used to assign positions in the subsequent manufacturing process. The film substrate 10 is unloaded and transferred.

本発明の第2工程は第4図に示す如く、フイル
ム基板10の一方の銅箔11をエツチングして所
望の導電パターン15を多数長さ方向に一定間隔
で連続して形成することにある。導電パターン1
5はフイルム基板10のほぼ中央部に設けた半導
体素子を載置する固着パツド16と固着パツド1
6の近傍から四方向に延在された複数本の電極リ
ード17より構成される。またこの電極リード1
7は各方向毎に平行に且つ一定間隔で配列されて
おり、最終的に外部端子として働く。
As shown in FIG. 4, the second step of the present invention consists in etching the copper foil 11 on one side of the film substrate 10 to form a large number of desired conductive patterns 15 successively at regular intervals in the length direction. Conductive pattern 1
Reference numeral 5 denotes a fixing pad 16 and a fixing pad 1 provided approximately in the center of the film substrate 10 on which a semiconductor element is placed.
It is composed of a plurality of electrode leads 17 extending in four directions from the vicinity of 6. Also, this electrode lead 1
7 are arranged in parallel in each direction and at regular intervals, and ultimately function as external terminals.

なお製造中フイルム基板10を移送する際に加
わる力から各導電パターン15を保護するため
に、フイルム基板10の両端にインデツクス孔1
4を含んで連続した帯状パターン18を設け、更
に必要であれば帯状パターン18をはしご状に接
続する連結パターン19を設けて完全に導電パタ
ーン15を囲む。このとき導電パターン15は帯
状パターン18および連結パターン19と電気的
に独立させ、且つ各電極リード17も夫々電気的
に独立させておく。
Incidentally, in order to protect each conductive pattern 15 from the force applied when transferring the film substrate 10 during manufacturing, index holes 1 are provided at both ends of the film substrate 10.
A continuous strip pattern 18 including the conductive pattern 15 is provided, and if necessary, a connecting pattern 19 for connecting the strip patterns 18 in a ladder shape is provided to completely surround the conductive pattern 15. At this time, the conductive pattern 15 is made electrically independent from the strip pattern 18 and the connection pattern 19, and each electrode lead 17 is also made electrically independent from each other.

本発明の第3の工程は第5図に示す如く、フイ
ルム基板10の他方の銅箔12をエツチングして
支持パターン20を各導電パターン15に対応し
て形成することにある。支持パターン20は点線
で示した導電パターン15の固着パツド16およ
び電極リード17のボンデイングが行なわれる固
着パツド16の近傍部分に重畳して形成される。
この支持パターン20は固着パツド16およびす
べての電極リード17の端部を接着剤13を介し
て一体的に支持し、支持機能を全く有さない接着
剤13の薄層に代つて導電パターン15を支持す
る。
The third step of the present invention, as shown in FIG. 5, consists in etching the other copper foil 12 of the film substrate 10 to form support patterns 20 corresponding to each conductive pattern 15. The support pattern 20 is formed so as to overlap the fixing pad 16 of the conductive pattern 15 shown by the dotted line and the vicinity of the fixing pad 16 where the electrode lead 17 is bonded.
This support pattern 20 integrally supports the fixing pad 16 and the ends of all electrode leads 17 via the adhesive 13, and the conductive pattern 15 is used in place of the thin layer of adhesive 13 that has no supporting function. To support.

また前述した帯状パターン18および連結パタ
ーン19を補強するために帯状パターン18およ
び連結パターン19と対応する部分に他方の銅箔
12を残して補強パターン21を設ける。更に各
電極リード17の外部端子として働く部分に対応
して他方の銅箔12を残して裏リード22を設
け、且つこの裏リード22を延長して補強パター
ン21と接続し各電極リード17の他端も補強パ
ターン21により一体的に支持する。
Further, in order to reinforce the band pattern 18 and the connection pattern 19 described above, a reinforcing pattern 21 is provided in a portion corresponding to the band pattern 18 and connection pattern 19, leaving the other copper foil 12. Furthermore, a back lead 22 is provided corresponding to the part of each electrode lead 17 that serves as an external terminal, leaving the other copper foil 12, and this back lead 22 is extended and connected to the reinforcing pattern 21, and the other part of each electrode lead 17 is connected to the reinforcing pattern 21. The ends are also integrally supported by the reinforcing pattern 21.

上述した如く導電パターン15は夫々電気的に
独立していても裏面に設けた支持パターン20、
補強パターン21および裏リード22によつて接
着剤13を介して帯状パターン18および連結パ
ターン19で形成される枠内に一体に支持できる
のでフイルム基板10の状態で製造に用いられ
る。
As described above, even if the conductive patterns 15 are electrically independent, the support patterns 20 provided on the back side,
Since the reinforcing pattern 21 and the back lead 22 can be integrally supported within the frame formed by the strip pattern 18 and the connecting pattern 19 via the adhesive 13, the film substrate 10 can be used for manufacturing.

前述した第2の工程および本工程の銅箔11,
12のエツチングは同時に行うことができる。即
ちフイルム基板10の両面の銅箔11,12に所
望形状にレジストをスクリーン印刷した後に両面
エツチング装置内にフイルム基板10を連続して
送り込み、エツチング液を対向するノズルからフ
イルム基板10の両面に吹き付けて同時に両面エ
ツチングを行う。
Copper foil 11 in the second step and main step described above,
Twelve etchings can be performed simultaneously. That is, after screen printing a resist in a desired shape on the copper foils 11 and 12 on both sides of the film substrate 10, the film substrate 10 is continuously fed into a double-sided etching device, and an etching solution is sprayed onto both sides of the film substrate 10 from opposing nozzles. Perform etching on both sides at the same time.

更に導電パターン15の必要な部分例えば電極
リード17の少くとも超音波ボンデイングを行う
固着パツド16側の端部にニツケルメツキ層を付
着形成しておく。
Further, a nickel plating layer is deposited on necessary parts of the conductive pattern 15, for example, at least the ends of the electrode leads 17 on the fixing pad 16 side where ultrasonic bonding is performed.

本発明の第4の工程は第6図に示す如く、各導
電パターン15の固着パツド16に半導体素子2
3を固着し、半導体素子23の電極と対応する電
極リード17とをボンデイング細線により接続す
る。ボンデイング細線は前述したニツケルメツキ
層上にボンデイングする。
As shown in FIG. 6, the fourth step of the present invention is to attach a semiconductor element 2 to the fixing pad 16 of each conductive pattern 15
3 is fixed, and the electrodes of the semiconductor element 23 and the corresponding electrode leads 17 are connected using bonding thin wires. The bonding thin wire is bonded onto the nickel plating layer described above.

導電パターン15等を形成したフイルム基板1
0を収納したカートリツジからインデツクス孔1
4を用いてコマ送りしてフイルム基板10を供給
し、各導電パターン15の固着パツド16に半導
体素子23を銀ペーストあるいは半田を用いて固
着した後に自動ボンデイング装置により半導体素
子23の電極と対応する電極リード17とをアル
ミニウムのボンデイング細線で接続する。各電極
リード17は電気的に独立しているのでボンデイ
ング終了後各電極リード17に検査用の針をたて
て通電し各半導体素子23の回路機能検査を行い
必要あればフアンクシヨナルトリミング等を行
い、不良の場合には半導体素子23を交換して再
生するかあるいは特別のマークを付けて以後の組
立工程を中止して完成品の歩留の向上を図る。
Film substrate 1 on which conductive patterns 15 etc. are formed
Index hole 1 from the cartridge containing 0
4 to feed the film substrate 10 frame by frame, and after fixing the semiconductor elements 23 to the fixing pads 16 of each conductive pattern 15 using silver paste or solder, the film substrates 10 are bonded to correspond to the electrodes of the semiconductor elements 23 by an automatic bonding device. The electrode lead 17 is connected with a thin aluminum bonding wire. Since each electrode lead 17 is electrically independent, after bonding is completed, a test needle is placed on each electrode lead 17 and energized to test the circuit function of each semiconductor element 23. If necessary, perform function trimming, etc. If the semiconductor element 23 is defective, the semiconductor element 23 is replaced and regenerated, or a special mark is attached and the subsequent assembly process is stopped to improve the yield of the finished product.

この検査後半導体素子23およびボンデイング
細線をシリコンレジン等の保護樹脂で被覆する。
After this inspection, the semiconductor element 23 and the bonding wire are coated with a protective resin such as silicone resin.

本発明の第5の工程は第7図に示す如く、フイ
ルム基板10の導電パターン15の外部端子とな
る電極リード17を残して他を樹脂24でモール
ドすることにある。
The fifth step of the present invention, as shown in FIG. 7, consists in molding the conductive pattern 15 of the film substrate 10 with a resin 24 except for the electrode lead 17 which will become the external terminal.

樹脂モールドはフイルム基板10のままでコマ
送りをして1個ないし数個づつ粉末のエポキシ樹
脂を吹き付けて加熱硬化させて外部端子となる部
分の電極リード17を露出させて全体をモールド
する。その後第7図で一点鎖線で示す部分で電極
リード17および補強パターン21を切断して個
別の半導体装置に分離する。なお電極リード17
と裏リード22とは接着剤13で絶縁されている
ので、第8図に示す如く貫通孔25を設けてその
孔に半田26を充填して電極リード17と裏リー
ド22を電気的に接続する。また裏リード22は
プリント基板への半田付けの際に用いられる。
The resin mold is moved frame by frame with the film substrate 10 as it is, and powdered epoxy resin is sprayed on one or several pieces at a time and heated and hardened to expose the electrode leads 17 which will become external terminals, and the whole is molded. Thereafter, the electrode lead 17 and reinforcing pattern 21 are cut at the portion indicated by the dashed line in FIG. 7 to separate the semiconductor devices into individual semiconductor devices. Note that the electrode lead 17
Since the electrode lead 17 and the back lead 22 are insulated by the adhesive 13, a through hole 25 is provided as shown in FIG. 8, and the hole is filled with solder 26 to electrically connect the electrode lead 17 and the back lead 22. . Further, the back lead 22 is used when soldering to a printed circuit board.

以上に詳述した如く本発明に依れば、二枚の銅
箔を貼り合せたフイルム基板によりポリイミド膜
等を用いない安価なフイルムキヤリア方式の量産
ができる。また本発明では半導体素子を固着後に
フイルム状のままで半導体素子の回路機能検査を
行うことができ完成品の歩留が大巾に向上する。
更に本発明では最終工程までフイルム状のままで
製造することができ一貫したフイルムキヤリア方
式を確立できる。
As described in detail above, according to the present invention, it is possible to mass-produce an inexpensive film carrier method using a film substrate with two copper foils bonded together without using a polyimide film or the like. Further, according to the present invention, the circuit function test of the semiconductor element can be carried out while the semiconductor element remains in the film form after being fixed, and the yield of finished products is greatly improved.
Furthermore, according to the present invention, the film can be manufactured in a film state until the final step, and a consistent film carrier system can be established.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は周知のフレキシブル基板を説明する断
面図、第2図は本発明を適用するフレキシブルフ
イルム基板を説明する断面図、第3図乃至第7図
は本発明の各工程を説明する平面図、第8図は本
発明により完成した半導体装置を説明する断面図
である。 主な図番の説明、10…フイルム基板、11,
12…二枚の銅箔、15…導電パターン、17…
電極リード、20…支持パターン、23…半導体
素子、24…モールド樹脂である。
FIG. 1 is a sectional view illustrating a well-known flexible substrate, FIG. 2 is a sectional view illustrating a flexible film substrate to which the present invention is applied, and FIGS. 3 to 7 are plan views illustrating each process of the present invention. , FIG. 8 is a sectional view illustrating a semiconductor device completed according to the present invention. Explanation of main figure numbers, 10...Film substrate, 11,
12... Two copper foils, 15... Conductive pattern, 17...
Electrode lead, 20... Support pattern, 23... Semiconductor element, 24... Molding resin.

Claims (1)

【特許請求の範囲】[Claims] 1 二枚の銅箔を熱硬化性樹脂で接着し且つ該樹
脂で互いに絶縁されたフイルム基板を形成する工
程、該基板の一方の銅箔をエツチングして形成し
た半導体素子の固着パツドおよび該固着パツド近
傍から延在される複数本の電極リードより成る導
電パターンを形成する工程、前記基板の他方の銅
箔をエツチングして形成され前記固着パツドおよ
び電極リードの一部と重畳する支持パターンを形
成する工程、前記固着パツドに半導体素子を固着
し該素子の電極と前記電極リードとをボンデイン
グにより接続する工程と、前記電極リードの外部
端子となる部分を露出して全体をモールドする工
程を具備することを特徴とする半導体装置の製造
方法。
1. A step of bonding two copper foils with a thermosetting resin and forming a film substrate insulated from each other with the resin, a fixing pad for a semiconductor element formed by etching one of the copper foils of the substrate, and the fixing. forming a conductive pattern consisting of a plurality of electrode leads extending from the vicinity of the pad; forming a support pattern formed by etching the other copper foil of the substrate and overlapping a portion of the fixing pad and the electrode lead; a step of fixing a semiconductor element to the fixing pad and connecting an electrode of the element to the electrode lead by bonding; and a step of exposing a portion of the electrode lead that will become an external terminal and molding the whole. A method for manufacturing a semiconductor device, characterized in that:
JP56027381A 1981-02-25 1981-02-25 Manufacture of semiconductor device Granted JPS57141947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56027381A JPS57141947A (en) 1981-02-25 1981-02-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56027381A JPS57141947A (en) 1981-02-25 1981-02-25 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57141947A JPS57141947A (en) 1982-09-02
JPS6152977B2 true JPS6152977B2 (en) 1986-11-15

Family

ID=12219465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56027381A Granted JPS57141947A (en) 1981-02-25 1981-02-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57141947A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167281U (en) * 1981-04-14 1982-10-21
JP4161399B2 (en) * 1998-03-12 2008-10-08 沖電気工業株式会社 Resin substrate for semiconductor device and semiconductor device
KR100838661B1 (en) 2006-06-23 2008-06-16 안동대학교 산학협력단 Electrochemical Biosensor Electrode Manufacturing Method

Also Published As

Publication number Publication date
JPS57141947A (en) 1982-09-02

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