JPS6152987B2 - - Google Patents

Description

[Detailed description of the invention] The present invention is a highly integrated ( LSI )
The present invention relates to semiconductor devices that are becoming increasingly integrated (integration), and particularly relates to a method of manufacturing a semiconductor device using a polycrystalline silicon (poly-Si) layer as an electrode or wiring. There have been remarkable advances in LSI technology in recent years, especially in MOS (Metal-Oxide-
The so-called Si gate technology, which uses poly-Si as the gate electrode and forms the source and drain in self-alignment, plays a major role in field-effect transistor (FET) LSIs. However, in order to achieve even higher levels of integration, there are several problems with conventional Si gate technology, and it is imperative that these be resolved. Therefore, the conventional LSI n-channel MOSFET
The above-mentioned problems will be explained with reference to FIGS. 1a to 1h, taking the manufacturing method as an example. First, a p-type Si substrate 1 is prepared, and the surface of this p-type Si substrate is selectively oxidized to form approximately 1 μm of oxidized Si (SiO ₂ ).
This oxidation step of forming a film 2 (FIG. 1a) is a step for isolating elements, and this oxide film 2 is usually called a field oxide film. The field oxide film 2 is usually formed by selectively forming a silicon nitride (Si ₃ N ₄ ) film and thermally oxidizing the substrate using this as a mask. Next, the so-called exposed substrate surface on which the field oxide film 2 is not formed is oxidized.
A thin SiO ₂ film of about 700 Å that will later become the gate oxide film 3
A poly-Si layer 4 of about 3000 Å is formed on the entire surface of this SiO ₂ film 3 by, for example, vapor phase growth (FIG. 1b). Thereafter, phosphorus (P) is diffused into the poly-Si layer 4 at about 1000° C. for about 10 minutes using, for example, trichlorophosphoric acid (POcl ₃ ) as a diffusion source (FIG. 1c). In this way, polySi
When phosphorus is diffused into the layer 4, the resistance of the poly-Si layer 4' becomes approximately 20Ω/□, as shown by the solid line in FIG. Thereafter, a photoresist film 5 is selectively formed on the phosphorous-doped poly-Si layer 4', and the poly-Si layer 4' is patterned by plasma etching using, for example, Freon plasma. A poly-Si layer 4' is left as a wiring (Fig. 1d). Next, the resist film 5 is removed and, for example, the etched poly-Si layer 4' is used as a mask.
As ions are implanted at 1×10 ¹⁶ /cm ² at 150 keV and annealed for about 1 hour in a N ₂ atmosphere at, for example, 1000° C. to form a source region 6 and a drain region 7 (FIG. 1e). After the source region 6 and the drain region 7 are formed in this way, it contains about 1×10 ²¹ /cm ³ of phosphorus.
A SiO ₂ film, so-called PSG film 8, is formed on the entire surface with a thickness of about 1 μm.
This PSG film 8 is heat treated at a temperature of about 1050°C for 20 minutes to melt the PSG film surface, so-called reflow.
(Figure 1 f). This reflow makes the surface of the PSG film 8 smooth, which will be formed later.
There are fewer breaks in the Al layer. After this, contact holes are opened to take out the electrodes of the source region 6 and drain region 7,
The Al layer 9 is formed on the entire surface by vapor deposition, and the Al layer 9 is formed into an arbitrary pattern 9 by ordinary photolithography.
a, 9b. _After this _, in order to obtain ohmic contact, for example, about 10
Sinter for a minute (Figure 1g). Next, a PSG film 10 with a thickness of, for example, about 1 μm is formed on the entire surface, and an electrode extraction portion is formed in the opening 1 in this PSG film 10.
0a and complete (Figure 1h). When manufacturing a MOSFET in this way, the resistance value of the poly-Si layer 4' that serves as the electrode and wiring is approximately 20Ω/□ as described above, and this resistance value changes depending on the diffusion time of phosphorus. The result will be as shown by the solid line in Figure 2. As is clear from FIG. 2, the resistance decreases as the diffusion time increases, but it does not fall below about 20Ω/□. This is because the concentration in the poly-Si layer does not increase beyond the solid solubility. In addition, the poly-Si layer is used as wiring and electrodes for transmitting signals in LSI, and its resistance value must be reduced as much as possible in order to reduce the operating speed of the device. . For example, the thickness of the poly-Si layer should be doubled to around 3000 Å, or approximately
When the thickness is 6000 Å, the resistance is approximately halved, but as the thickness increases, accurate patterning becomes difficult, and in particular, it cannot be used in the process of forming fine patterns. The present invention has been made in view of the above-mentioned points.
The present invention provides a method for manufacturing a semiconductor device that can lower the resistance without increasing the thickness of the Si layer and improve the operating speed of the element. That is, the present invention involves manufacturing a semiconductor device in which a poly-Si layer serving as an electrode or wiring is doped with an impurity, and the impurity-doped poly-Si layer is irradiated with a laser beam through an insulating film to lower the resistance of the poly-Si layer. The present invention provides a method. The present invention will be described below based on embodiments and with reference to the drawings. Figures 3a to 3i are process cross-sectional views showing one embodiment of the present invention, and are LSI-based n-channel
This is an example when applied to a MOSFET manufacturing method. First, as in the conventional method, a p-type Si substrate 11 is prepared, and this p-type Si substrate 11 is selectively oxidized to form a field oxide film 12 of about 1 μm (FIG. 3a). Next, the exposed surface of the substrate 11 on which the field oxide film 12 is not formed is oxidized to form a thin SiO ₂ film 1 of about 700 Å, which will become the gate oxide film.
form 3. Then, a poly-Si layer 14 of about 3000 Å is formed on the entire surface of this SiO ₂ film 13 by, for example, vapor phase growth (FIG. 3b). Thereafter, phosphorus (P) is diffused into the poly-Si layer 14 at about 1000° C. for about 10 minutes using, for example, trichlorophosphoric acid (POcl ₃ ) as a diffusion source (FIG. 3c). When phosphorus is diffused into the poly-Si layer 14 in this manner, the resistance of the poly-Si layer 14' becomes approximately 20 Ω/□, as shown by the solid line in FIG. Thereafter, a photoresist film 15 is selectively formed on the phosphorous-doped poly-Si layer 14', and the poly-Si layer 14' is patterned by plasma etching using, for example, Freon plasma. A poly-Si layer 14' is left as a wiring (FIG. 3d). Next, the resist film 15 is removed, and As ions are implanted at 1×10 ¹⁶ /cm ² at 150 keV using the etched poly-Si layer 14' as a mask, for example, in an N ₂ atmosphere at 1000°C. Annealing is performed for about one hour to form a source region 16 and a drain region 17 (FIG. 3e). After the source region 16 and drain region 17 are formed in this manner, a SiO ₂ film containing phosphorus at a concentration of about 1×10 ²¹ /cm ^{3 ,} the so-called PSG film 18, is formed over the entire surface to a thickness of about 1 μm. Heat treatment is performed at a temperature of about 1050° C. for 20 minutes to melt the PSG film surface, so-called reflow (Fig. 3 f). By this reflow, the surface of the PSG film 18 becomes smooth, and there are fewer breaks in the Al layer that will be formed later. After that, the poly-Si layer 1 is
4' is irradiated with laser light 30, which is a feature of the present invention (FIG. 3g). Laser light used here 30
A pulsed laser beam was used, and an Nd-YAG laser device as shown in Figure 4 with a maximum output of 10W was used. The output light from the laser light source 41 of this Nd-YAG laser device, the so-called laser light 30, is the first
It is bent by 90 degrees by the reflecting mirror 43 through the lens 42, and the second lens 44
m, and irradiates a wafer 46 placed on a stage 45. Furthermore, the above stage 45 is
By scanning in the direction and Y direction,
The entire surface of the wafer 46 on which the Si layer is formed can be irradiated.
Also, the pulse width of the pulsed laser beam used here is
The time was 20nsec to 200nsec, and the frequency was 5KHz to 30KHz. PSG film 18 reflowed in this way
By irradiating the poly-Si layer 14' with laser light 30 through the poly-Si layer 14', the resistance of the poly-Si layer 14' is
As shown by the dotted line in the figure, the resistance becomes about 1/2 that before irradiation with the laser beam 30, that is, about 10 Ω/□, making it suitable for using this poly-Si layer 14' as a gate electrode or wiring. In this way, the poly-Si layer 14' is inserted through the PSG film 18.
After irradiating the laser beam 30 to the source region 16
A contact hole is opened for taking out the electrode in the drain region 17, and an Al layer 19 is formed on the entire surface by vapor deposition, and the Al layer is formed into arbitrary patterns 19a and 19b by ordinary photolithography. After this, in order to obtain ohmic contact, e.g.
Heat treatment (sintering) is performed for about 10 minutes in a forming gas (H ₂ :H ₂ =10% by volume: 90% by volume) atmosphere (Fig. 3h). Next, a PSG film 20 with a thickness of, for example, 1 μm is formed on the entire surface, and an electrode extraction portion is formed in the opening 2 in this PSG film 20.
0a and complete (Figure 3 i). When a MOSFET is manufactured in this way, the resistance of the poly-Si layer 14' is as shown by the dotted line in FIG.
It can be seen that the value has decreased to about half of the value before irradiation with laser light 30 times. The detailed mechanism of this phenomenon has not yet been elucidated, but irradiation with laser light 30 activates electrically inactive phosphorus (P) and at the same time changes the grain structure of the poly-Si layer. It is thought that the carrier's mobility has also increased.
Furthermore, when a poly-Si layer (approximately 3000 Å) is doped with As, the lowest resistance is approximately 30Ω/□, but this value can be further reduced to approximately half by irradiation with laser light. However, after irradiation with laser light 30 times, heat treatment at 600°C or higher, for example, ion implantation to form the source region 16 and drain region 17, at 1000°C for about 1 hour, or PSG
There is a phenomenon in which the resistance of the poly-Si layer returns to around its original value when a heat process is performed to reflow the film 18 (at 1050°C for 20 minutes). If a step of irradiating the laser beam 30 is included after the formation of the Al layer 17 and after the reflow of the PSG film, the subsequent thermal steps are only a thermal step for making ohmic contact with the Al layer 19 and a step of vapor phase growth of the PSG film 20. , both have temperatures lower than 500℃, and the resistance value rarely returns to its original value. Even if the change occurs, it is about 10% when the poly-Si layer 14' is doped with (P).
When the Si layer 14' is doped with As, the amount is 10% or less. As can be seen from the above results, according to the present invention, the resistance of polysilicon can be reduced without increasing the thickness of the polysilicon layer, microfabrication of the polysilicon layer can be easily performed, and the resulting device can operate smoothly. It has excellent features such as being able to increase speed. In the above example, explanation was given only for the case where the laser light irradiation process is performed through the reflowed PSG film, but other than that, for example, vapor phase growth
There is nothing contrary to the gist of the present invention even if it is carried out through CVD SiO ₂ or a double layer of CVD SiO ₂ and PSG. Furthermore, when introducing impurities into the poly-Si layer, we have described the diffusion of phosphorus (P) using _POcl3 as a diffusion source, but the impurity can also be As or boron, and in-phase diffusion or ionization can be used as a means of introducing impurities. It is clear that injection may also be used. Furthermore, although we have shown a case in which impurities are introduced into the poly-Si layer separately from the formation of the source and drain regions, it is also possible to introduce impurities into the poly-Si layer at the same time as forming the source and drain regions. good. Further, in the above embodiment, a p-type Si substrate is used, but it may be an n-type Si substrate, and in this case, boron or the like is used as the impurity to be diffused. Furthermore, in the above embodiment, the n-channel MOSFET
Although this has been explained, it can also be applied to CMOS and bipolar transistors.

[Brief explanation of the drawing]

Figures 1a to 1h are cross-sectional views showing the manufacturing process of an n-channel MOSFET, which is one of the conventional semiconductor devices. Figure 2 is a curve showing the resistance change of the poly-Si layer with respect to the diffusion time of phosphorus from _POcl3 . In the figure, the solid line is the conventional case, the dotted line is the case of the embodiment of the present invention, and FIGS. , FIG. 4 is a perspective view schematically showing the laser device for irradiating the laser beam in FIG. 3. 11... p-type Si substrate, 12... field oxide film, 13... SiO ₂ film to be gate oxide film, 14
...Poly-Si layer, 14'... Linguar-doped poly-Si layer, 15... Photoresist film, 16... Source region, 17... Drain region, 18... Reflowed PSG film, 19a and 19b... Patterned Al layer, 20...PSG film, 20a
...Aperture for taking out the electrode, 30...Laser light.

Claims (1)

[Claims] 1. When manufacturing a semiconductor device using a polycrystalline silicon layer doped with impurities as an electrode or wiring, one or more insulating films are formed on the polycrystalline silicon layer doped with impurities. A method of manufacturing a semiconductor device, characterized in that at least a portion of the polysilicon layer is irradiated with laser light through the insulating layer. 2 Heat-treating and melting the surface of the insulating film on which at least an electrode or wiring layer is formed among the one or more insulating layers, and irradiating at least a portion of the polysilicon layer with laser light through the melted insulating film. A method for manufacturing a semiconductor device according to claim 1, characterized in that: 3. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the one or more insulating films is a silicon oxide film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the one or more insulating films is a silicon oxide film doped with phosphorus, arsenic, or boron. 5. Claim 1, characterized in that As is used as an impurity to be doped into the poly-Si layer.
A method for manufacturing a semiconductor device according to section 1. 6. Claim 1, characterized in that phosphorus is used as an impurity doped into the poly-Si layer.
A method for manufacturing a semiconductor device according to section 1.