JPS6153735B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device in a CRT terminal control device.

CRT used as a terminal device for electronic computers
The terminal control device inputs data according to a predetermined format, displays the input data on a CRT screen, and then transfers it to a CPU (information processing device). When performing data entry using a display device in this way, the display screen is generally divided into a fixed field and an input field, guidance data is displayed on the fixed field, and the operator enters the input field according to this guidance data. Enter data into. In this case, the area other than the input field is protected as a protect field to prevent key input. The above input fields are cleared prior to data input, but conventionally, all input fields are simply cleared, and after clearing, a predetermined code is written in all input fields to indicate the position of the input field. be.

If you want to clear the input field mentioned above, it can be easily done because the terminal side has a command for clearing the input field, but since the position and number of digits of the input field cannot be identified,
The disadvantage is that operator guidance-like displays cannot be provided. In addition, when writing a predetermined code to all input fields, an operator guidance display can be performed, but conventionally the CPU sends a predetermined code to all input fields, which reduces the amount of data transferred. There are a lot of problems, and the disadvantage is that the line cost is high.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a display device that can write and display predetermined codes in all input fields without increasing the amount of data transferred.

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of the CRT terminal control device will be explained with reference to FIG. In Figure 1, DB is
A data bus that transmits data from a CPU (not shown).This data bus DB is connected to an internal bus 2 via an interface 1 that operates according to an operation command I from the CPU.
A CRT controller 3 and screen memory 4 are connected. Furthermore, a line data memory 5 is connected to the internal bus 2 via a gate circuit _G1 , and a line control memory ₆ is also connected via a gate circuit G2. And above
The CRT controller 3 is given a read/write command R/W1 and an enable signal _E1 from the CPU, and address data is also input via the address bus AB. The CRT controller 3 mentioned above performs reading and writing control of the screen memory 4, cursor movement control, etc., which will be described in detail later.
Read/write command R/W to screen memory 4
2. Give the gate signal GS to the gate circuit G ₃ and the cursor address data and address register designation signal AS to the address register (AR) 7. The data set in the address register 7 is input to the screen memory 4 via the gate circuit _G3 . Furthermore, the count contents of the address counter 10, which are sequentially counted up in response to signals from the synchronization control circuit 9, are input to the screen memory 4 via the gate circuit _G3 . This screen memory 4 includes a screen data memory SDM and a screen control memory as shown in Figure 2.
For example, 1, 3, 5...2n
+1 odd address is screen data memory SDM
The even addresses 0, 2, 4, . . . 2n are the areas of the screen control memory SCM. This screen control memory SCM contains, for example, control data indicating error e, duplication d, protect p, reverse r,
Control data for controlling the display state of blink b and half bright is stored. However,
Screen data memory in screen memory 4
The display data stored in the SDM is sent to the line data memory 5 via the gate circuit _G1 as described above, and then sent to the screen control memory.
The control data stored in the SCM is sent to the line control memory 6 via the gate circuit _G2 . The line data memory 5 and line control memory 6 are composed of shift registers,
Gate circuit for each raster scan of the screen
It makes one cycle via G ₁ and G ₂ and stores and holds data. The line data memory 5 and the line control memory 6 are used to store the next line display data and control read out from the screen memory 4 via the gate circuits G ₁ and G ₂ every time one line of the screen (one line of characters) is scanned. Store data. In this case, the synchronization control circuit 9 controls the gate circuits G ₁ and G ₂ . The line data stored in the line data memory 5 is
It is sent to the character generator 11. This character generator 11 operates in synchronization with a signal from the synchronous control circuit 9, and generates character data for input line data. This character data is converted into serial data via a PS (parallel-serial) conversion circuit 12 and sent to a synthesis circuit 13. Further, the control data stored in the line control memory 6 is detected by the detection circuit 14, and a control signal based on the detected content is sent to the synthesis circuit 13 and synthesized with the display data. The signal synthesized by this synthesis circuit 13 is passed through an OR circuit 15 as a video signal.
The signal is sent to a CRT display unit (not shown). moreover,
This CRT display section includes a coincidence detection circuit 16 that detects coincidence of contents between the address register 7 and the address counter 10 according to a signal from the synchronization control circuit 9.
The output of is inputted via the OR circuit 15. This matching circuit 16 detects the position of the cursor display. Further, a horizontal synchronizing signal H.SYNC and a vertical synchronizing signal V.SYNC are applied to the CRT display section.

Next, details of the CRT controller 3 will be explained with reference to FIG. CPU to data bus DB
The data given to the internal bus 2 via the interface 1 is input to the input register 21 in the CRT controller 3 or the cursor counter (CC) 2.
2. Also, read and write commands R/W sent from the CPU to the CRT controller 3
1, the enable signal E ₁ and address data are input to the address decoder 23. Address decoder 23 selects input register 21 or cursor counter 22 according to address data sent from the CPU via address bus AB, and issues a write command. Then, the input register 2
The data set to 1 is sent to the control circuit 24 and also to the buffer 25 via the gate circuit _G4 . The data temporarily stored in the buffer 25 is returned to the internal bus 2 via the gate circuit _G6 and transferred to the screen memory 4. Further, the data set in the input register 21 is sent to the protect bit detection circuit 2 via the gate circuit _G5 .
6 and the duplex bit detection circuit 27. The read/write signal R/W2 outputted from the control circuit 24 is applied to the gate circuit _G5 via an inverter 28 as a gate signal. The control circuit 24 decodes the input data, and outputs the read and write commands R/W2 and the gate signal.
It outputs GS, address register designation signal AS, and other control signals from output lines a to c. That is, the output line a of the control circuit 24 outputs a "1" signal when the erase code of the input field is input, and the output line b outputs a cursor signal according to the cursor key when the cursor key is operated. A control signal is output. In addition, from the output line c of the control circuit 24, an input field clear command (hereinafter referred to as
When an EFC command (abbreviated as EFC command) and an erase code are input, a "1" signal is output. However,
The signal output from the output line a of the control circuit 24 is sent to the gate circuit _G4 as a gate signal,
The cursor control signal output from output line b is sent to ±1 circuit 29. This ±1 circuit 29 counts up or down the contents of the cursor counter 22 in accordance with the input cursor control signal. Further, the signal output from the output line c of the control circuit 24 is transmitted to the flip-flop 30.
is applied to the set terminal S of the cursor counter 22 and also to the clear terminal of the cursor counter 22. The output signal of the flip-flop 30 is transmitted to the control circuit 2.
It is applied to the AND circuit 31 together with the read/write signal R/W2 outputted from R/W2. Furthermore, this AND circuit 31 includes a protect bit detection circuit 2.
6 and the output of the duplex bit detection circuit 27 are input via an inverter 32. and,
A gate circuit is formed by the output of this AND circuit 31.
G ₆ gate control is performed. Further, the output of the flip-flop 30 is sent to the end detection circuit 33 as an operation command. This end detection circuit 3
3 is for detecting when the count content of the cursor counter 22 reaches the final position on the display screen, and the detection signal is applied to the reset terminal R of the flip-flop 30.

Next, the operation of the present invention configured as described above will be explained. For example, when creating a sales slip for inventory management, data is input from the key input section according to a predetermined data format that has been selected and designated in advance and displayed on the CRT display section, as shown in FIG. 4, for example. Data input from this key input section is written to the screen data memory SDM in the screen memory 4. In this case, the screen control memory SCM is provided with a protect area p and a duplex area d corresponding to the data stored in the screen data memory SDM, as shown in FIG. A protect bit "1" is written in the protect bit area p for characters such as "No." and "Tokisaki Code" that should not be erased, character spacing parts, etc. Furthermore, a duplication bit "1" is written in the duplication area d for items that can be copied.

Thus, after performing input processing for the first slip, when creating the next slip, the operator performs a clear operation on the input field. For example, input the expansion code ESC, input field erase command code EFC, and erase code to be written in the input field, such as the * mark code, in sequence from the keyboard.
By the above key operation, the portion of the input field other than the protect field and duplicator field is erased, and an asterisk (*) is displayed on the erased portion as shown in FIG. The above input field erasing operation will be explained below with reference to the flowchart of FIG. When the input field is erased, that is, the keys are operated in the order of ESC EFC □〓, this key input data is set in the input register 21 as shown in step A of Fig. 6, and the set contents are as shown in step B. It is decoded by the control circuit 24. When the control circuit 24 decodes that the key operations were performed in the above order,
□〓After key operation, “1” is output from output line a
Output a signal to open the gate of gate circuit _G4 ,
As shown in step C, write the 〓 mark code to buffer 2.
Enter into 5. Next, the control circuit 24 outputs a "1" signal from the output line c, and as shown in step D, the flip-flop 30 is set and the cursor counter 22 is cleared. Next, the control circuit 24 outputs the address register designation signal AS, and as shown in step E, the cursor counter 2
Transfer the contents of 2 to address register 7. Furthermore, the control circuit 24 provides the read/write signal R/W2 to the screen memory 4 in read mode (“0”), and as shown in step F, the control circuit 24 applies the read/write signal R/W2 to the screen control memory 4 indicated by the address register 7.
The contents of the SCM, in this case the contents of address 0, are read and set in the input register 21. Thereafter, the control circuit 24 outputs a cursor control signal from the output line b to the ±1 circuit 29, and the content of the cursor counter 22 is incremented by 1 as shown in step G. Next, the control circuit 24 outputs the address register designation signal AS to transfer the contents of the cursor counter 22 to the address register 7 as shown in step H.
Thereafter, as shown in step I, the input buffer 21
The control data held in the gate circuit
The signal is sent to the protect bit detection circuit 26 and the duplex bit detection circuit 27 via _G5 , and detects the protect bit and the duplex bit. If neither the protect bit nor the duplex bit is detected in step I, the outputs of both the detection circuits 26 and 27 are "0", and the output of the inverter 32 is "1".
The result is added to the AND circuit 31. At this time,
The read/write signal R/W2 output from the control circuit 24 enters the write mode (“1”) as shown in step J, and the gate of the AND circuit 31 is opened to screen the 〓 mark code held in the buffer 25. Transfer to memory 4 and address register 7
Write to the screen data memory SCM indicated by . Next, proceed to step K, where the end detection circuit 3
3, it is determined whether the contents of the cursor counter 22 have reached the final value. As a result of this determination, if the contents of the cursor counter 22 have reached the final value, the flip-flop 30 is reset, but if the contents have not reached the final value, the process returns to step E and the contents of the cursor counter 22 are incremented by one. If either the protect bit or the duplication bit is detected in step I, the process immediately proceeds to step K without writing the mark code shown in step J. Repeat steps E to K in the same way, and enter the fourth input field.
As shown in the drawings and FIG. 5, cross-mark codes are sequentially written in areas that are not protected by the protect bit or duplication bit. Then, when the contents of the cursor counter 22 reach the final value,
The flip-flop 30 is reset by the output of the end detection circuit 33, and the erasing operation of the input field is completed.

As described above, according to the present invention, when erasing an input field, a predetermined code is stored in a buffer on the terminal side, and the codes stored in this buffer are sequentially read out and written in each digit of the input field. Therefore, the position and number of digits of the input field can be visually checked, any code can be written to the input field with simple key operations, and the amount of data transferred can be significantly reduced to lower line costs.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a configuration diagram showing details of the screen memory in FIG. 1,
Figure 3 is a block diagram showing details of the CRT controller part in Figure 1, Figure 4 is a diagram showing an example of display data, and Figure 5 is the storage of protect bits, duplication bits, and erase codes in the screen memory. The figure showing an example, FIG. 6, is a flowchart showing the operation contents. 2...Internal bus, 3...CRT controller, 4...
Screen memory, 7...address register (AR), 21...input register, 22...cursor counter (CC), 30...flip-flop (FF).

Claims (1)

[Scope of Claims] 1. Storage means for storing data to be displayed in fixed fields and input fields, and storing identification information for identifying fixed fields and input fields in correspondence with storage positions of the data storage means. identification information storage means; means for writing a specific code into the data storage means corresponding to the input field identified by the identification information in response to an input field deletion designation; a fixed field and an input field; and displaying the data in the data storage means,
and display means for displaying the specific code written by the writing means in an input field.