JPS6153897B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to muting control, particularly to a synchronous detection circuit having a muting control function suitable for selectively muting output signals after synchronous detection.

In a phase locked loop (PLL) circuit generally used for the purpose of synchronous quadrature detection, such as an AM stereo PLL circuit, the loop response frequency is set to the lower limit of the modulation frequency so as not to respond to sideband components. Therefore, if the capture range, that is, the PLL circuit is initially not locked, and the input signal is changed, the oscillation frequency range of the PLL circuit's VCO (high voltage controlled oscillator) that can lock to that signal becomes very narrow, and the PLL circuit cannot be locked manually. It is difficult to synchronize. For this reason, a lock detection circuit is usually provided, and its output controls the gain and CR constant of the low frequency amplifier and DC amplifier included in the PLL circuit, so that it has a large capture range when the lock is lost. The capture range is switched to a predetermined band, and the first
The diagram is also an example.

In other words, in FIG. 1, an intermediate frequency input signal supplied to an input terminal 1 is supplied to an amplitude limiter 2 to remove its amplitude component, and then supplied to a PLL circuit 3 and a multiplier 4 having a phase comparison function. Supplied to one input end. An output signal that is 90 degrees out of phase with the input signal is taken out from the output side of the PLL circuit 3, and this signal is phase-shifted by 90 degrees in the phase shifter 5, and is again output to the multiplier 4 as a signal that is in phase with the input signal. supplied to the other input end. The multiplier 4 compares the phases of the signal directly input from the amplitude limiter 2 and the signal supplied through the phase shifter 5, and in the locked state generates a DC signal on its output side through the low frequency filter 6.
When the lock is released, the output side of the wave generator 6 is prevented from generating a DC signal. Note that the multiplier 4, phase shifter 5, and low frequency converter 6 constitute a phase difference detection circuit.

The output signal of the wave generator 6 is supplied to a lock detection circuit 7, and when a DC signal appears in the output measurement of the wave generator 6, that is, in a lock state, the lock detection circuit 7 narrows the capture range of the PLL circuit 3 using the output signal. When a DC signal does not appear on the output side of the wave generator 6 in a predetermined band, that is, when the lock is released, the capture range of the PLL circuit 3 is widened. This makes manual tuning easier.

Further, the output signal of the PLL circuit 3 is supplied to one input terminal of the multiplier 8, and the input signal from the input terminal 1 is directly supplied to the other input terminal of the multiplier 8. As a result, a desired audio frequency signal is extracted at the output side of the multiplier 8.

By the way, in synchronous detection, when the lock is lost, a beat is generated between the input signal and the output signal of the VCO of the PLL circuit 3. Therefore, a muting switch 9 is provided after the multiplier 8, and when the lock is lost, a muting switch 9 is provided. The muting switch 9 is released by the output signal from the multiplier 8 so that the output signal of the multiplier 8 is not sent to the output terminal 10, that is, muting is applied.

By the way, in the case of the conventional circuit configured as described above, if the muting switch 9 is directly driven by the output signal of the lock detection circuit 7, when the frequency of the input signal changes continuously, such as during manual tuning, etc.
The capture range of PLL circuit 3 is locked in.
Because it is alternately widened and narrowed depending on the lockout, when an audio frequency stage or speaker (not shown) is connected to the output terminal 10 and the audio signal is opened, abnormal noise occurs in the audio signal. There were drawbacks such as:

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a muting circuit that does not cause abnormal noise in the output audio signal even when the frequency of the input signal changes continuously.

An embodiment of the present invention will be described in detail below with reference to FIGS. 2 and 3.

FIG. 2 shows the configuration of this embodiment. In FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, the lock detection circuit 20 is constituted by circuits having a plurality of threshold voltages, for example, threshold circuits 21 and 22 having threshold voltages Vth ₁ and Vth ₂ , respectively. The threshold voltages Vth ₁ and Vth ₂ have a relationship of Vth ₂ > Vth ₁ , and the output signal of the threshold circuit 21 is used to switch the capture range band of the PLL circuit 3, and the output signal of the threshold circuit 22 is used to switch the muting switch. The opening and closing of 9 is controlled. The rest of the structure is the same as that shown in FIG.

Next, the operation of this embodiment will be explained with reference to FIG. Note that the horizontal axis in FIG. 3 represents the phase difference between the signals supplied to each input terminal of the multiplier 4, that is, the input/output phase difference of the PLL circuit 3, and the subordinate axis represents the DC signal appearing on the output side of the low-frequency amplifier 16. shall represent the level of

When the lock is currently off, the threshold circuit 21 widens the capture range band of the PLL circuit 3 to facilitate manual tuning, while the threshold circuit 22 outputs the output signal of the multiplier 8 to the output terminal 10. Muting switch 9 is released to apply muting so that it is not transmitted. When the lock gradually increases and the output level of the low frequency converter 6 reaches the threshold voltage Vth ₁ as shown in FIG. 3, the threshold circuit 21 uses its output signal to narrow the band of the capture range of the PLL circuit 3. switch to the opposite direction, pull in the tuning signal, and enter the lock state. Furthermore, when the output level of the low frequency converter 6 reaches the threshold voltage Vth ₂ as shown in FIG.
Threshold circuit 22 uses its output signal to close muting switch 9 to release muting, and passes the output of multiplier 8 to output terminal 10.

Therefore, while the frequency of the input signal is fluctuating, that is, when the lock is not applied, the muting is active and no abnormal noise is generated on the output side.

As described above, according to the present invention, a plurality of detection signals corresponding to phase lock states are obtained in the lock detection circuit, and muting is canceled after narrowing the capture range of the PLL circuit based on these detection signals. Therefore, muting is not canceled while the frequency of the input signal is changing, and even if the frequency of the input signal changes continuously, no abnormal noise will be produced in the output audio signal.

It goes without saying that the present invention is not limited to the above-described embodiments, but can be similarly applied to other circuits that use synchronous detection.

Also, although not shown, the threshold voltage Vth ₁ and
A third threshold voltage Vth ₃ may be provided between Vth ₂ and this voltage Vth ₃ may be used to drive an indicator indicating the lock state.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram showing an example of a conventional circuit.
FIG. 4 is a diagram for explaining the operation of the figure. 3 is a PLL circuit, 4 and 8 are multipliers, 6 is a low frequency amplifier, 9 is a muting switch, and 20 is a lock detection circuit.

Claims (1)

[Claims] 1. In a synchronous detection circuit having a phase lock loop circuit whose capture range can be switched, a muting means for mutating a signal synchronously detected by the synchronous detection circuit, and a signal supplied to the phase lock loop circuit. and a phase difference detection circuit for detecting a phase difference between the signal output from the phase lock loop circuit and the signal output from the phase lock loop circuit, and the phase difference detected by the phase difference detection circuit reaches a first set value. and forms a control signal for switching the capture range of the phase lock loop circuit to a narrow range, and also corresponds to the fact that the phase difference detected by the phase difference detection circuit further reaches a second set value. By providing a lock detecting means for forming a control signal for canceling the operation of the muting means, after the capture range of the phase lock loop circuit is switched to a narrow range, the lock detecting means can be synchronized by the synchronous detection circuit. A synchronous detection circuit equipped with a muting control function characterized in that muting of a detected signal is canceled.