JPS6153911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color demodulation system for a SECAM color video circuit.

The carrier color signal of the SECAM color video signal is a line sequential signal in which an FM signal modulated by a blue color difference signal and an FM signal modulated by a red color difference signal are alternately arranged for each horizontal period. Therefore, in a SECAM type color receiver, it is necessary to perform color demodulation by converting the conveyed color signal from a line sequential signal to a simultaneous signal.

FIG. 1 shows an example of such a color demodulation system, in which a SECAM color video signal is supplied to a bandpass filter 1 and a carrier color signal Sc is extracted. As mentioned above, this signal Sc is also
As shown in Figure A, FM signal with blue color difference signal
Cb and the FM signal Cr based on the red color difference signal are line sequential signals, and the FM signal Cb has a carrier frequency f
_b = 4.25MHz, and the FM signal Cr has a carrier frequency f _r
〓It is said to be 4.41MHz. Furthermore, during the backport period of the horizontal synchronizing pulse, the signal Sc is not modulated by the color difference signal and is used as discrimination signals (unmodulated subcarriers) Db and Dr.

This signal Sc is then supplied to a switch circuit 4 through a bell filter 2 and a limiter 3, and is also supplied to a delay circuit 5 to become a signal Sd delayed by one horizontal period as shown in FIG. 2B. is supplied to the switch circuit 4.

In addition, flyback pulse Pf is transmitted through terminal 11.
_is supplied to the shaping circuit ₁₂ , and as shown in FIG. 13 to a flip _- flop circuit 14 to form a signal _S14 which is inverted at every leading edge of the pulse _P12 as shown in FIG. ₁₂ is supplied to the OR circuit 15, and the signal _S15 shown in FIG. 2E is taken out from the OR circuit 15. This signal _S15 is supplied to the switch circuit 4 as a control signal, and the switch circuit ₄ receives
When it is “1”, it is switched to the state shown in the figure, and S ₁₅ =
When it is "0", the state is switched to the opposite state as shown in the figure.

Therefore, from the switch circuit 4, the signals F and G in FIG.
As shown in the figure, the synchronized FM signals Cb and Cr are successively extracted. And this signal Cb, Cr
are supplied to the color demodulation circuits 6B and 6R to produce blue and red color difference signals Sb and Sr as shown in FIG. 2H and I.
are demodulated and taken out through amplifiers 7B and 7R.

However, in this case, when the phase of the signal S ₁₄ is reversed (when the state of "1" and the state of "0" are reversed), the switching phase of the switch circuit 4 is reversed, so that the signal S14 is output from the switch circuit 4. The signal Cb is supplied to the demodulation circuit 6R, and the signal Cr is supplied to the demodulation circuit 6B, which makes it impossible to perform correct color demodulation.

Therefore, when the phase of the signal _S14 is reversed, a circuit that corrects it to the correct phase is configured as follows.

That is, the demodulation characteristic of the demodulation circuit 6B is defined by a straight line 100B in FIG. 4, and the demodulation characteristic of the demodulation circuit 6R is defined by a straight line 100R. and,
The signals Sb and Sr from the demodulation circuits 6B and 6R are supplied to the adder circuit 21, and the added signal _S21 is supplied to the sampling hold circuit 22, and the horizontal synchronizing pulse Ph is sent to the shaping circuit 24 through the terminal 23.
is supplied to the discrimination signal as shown in Fig. 2K.
A pulse P ₂₄ which is "1" only during the first half of Db and Dr is formed, and this pulse P ₂₄ is supplied to the sampling hold circuit 22 as its control signal.

Then, the output signal S ₂₂ of this sampling hold circuit 22 is sent to the comparison circuit 25 and the integration circuit 26.
is supplied to This comparison circuit 25 includes transistors _Q51 to _Q55 and a capacitor _C51 , and uses transistors _Q51 and _Q52 as _a constant current source.
are differentially connected, and current mirror connected transistors Q ₅₄ and Q ₅₅ are connected to them, and a capacitor C ₅₁ is connected to the collector of transistor Q ₅₅ .
is connected. And the signal to transistor Q ₅₁
S ₂₂ is supplied, and the output signal of the integrating circuit 26 is supplied to the transistor Q ₅₂ . Furthermore, as shown in FIG. 2M, a signal ₁₄ having an opposite phase to the signal S14 is taken out from the flip-flop circuit ₁₄ and supplied to the transistor _Q53 .

Further, a capacitor C ₅₁ is connected to the non-inverting input terminal of the voltage comparison circuit, in this example, the differential amplifier 27, and a clamping diode D 81 and a clamping diode D ₈₁ are connected between the capacitor C ₅₁ and the inverting input terminal of the amplifier 27. DC bias source E ₈₁ is connected in series, and amplifier 27
A DC bias source E ₈₂ is connected to the inverting input terminal of. The output signal _S27 of the amplifier 27 is then supplied to the flip-flop circuit 14 through the OR circuit 13.

Therefore, when the phase of the signal S ₁₅ is correct, that is, when the switching phase of the switch circuit 4 is correct, the output signal S ₂₁ of the adder circuit 21 is as shown in FIG.
Since this signal S ₂₁ is sampled and held by the pulse P ₂₄ (K in FIG. 2) in the sampling and hold circuit 22, the output signal S ₂₂ becomes as shown in FIG. 2L. Then, this signal S ₂₂ is averaged in an integrating circuit 26 to obtain a voltage E ₂₆ at the average level of the signal S ₂₂ , as shown by the broken line in FIG. 2L.

Therefore, assuming that transistor Q ₅₃ is always on, when S ₂₂ > E ₂₆ , transistor Q ₅₁ is on, transistor Q ₅₂ is off, and transistor Q ₅₁ is on, so that transistor Q ₅₄ , Q ₅₅ is turned on, so a charging current I ₅₁ flows into the capacitor C ₅₁ , while when S ₂₂ < E ₂₆ ,
Since transistors Q ₅₁ , Q ₅₄ , and Q ₅₅ are turned off and transistor Q ₅₂ is turned on, discharge current I ₅₁ flows out from capacitor C ₅₁ . And the transistor Q ₅₃ is
It turns on when ₁₄ = “1” (M in Figure 2), so
If the polarity with which the current I ₅₁ charges the capacitor C ₅₁ is positive, the current I ₅₁ becomes as shown in FIG. 2 N.

In this FIG. 2N, the current discharged from the capacitor C ₅₁ is larger on average, so the terminal voltage E ₅₁ of the capacitor C ₅₁ is changed from the power source E ₈₁ , as shown in FIG. E ₈₂ difference voltage (E ₈₂ −
E ₈₁ ) (ignoring the voltage drop across diode D ₈₁ ).

Therefore, the output signal _S27 of the amplifier 27 is as shown in FIG.
Since the signal _S27 is "0" _as shown in FIG.
_S14 is inverted every horizontal period with the correct phase, or the switch circuit 4 is also switched every horizontal period with the correct phase.

That is, if the switching phase of the switch circuit 4 is correct, that state continues.

However, if the phase of the signal _S14 is reversed due to noise or the like, and therefore the switching phase of the switch circuit 4 is reversed, the operation shown in FIG. 3 is performed and the original correct phase is restored at time _t1 . Corrected.

That is, in this case, the signal Cr is supplied to the demodulation circuit 6B, the signal Cb is supplied to the demodulation circuit 6R, and the demodulation characteristics of the demodulation circuits 6B and 6R are set to the characteristics 100B and 100R in FIG. Therefore, the signal shown in FIG. 3H is output from the demodulation circuit 6B.
Sb is extracted from the demodulation circuit 6R as shown in FIG.
A signal Sr shown in is extracted. Therefore, the current I ₅₁
is as shown in FIG. 3N, and since the current charging the capacitor C ₅₁ is larger on average, the terminal voltage E ₅₁ of the capacitor C ₅₁ increases as shown in FIG. 3O.

Then, when E ₅₁ ≧ E ₈₂ , the output of the amplifier 27 becomes "1", which triggers the flip-flop circuit 14, and henceforth, the signal
The phase of _S14 becomes correct, and thereby the switching phase of the switch circuit 4 also becomes correct.

Thus, according to this circuit, the switch circuit 4
When the switching phase of The higher the value, the better. In order to achieve this, E ₅₁ ≧ E ₈₂ needs to be satisfied as soon as possible, so it is possible to reduce the capacitance of capacitor C ₅₁ , lower voltage E ₈₁ , or increase the absolute value of current I ₅₁ . Bye.

However, this method shortens the time until correction, but in a weak electric field, noise causes S ₂₇
= "1", and as a result, the switch circuit 4 malfunctions. In other words, in the above cases, the voltage E ₈₂ is relatively lowered. On the other hand, the level of the voltage E ₅₁ rises and falls for each horizontal period due to noise, so correct operation is not possible. Even if S ₂₇ is performed, S 27 becomes “1” and signal S ₁₄
The phase of the switch circuit 4 may be reversed, and the switching phase of the switch circuit 4 may be reversed.

In view of these points, the present invention aims to provide a correction circuit that takes a short time to correct when the switching phase of the switch circuit 4 is reversed and is stable against noise. .

Therefore, in the present invention, the received electric field level is detected, and the voltage E ₈₂ or the current I ₅₁ is changed based on this detection signal, thereby lengthening the time until the correction is made in the case of a weak electric field, thereby improving noise resistance. It was designed to improve.

Let's explain one example below.

In the example shown in FIG. 5, the voltage E ₈₂ is changed by using the color killer voltage as a detection signal of the received electric field level.

That is, transistors Q ₅₆ and Q ₅₇ are connected to transistors Q ₅₁ and Q ₅₄ in the same way as transistors Q ₅₂ and Q ₅₅ , and a capacitor C having a sufficiently larger capacity than capacitor C ₅₁ is connected to the collector of transistor Q ₅₆ . ₅₂ are connected. A resistor R ₈₁ is connected between this capacitor C ₅₂ and a DC bias power source E ₈₄ , and the capacitor C ₅₂ is connected to the inverting input terminal of the amplifier 27 . Note that the DC bias power supply (voltage) _E83 is _E83 = _E82 - _E81 .

In addition, capacitor _C52 is connected to the DC bias power supply.
Voltage comparator circuit, e.g. differential amplifier 2 through _E85
9 and the power supply E ₈₄
is connected to the inverting input terminal of amplifier 29, and amplifier 2
The output signal of 9 is supplied to amplifiers 7B and 7R as a color killer signal.

According to such a configuration, a current similar to the current I ₅₁ of capacitor C ₅₁ also flows through capacitor C ₅₂ , so that the terminal voltage E ₅₂ of capacitor C ₅₂ is
The terminal voltage of C ₅₁ changes similarly to E ₅₁ , but in this case
Since C ₅₂ >>C ₅₁ , the variation width of the voltage E ₅₂ is smaller than that of the voltage E ₅₁ , as shown in FIG. 2O and FIG. 3O.

If the phase of the signal S ₁₄ is correct and the switching phase of the switch circuit 4 is correct (in the case of Fig. 2), then the on period of the transistor Q ₅₇ (period of I ₅₁ > 0 in N in Fig. 2) Since the on period of transistor Q ₅₆ (period when I ₅₁ < 0) is longer, on average, power supply E ₈₄ → resistor R ₈₁ → transistor Q ₅₆
Current will flow through the capacitor line.
The terminal voltage E ₅₂ of C ₅₂ has a value lower than the voltage E ₈₄ by the voltage drop across the resistor R ₈₁ (FIG. 2 O).

And in this case, since E ₅₂ > E ₅₁ , S ₂₇
= "0", the flip-flop circuit 14 is not triggered, and therefore the switching phase of the switch circuit 4 remains correct.

On the other hand, when the phase of the signal S ₁₄ is reversed and the switching phase of the switch circuit 4 is reversed (as in the case of FIG. 3), the on period of the transistor Q ₅₇ is longer than the on period of the transistor Q ₅₆ , so that On average, capacitor C ₅₂ is charged and its terminal voltage E ₅₂ increases (Fig. 3O). And at time t ₁ E ₅₁
When ≧E ₅₂ , S ₂₇ becomes “1”, the flip-flop circuit 14 is triggered, and the switching phase of the switch circuit 4 is brought to the correct state.

In this case, as the received electric field level decreases, the noise level with respect to the signal S ₂₂ increases, and therefore the level of the voltage E ₅₁ fluctuates up and down significantly every horizontal period due to the noise. but,
Since the voltage E ₅₂ is the voltage obtained across the large-capacity capacitor C ₅₂ , it remains almost constant even in the presence of noise.
At this time, as the level of the signal S ₂₂ becomes smaller, the current flowing through the transistor Q ₅₆ when the transistor Q ₅₆ is on becomes smaller, so the voltage drop across the resistor R ₈₁ becomes smaller, and therefore, Voltage E ₅₂ is rising. That is, when the received electric field level is small, the level of voltage E ₅₁ fluctuates greatly due to noise, but the level of voltage E ₅₂ increases.

Therefore, even if the level of voltage E ₅₁ increases due to noise, E ₅₁ ≧ E ₅₂ will not be satisfied, and S ₂₇ will not become “1” due to noise. The phase of the signal is not reversed to the wrong state.

In this way, even if the received electric field level is small, the switching phase of the switch circuit 4 will not be reversed to an incorrect state. time can be shortened.

In addition, when the received electric field level is extremely low and color reproduction is not suitable, or when receiving black and white broadcasts,
Since the voltage drop across resistor R ₈₁ becomes even smaller,
The non-inverting input of the amplifier 29 becomes larger than the inverting input, and its output signal becomes "1", whereby color killer is performed by the amplifiers 7B and 7R.

Thus, according to the invention, the switch circuit 4
Even if the phase of switching is incorrect, the time until it is corrected is short, and there is no malfunction due to noise even when the received electric field level is small.

FIG. 6 shows a specific connection example of the circuit in FIG. 5. A voltage E ₈₃ is formed by the resistors R ₃₁ to R ₃₃ , and this voltage E ₈₃ is supplied to the base of the transistor Q ₃₁ . At the same time, its emitter becomes a capacitor.
Connected to C ₅₁ . Therefore, the area between the base and emitter of transistor _Q31 corresponds to diode _D81 .

Further, a voltage E ₈₄ is formed by the transistor Q ₄₁ and the diode D ₄₁ .

Furthermore, a transistor Q ₇₁ is used as a comparison circuit 27.
is provided, its emitter is supplied with a voltage E ₅₁ , its base is supplied with a voltage E ₅₂ , and
Transistor Q ₇₂ in the positive feedback path of transistor Q ₇₁
is connected so that the signal _S27 rises rapidly due to positive feedback. Then, the horizontal pulse Pf is supplied to the wave rectifying circuit _{31 to form the pulse P 31 shown} in FIG. _2Q and _FIG . will be reset to

In these examples, a color killer voltage is used, but a signal indicating the level of a carrier color signal or a color difference signal may also be used.

[Brief explanation of the drawing]

Figure 1 is a system diagram for explaining this invention, Figures 2 to 4 are diagrams for explaining this invention, Figure 5 is a system diagram for an example of this invention, and Figure 6 is a system diagram for explaining this invention. It is an example connection diagram. 5 is a delay circuit, 6B and 6R are color demodulation circuits, 14
2 is a flip-flop circuit, and 22 is a sampling and holding circuit.

Claims (1)

[Claims] 1 A first FM demodulator that demodulates a first color difference signal from a carrier color signal of the SECSM system, a second FM demodulator that demodulates a second color difference signal from the carrier color signal, and a delay circuit that delays by one horizontal period; a switch circuit that alternately selects the delayed carrier color signal and the carrier color signal to obtain continuous first and second color difference signals; In the SECAM signal demodulation circuit, the SECAM signal demodulation circuit has a signal path for supplying the FM demodulator to the FM demodulator, and a correction circuit that controls the switching phase of the switch circuit and corrects it when the switching phase deviates from the normal one.
A detection circuit is provided for detecting the output level of the non-modulated discrimination signal portion in the carrier color signal from the output of the demodulator, and this output is compared with a reference level by a comparison circuit,
A control circuit is provided which controls the correction circuit with the output of the comparator and changes the reference level according to the received electric field level, thereby weakening the detection sensitivity of the correction circuit when the electric field level is small. A correction circuit for a SECAM signal demodulation circuit characterized by: