JPS6155693B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system, and more specifically, provides a system for efficiently processing machine language instructions using a microprogram.

In general, microprogram-controlled computers require (1) retrieval of machine language instructions from main memory; (2)
Generates the start address of the corresponding microprogram routine from a machine language instruction. (3) Retrieval of microinstructions from control memory. There are four processes: (4) Execution of microinstructions. When executing one machine language instruction, steps (1), (2), (3), and (4) usually take separate machine cycles, and each process takes one machine cycle. Simply calculated, it would require at least four machine cycles to execute this machine language instruction. Therefore, in order to reduce the number of machine cycles for one machine language instruction to less than this, processes (1), (2), (3) and (4) above are processed in parallel,
It is necessary to reduce the effective execution time.

Furthermore, the execution process of a single machine language instruction may be as simple as the four processes described above being performed once in sequence, but in order to execute a complex and highly functional machine language instruction, a large number of microprogram routines are required. In many cases, it is necessary to execute the above process (1) only once for one machine language instruction, but (2),
Processes (3) and (4) are repeated multiple times. This will be explained using a flowchart.

FIG. 1 shows the flow of executing machine language instructions I1, I2, and I3. In Figure 1, A, B, C, E, and O are respectively
Corresponds to process (1), process (2), process (3) and (4), process (2), process (3) and (4). Also, A,
B, C and D indicate the types of microprogram routines.

In FIG. 1, an arithmetic processing unit (hereinafter referred to as CPU) executes microprogram routines A and C for machine language instruction I1, executes A and D for I2, and executes microprogram routines A and D for I3. Well,
Execute B and move on to processing the next instruction. As is clear from this, in a machine language instruction such as I1 that executes a plurality of microprogram routines, it is necessary to generate the start addresses of the plurality of microprogram routines from one machine language instruction. Therefore, in the process of executing I1, it is necessary to generate the start address of microprogram routine C when the execution of microprogram routine A is finished, so machine language instruction I1 needs to be held. Yes, it is not possible to read new machine language instructions. In this way, since there are microprogram routines that proceed to read machine language instructions and other microprogram routines that do not proceed, information on whether or not to read machine language instructions is required, and this information is
Generally given by microinstructions.

However, such a method has a drawback in that the next machine language instruction to be processed cannot be read unless a microinstruction having this information is executed.

The earlier you can obtain information on whether or not to read a machine language instruction, the earlier you can start preparing the next machine language instruction to be processed.
Efficient processing becomes possible.

Hereinafter, based on the above-mentioned purpose, a conventional example in which the number of machine cycles is shortened will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of a microprogram controlled computer. In FIG. 2, 201 is a CPU, 202 is a main storage device, and 20
3 is a data bus. In the CPU 201,
204 is the CPU 201 via the data bus 203
205 is a register (hereinafter referred to as IR) that holds machine language instructions, and 206 is a microprogram routine corresponding to machine language instructions. A programmable logic array (hereinafter referred to as PLA) is used to generate the start address, and 207 is a register (hereinafter referred to as PLA) that holds a micro address.
It is written as RAR. ), 208 is a control memory (hereinafter referred to as CROM) that stores a microprogram, 209 is a register that holds microinstructions (hereinafter referred to as MIR), 210 is a microinstruction decoder, and 211 is a general-purpose register. This is an arithmetic control section that includes In the explanation of FIG. 1, the signal line 212 is an information transmission path for determining whether or not to proceed to reading a machine language instruction, and the signal line 212 is an information transmission path for determining whether or not to proceed to reading a machine language instruction. IR20
Transfer to 5. That is, it is used as a starting signal for the operation to perform the process (1).

The operation of the system shown in FIG. 2 will be explained with reference to the timing chart shown in FIG. FIG. 3 shows the operation when a machine language instruction such as I3 shown in FIG. 1 is processed by the system shown in FIG. 31, 32, 33 and 3 in Figure 3.
4 corresponds to the steps (1), (2), (3) and (4) above, respectively. Furthermore, broken lines indicate machine cycle divisions. The above (1), that is, the process A1 in FIG.
This corresponds to reading machine language instructions from the main storage device 202 by the input control unit 204 and holding them in the IR 205 . The above (2), that is, the process of A2, is
The contents of IR205 are input to PLA206, and PLA
206 generates the start address of the microprogram corresponding to the machine language instruction held in the IR 205, and this information is stored in the RAR 207. RAR207 has PLA2
In addition to the output of PLA 206, the value of the contents of RAR 207 plus 1 can be stored, and the output of PLA 206 is selected and held in the process of generating the start address of a microprogram routine from a machine language instruction. The above (3), that is, the process of A3, is RAR20
It corresponds to the micro address held in 7.
This corresponds to the fact that the contents of the CROM 208 are held in the MIR 209. The process (4), ie, A4, corresponds to the fact that the content of the MIR 209 becomes a control signal for each section by the decoder 210, and the arithmetic control 211 is controlled. Further, in the process of A4, a signal 212 is supplied from the microinstruction, and a new machine language instruction, ie, B1, is simultaneously read out. Similarly, the processing of the machine language instruction read out in B1 progresses through B2, B3, and B4, and in the process of B4, a new machine language instruction in C1 is simultaneously read out.

The above is an overview of the operation of the system shown in Figure 2.
As shown in FIG. 3, the steps (1) and (4) are processed in parallel, so that the effective number of machine cycles T for one machine language instruction is three.

The present invention makes it possible to process the steps (1) and (3), and the steps (2) and (4) in parallel by supplying the signal 212 from the PLA. The present invention provides a method for further reducing the effective number of machine cycles T for word instructions. An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing an example of a microprogram-controlled computer implementing the method of the present invention. In Figure 4, the numbers whose last two digits are the same as those in Figure 2 indicate that the signal 412 is the same as the number in Figure 2.
It shows a similar function except that it is output from PLA 406.

Figure 5 shows 405,406 of the system in Figure 4.
and 407 are detailed views of the portion 505,5
06 and 507 are 405, 406, 4 respectively
Corresponds to 07. The PLA 506 consists of an AND matrix 506a and an OR matrix 506b, and the contents held in the IR 505 are input to the AND matrix 506a, and the micro address and signal 512 corresponding to this input are output from the OR matrix 506b. Signal 512 corresponds to signal 412 in FIG. and matrix 506a
A bit pattern corresponding to each machine instruction is written in each row of the OR matrix 506b, and a microaddress corresponding to each row of the AND matrix 506a is written in each row of the OR matrix 506b, and the signal 512 is set to logic "1".
Information on whether or not to do so is written. PLA
506 is input content and AND matrix 506a
The contents of each row are compared, and only the row with the matching bit pattern is selected, and the contents of the same row of the OR matrix 506b are output. For example, if the information shown in Figure 5 is written in the PLA 506 and "1101" is held in the IR 505 as a machine language instruction, the line indicated by "A" will be selected and "010000" will be stored as the micro address. , "1" is output as the signal 512. here and matrix 5
The "X" in 06a indicates that the bit is not compared. If signal 512 is “1”, IR50
The operation to prepare a new command to 5 is activated and becomes “0”.
If it is defined that it will not be started in the case of , then in this case it is "1", so the operation of preparing a new instruction to the IR 505, that is, the machine language instruction is read from the main storage device 402 and held in the IR 405. The operation (1) above will be activated.

As shown in FIG. 2, in the conventional method, the signal 212 is output from the MIR 209, so the information path in the process from the machine language instruction to the generation of the signal 212 is 205 → 206 → 207 → 2.
08→209→212. In the method of the present invention shown in FIG. 4, the information path in the process from the machine language instruction to obtaining the signal 412 is 405→406.
→412, compared to the conventional method, 407→
The path from 408 to 409, that is, the process of reading out the microinstructions, is eliminated and the path is shortened. Also, the activation signal for preparing a new machine language instruction is not supplied from the MIR 209 like the signal 212 in FIG. 2, but from the PLA 406 like the signal 412 in FIG.
Therefore, the operation process of preparing a new machine language instruction to the IR 405 activated by the signal 412 and the process of reading the microinstruction, that is, the process of (1) and (3) above, are independent. That means you are doing it. Therefore, the process (1) and the process (3) can be processed in parallel. Furthermore, this makes it possible to process the process (2) following the process (1) and the process (4) following the process (3) in parallel. If the above is expressed in a timing chart, it is number 6.
It will look like the figure.

FIG. 6 shows the operation when a machine language instruction such as I3 shown in FIG. 1 is processed by the system shown in FIG. In Figure 6, 61,6
2, 63 and 64 correspond to the steps (1), (2), (3) and (4), respectively, as in the case of FIG.
Furthermore, broken lines indicate machine cycle divisions. In FIGS. 4 and 6, from main memory 402 to IR4
After reading A1 of the machine language instruction to 05, the micro address and signal 4 corresponding to the machine language instruction are read.
12 is generated by the PLA 406, and as a result, in the next cycle, machine language instruction reading B1 and microinstruction reading A3 are processed in parallel. Furthermore, in the next cycle, the microaddress and signal 412 corresponding to the machine language instruction read out at B1 are generated by the RLA 406 B2, and at the same time, the microinstruction read out at A3 is executed A4. Similarly, C1, B3, C
2 and B4 are processed in parallel. Therefore, the effective number of machine cycles T for one machine language instruction is 2, which is shorter than in the conventional system.

By implementing the method of the present invention as described above, efficient parallel processing can be realized and effective processing time can be shortened.

In the above explanation, the case where the start address of one microprogram routine is generated for one machine language instruction, such as I3 shown in FIG. 1, was used as an example, but I1 and I2 are The method of the present invention can be implemented even when the start addresses of a plurality of microprogram routines are generated for one machine language instruction as shown in FIG. In other words, "0" is written in the line that generates the start address of microprogram routine A as information on whether or not to read machine language instructions.
It is sufficient to write "1" in the lines for generating the start addresses of microprogram routines C and D.

As described above, the present invention generates the start address of a microprogram using a machine language instruction held in a register, and also generates a startup instruction to start data transfer from an input/output control unit to the register, and controls the input/output. By configuring the microaddress generator to directly output the microaddress to the microaddress generator, the execution time of machine language instructions can be shortened, which has a significant effect.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the flow of processing of machine language instructions, Fig. 2 is a block diagram showing an example of a conventional method, and Fig. 3 is an explanatory diagram for explaining the operation of the system shown in Fig. 2. , FIG. 4 is a block diagram showing the microprogram control method of the present invention, FIG. 5 is a block diagram for explaining a part of FIG. 4, and FIG. 6 is a block diagram for explaining the operation of the system shown in FIG. 4. FIG. 401...CPU, 402...Main storage device, 4
03...Data bus, 404...I/O control unit,
405,505...Register for holding machine language instructions, 406,506...Programmable logic array, 407,507...Register for holding micro addresses, 408...Control memory, 40
9...Register for holding microinstructions, 410
...Decoder, 411...Arithmetic control section, 412...
…Signal line.

Claims (1)

[Claims] 1. A register that holds machine language instructions, an input/output control unit that prepares data to be stored in the register, and generates the start address of a microprogram based on the machine language instructions held by the register, and also controls the input/output control. microaddress generation means for generating a start-up instruction to start data transfer from the unit to the register and directly outputting the start-up instruction to the input/output control unit; and a start address of the microprogram generated by the microaddress generation means. A microprogram control system comprising a microprogram storage means for outputting a microprogram.