JPS6155776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an insulating film.

The following explanation will be given by taking as an example a case where a multilayer wiring is formed using a silicon dioxide (SiO ₂ ) film formed by a CVD method (Chemical Vapor Deposition) method as an interlayer insulating film.

FIGS. 1a to 1d are longitudinal cross-sectional views of a wafer during main steps in a conventional method for forming multilayer wiring.
First, as shown in FIG. 1a, a first SiO ₂ film 2 is formed on a silicon (Si) substrate 1 by a known method,
A planar wiring consisting of a first layer of metal wiring 3 and an insulator 4 is formed thereon. Next, as shown in FIG. 1b, on the metal wiring 3 and insulator 4,
A second SiO ₂ film 5 is formed by CVD.
Subsequently, as shown in FIG. 1c, the SiO ₂ film 5 is selectively removed using a fluorine-based etching solution or a dry process such as gas plasma to form a through hole 6. Furthermore, as shown in FIG. 1d, a second layer of metal wiring 7 is formed on the second SiO ₂ film 5 and on the metal wiring 3 exposed in the through hole 6, and a second layer of metal wiring 7 is formed between the first layer of metal wiring 3 and the second layer of metal wiring 3. A multilayer wiring is obtained by connecting with the metal wiring 5 of the second layer. When a multilayer wiring is formed as described above, since there is a steep step at the through hole 6, the thickness of the metal wiring 7 becomes thinner at that part.
The metal wiring 7 had a defect that caused a disconnection.

The present invention has been made in order to eliminate such drawbacks, and by making the side wall of the through hole slope so that the opening of the through hole becomes smaller from the surface of the silicon oxide film toward the inside, the silicon oxide film It is an object of the present invention to provide a novel method for manufacturing a semiconductor device that can prevent disconnection of metal wiring formed on the oxide film and in the through hole.

The present invention involves growing a silicon oxide film in a vapor phase by increasing the flow rate ratio of oxygen or an oxygen compound to a silicon compound, and growing the silicon oxide film in a vapor phase in order to slope the side wall of a through hole formed in a silicon oxide film. A silicon oxide film is formed by increasing the molar concentration of phosphorus or boron contained in the film during the vapor phase growth, and the silicon oxide film thus formed is selectively removed by CF ₄ gas plasma. As a result, the side walls of the through holes formed in the silicon oxide film are made to have an inclination.

As a result, the surface area of the silicon oxide film
Since the etching rate by CF ₄ gas plasma is higher than the etching rate inside the silicon oxide film, the side wall of the through hole is sloped so that the opening of the through hole becomes smaller from the surface of the silicon oxide film toward the inside. Therefore, disconnection of the metal wiring can be prevented.

An embodiment of the present invention will be described below with reference to the drawings.

First, the experimental results that are the basis of this invention will be briefly explained. _N2 as carrier gas,
Taking the case where a silicon oxide film is formed using SiH ₄ and N ₂ O gas as an example, the flow rate ratio of N ₂ O gas to SiH ₄ , that is, N ₂ O/SiH ₄ , is varied in the range of 8 to 350. In this case, the etching rate of the formed silicon oxide film by the etching solution is 350 to 1150 Å/mn.
It varied within the range. Also, as shown in Figure 2,
When the molar concentration of phosphorus in the silicon oxide film was varied in the range of 0 to 10%, the etching rate by CF ₄ gas plasma was varied in the range of 200 to 500 Å/min.

An embodiment of the present invention in which the above experimental results are applied to the formation of multilayer wiring will be described with reference to FIG. 3A to 3D are longitudinal cross-sectional views of the wafer in the main steps of the above embodiment. First, the third
As shown in figure a, a first SiO ₂ film 2 is deposited on a Si substrate 1.
A planar wiring consisting of a first layer of metal wiring 3 and an insulator 4 is formed thereon. This step is the same as the conventional method. Next, as shown in FIG. 3b, when growing a second SiO ₂ film 5a as a wiring interlayer insulating film by CVD method, SiH ₄
The flow rate of N 2 O gas to SiH 4 is kept constant in the range of 1.5 to 2.0 cc/min, that is, the flow rate ratio of N ₂ O gas to SiH ₄ is
The flow rate of N ₂ O is gradually increased so that N ₂ O/SiH ₄ is changed within the range of 8 to 350, and the molar concentration of phosphorus contained in the silicon oxide film 5a is gradually increased from 0% to 10%. increase.

In this case, if it is difficult to continuously change the N ₂ O flow rate or phosphorus flow rate due to equipment constraints, you can also change it stepwise.
You can reach your goal. Next, as shown in FIG. 3c, a predetermined portion of the silicon oxide film 5a is covered with _CF4.
When removed using gas plasma, the etching rate increases toward the surface of the silicon oxide film 5a, forming a through hole 6a having a side wall with a gentle slope from the surface of the silicon oxide film 5a inward. be done.

Therefore, when the second layer of metal wiring 7a is formed as shown in FIG. Since no thin portion occurs, disconnection of the metal wiring 7a at the through hole 6a can be prevented.

Here, changing the flow rate ratio of N ₂ O to SiH ₄ corresponds to changing the O/Si ratio, and while increasing the O/Si ratio continuously from 0.5 to 2.0, the phosphorus concentration Forming a silicon oxide film by continuously increasing from 0 mol% to 10 mol%,
When the silicon oxide film is then etched by CF ₄ gas plasma, the CF ₄ plasma etching rate changes as shown by the solid line in FIG.

As is clear from this Figure 4, the CF ₄ plasma etching rate is approximately 40 Å/min to approximately 500 Å/min.
It can be seen that the amount increases by approximately 10 times.

The dotted line in FIG. 4 indicates the CF ₄ plasma etching rate when the O/Si ratio is increased at a phosphorus concentration of 0 mol %.

In this way, when a silicon oxide film is formed by the above method, the surface area of this silicon oxide film becomes
It becomes _a substance similar to silicon, such as SiO _0.5 , and the surface part becomes a substance similar to silicon dioxide, such as SiO ₂ .

This means that the presence of O ₂ decreases from the surface of the silicon oxide film toward the inside, and therefore the reaction rate decreases.

On the other hand, the reaction between the silicon oxide film and the CF ₄ gas plasma proceeds as follows: CF ₄ →C+4F ^* SiO ₂ +4F ^* →SiO ₂ +O ₂ (F ^* is an activated fluorine ion) .

Since the reaction rate between 4F ^* and SiO ₂ is approximately equal to the etching rate, the etching rate on the surface of the silicon oxide film is higher than on the inside.

Thus, by the above method, the side wall of the through hole can be sloped so that the opening of the through hole becomes smaller from the surface of the silicon oxide film toward the inside.

In the above explanation, we took as an example a silicon oxide film obtained using SiH ₄ and N ₂ O gas system, but it is not necessarily limited to this gas composition, and can be formed by appropriately selecting the generation temperature and gas flow rate ratio. Other reactive gas systems, i.e. SiCl ₄ , BiHCl ₃ or SiH ₂ Cl ₂ instead of SiH ₄ as silicon compounds or O ₂ , H ₂ O, CO ₂ or NO ₂ instead of N ₂ O as oxygen compounds
It can also be applied to gas systems composed of etc.

Also, when boron is applied instead of phosphorus,
The same effects as in the above embodiment can be achieved.

Furthermore, in the above embodiment, a case was described in which an interlayer insulating film of multilayer wiring was formed, but a mask for selective diffusion of impurities in the manufacture of semiconductor devices,
By manufacturing the surface protection insulating film after the metal wiring by the method of the present invention, it is possible to form windows with gently sloped side walls.

As explained above, according to the present invention, the surface portion of the silicon oxide film has a higher etching rate than the inside, so when a through hole is formed in the silicon oxide film and a metal wiring is provided on the through hole, the metal wiring is etched. Disconnection can be effectively prevented.

[Brief explanation of the drawing]

Figures 1a to d are longitudinal cross-sectional views of a wafer during the main steps of a conventional method for forming multilayer wiring, and Figure 2 is a diagram showing the relationship between the molar concentration of phosphorus in the silicon oxide film.
Correlation diagram showing the correlation between the etching rate of this silicon oxide film by CF ₄ gas plasma, Figures 3a to d
4 is a vertical cross-sectional view of a wafer in the main steps of the method of one embodiment of the present invention for forming multilayer wiring, and FIG.
When the Si ratio is changed continuously from 0.5 to 2.0
FIG. 3 is a characteristic diagram showing changes in CF ₄ plasma etching rate. In the figure, 1 is a Si substrate (semiconductor substrate), 2 is a first SiO ₂ film, 3 is a first layer of metal wiring (conductive layer), 4 is an insulator, 5 and 5a are silicon oxide films,
6 and 6a are through holes, and 7 and 7a are second layer metal wiring. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. Growing a silicon oxide film in vapor phase by increasing the flow rate ratio of oxygen or oxygen compound to silicon compound, and increasing the molar concentration of phosphorus or boron contained in this silicon oxide film along with the vapor phase growth. forming a silicon oxide film; selectively removing the silicon oxide film using _{CF 4} gas plasma to form a through hole in the silicon oxide film; A method of manufacturing a semiconductor device, characterized in that the side wall of the through hole is inclined so that the opening of the through hole becomes smaller from the surface of the silicon oxide film toward the inside.