JPS6156473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch with a timer, and more particularly to an electronic watch with a timer that can be used any number of times once a timer time has been set and has a repeatable timer function.

Generally, a timer function is used to notify the user of the arrival of an arbitrary time after the current time by means of sound, etc., but in order to operate the timer, the timer time must be set. With the conventional timer function, when the same timer time is used many times or when the timer is operated repeatedly, the timer time must be corrected each time, making it extremely difficult to use.

The present application has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide an electronic timer with a timer that eliminates the drawbacks of the conventional timer by storing the set timer time in a memory circuit. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

1 is a crystal oscillation circuit that generates a reference signal; 2 is a frequency dividing circuit that divides the reference signal to obtain a 1Hz second signal;
3, 4, and 5 are second counters, minute counters, and hour counters that are connected in series to obtain the time by counting second signals, and 6 and 7 are second counters that constitute a timer and consist of a down counter that subtracts and counts the second signals. 8 is a memory circuit for storing the contents of the minute counter 7; 9, 10, 11, 12, and 13 are a common line 14 for storing the count contents of each counter 3, 4, 5, 6, and 7;
15 is a decoder for decoding the signal sent to the common line 14; 16 is a display device comprising a liquid crystal or the like and performing digital display based on the output of the decoder 15; Further, 17 is connected to switches SW ₁ , SW ₂ , and SW ₃ , and these switches are connected to each other.
A mode selection circuit that selects a mode by opening and closing SW ₁ , SW ₂ , and SW ₃ ; 18 a control circuit that controls timer counters 6 and 7 and a memory circuit 8; 19 a control circuit that controls when counters 6 and 7 reach zero; 20 is a zero detection circuit for detecting the temperature, and a sound generation circuit.

The count contents of the second counter 3, minute counter 4, and hour counter 5, which count the 1Hz second signal obtained by the crystal oscillation circuit 1 and the frequency divider circuit 2, are normal, that is, when the switches SW ₁ , SW ₂ and SW ₃ are If not closed,
The gates 9, 10 and 11 are opened in response to the signal MD ₂ outputted from the mode selection circuit 17, which is sent to the decoder 15 in a time-division manner via the common line 14 and digitally displayed on the display device 16. Also, the signal MD ₁ from the mode selection circuit 17 is sent to the gates 12, 1.
3 and the control circuit 18, normally the gates 12 and 13 are closed, and the counters 6 and 7 are connected to the control circuit 18.
It is prohibited to send the contents of the file to the common line 14.

Switch SW ₁ is a switch for selecting current time display mode, timer display mode, time correction mode, or although not shown in Fig. ₁ , day of the week display mode, alarm time display, setting mode, etc. This is a switch that instructs the correction digit in the correction mode or when setting the alarm time, and also switches to the timer correction mode in the timer display mode. Switch SW ₃ is used to start and stop the timer operation, and to control the timer operation in each correction mode. Depending on the opening and closing of these switches SW ₁ , SW ₂ and SW ₃ , various signals are output from the mode selection circuit 17 to control each circuit. (In FIG. 1, signals and circuits other than those related to the timer are omitted.) The control circuit 18 controls the second counter 6, minute counter 7, and memory circuit 8 that constitute the timer. It outputs control signals S ₁ , S ₂ , S ₃ and S ₄ depending on the applied signals.
The storage circuit 8 is connected to the minute counter 7 by a line 21 and is used to store the contents of the minute counter 7 or to transfer the stored contents to the minute counter 7. The second signal from the frequency divider circuit 2 is input to the second counter 6.
The signal is applied via a NOR gate 22 and an inverter 23, and the timer is started and stopped by opening and closing the NOR gate 22 with the signal _S1 . Further, the output of the second counter 6 and the signal S ₄ are applied to the minute counter 7 via an OR gate 24, and the signal S ₄ is used to correct the minute counter 7.

On the other hand, the zero detection circuit 19 receives the count contents of the second counter 6 and the minute counter 7, detects that the count contents have become zero by counting down the second signal, and sends a signal. Output DT ₄ . The signal DT ₄ is applied to the sound generation circuit 20, and the sound generation circuit 20 notifies the user by sound that a preset time has elapsed. At the same time, the signal DT ₄ is also applied to the control circuit 18, and unless the timer operation is stopped, the contents of the memory circuit 8 are transferred to the minute counter 7 according to the signal S ₃ and the timer operation is repeated.

Switch in normal state, that is, time display mode.
When SW ₁ is closed once, the signal MD ₂ output from the mode selection circuit 17 changes from the “1” level to “0”.
To reach the level, gates 9, 10, 11 are blocked and the contents of counters 3, 4, 5 are transferred to the common line 14.
It will no longer be transmitted and the time display will disappear. At the same time, the signal MD ₁ output from the mode selection circuit 17 changes from the "0" level to the "1" level and the gate 1
2 and 13 are opened, and the contents of a second counter 6 and a minute counter 7, which are down counters for timers, are transmitted to a common line 14 in a time-division manner and displayed on a display device 16. At this time, if the timer is operating, the operating timer time is displayed, but if the timer is stopped, signals S ₂ and S ₃ are output from the control circuit 18, the second counter 6 is reset, and the minute counter 7 is The contents stored in the storage circuit 8 are transferred. Therefore, the display will be the transferred content.

When the timer operation is stopped in the timer display mode, when the switch SW ₃ is closed, the signal DT ₁ is output from the mode selection circuit 17 and the control circuit 1
8 outputs a signal _S1 depending on this signal _DT1 . The signal S ₁ opens the NOR gate 22 so that the second signal is
The signal is applied to the second counter 6 through the NOR gate 22 and the inverter 23, and the second counter 6 and the minute counter 7 start counting down and enter timer operation. When the second counter 6 and the minute counter 7 reach zero, the zero detection circuit 19 outputs the signal DT ₄ , the sound generation circuit 20 generates sound for a certain period of time, and the signal DT ₄ is output.
Signals S ₂ and S ₃ are output from the control circuit 18 to which is applied, the second counter 6 is reset and the contents of the memory circuit 8 are transferred to the minute counter 7, and the timer operation for the same time is started again. . On the other hand, stopping the timer operation is accomplished by closing switch _SW3 , and signal _S1 from control circuit 18 closes NOR gate 22, cutting off the seconds signal.

Close switch SW ₁ to set the timer display mode, and close switch SW ₂ to switch to mode selection circuit 1.
The signal DT ₅ is output from 7 to enter the timer time correction mode, and by closing the switch SW ₃ , a pulse corresponding to the number of times it is closed, or a continuous pulse by continuing to close the switch SW 3. is output as control signals S ₄ and S ₂ . This signal S ₄ is OR
The signal S 2 is applied to the gate 24 and the memory circuit 8, and the minute counter 7 is subtracted and corrected through the OR gate 24, and the content of the correction of the minute counter 7 is stored in the memory circuit 8 for each correction pulse _. The pulse resets the seconds counter 6. Therefore, the timer time can be adjusted arbitrarily in minutes, and the time can be used any number of times until it is adjusted again.

On the other hand, when the switch SW ₂ is closed and then the switch SW ₃ is closed while the timer is operating, the control circuit 18 outputs a pulse only to the signal S ₄ , and the second counter 6
is not reset but a subtractive count is performed, and only the minute counter 7 can be corrected, and in this case as well, the contents of the minute counter 7 are stored in the storage circuit 8.

Further, when the switch SW ₁ is closed and the timer display mode is entered, and a certain period of time has elapsed without any other switches being closed, the mode selection circuit 17 automatically sets the signal MD ₁ to "0" and changes the signal MD ₂ to "0". “1”
The mode is switched to the time display mode.
Furthermore, the mode selection circuit 17 selects the control circuit 1 when the timer is operating or when the timer correction mode is entered.
Depending on the signal DT ₂ output from 8, switch SW ₁
When opened or closed, it returns to time display mode without switching to the next mode.

FIG. 2 is a logic circuit diagram of the control circuit 18 in the block diagram shown in FIG. 1, in which 25 is a flip-flop that controls the start and stop of the timer, 26 is a flip-flop composed of NAND gates 27 and 28, 29, 30 are AND gates, 31, 32, 33, 34 are NOR gates, 3
5 and 36 are NAND gates, and 37 is a latch circuit.

The signal MD ₁ indicating the timer display mode is
It controls the opening and closing of the AND gate 29 and the NAND gate 25, and also controls the opening and closing of the NAND gate 29 of the flip-flop 26.
8. Flip-flop 26 is a signal
It is set or reset depending on the output of the NOR gate 31 applied to MD ₁ and the NAND gate 27, and the output of the flip-flop 26 is applied as a signal DT ₂ to the mode selection circuit 17, and this signal DT ₂ is output. switch when
Close SW ₁ to enter time display mode. NOR
A signal DT ₅ indicating the timer time correction mode is applied to the gate 31 . A signal applied to the output of the AND gate 29 and the input of the flip-flop 25 .
DT ₁ and output Q are applied.

The output Q of the flip-flop 25 is further applied to the NOR gate 33, and a signal DT ₃ is output from the mode selection circuit 17 when the mode is shifted to the timer display mode.
control. Further, the output of the flip-flop 25 is outputted as a signal _S1 which controls the NAND gate 35 and the start and stop of the timer operation.

The NAND gate 35 is the output of the AND gate 30 to which the modified pulse SET is applied, i.e. the minute counter 7.
A signal S ₄ is further applied to perform the correction, and the output of the NAND gate 35 and the output of the NOR gate 32 become
It is outputted via the NAND gate 36 as a reset signal S2 for the second counter 6. On the other hand, the output of the NOR gate 33 and the output of the NOR gate 34 obtained by differentiating the signal of the detection circuit 19 using the latch circuit 37 and the NOR gate 34 are applied to the NOR gate 32. It is output as a signal _S3 that transfers the contents to the counter 7.

Next, the operation of the control circuit 18 shown in FIGS. 1 and 2 will be explained with reference to the timing chart shown in FIG. 3.

First, when the switch SW ₁ is closed in the time display mode (T ₁ in Fig. 3), the signal MD ₁ output from the mode selection circuit 17 changes from the "0" level to the "1" level, and the timer display mode is entered. At the same time, a "0" level pulse is output to the signal _DT3 . At this time, the flip-flop 25 is in the reset state, and its output is that Q is at the "0" level and (S ₁ ) is at the "1" level.
The output of the NOR gate 34 is at the "0" level, making the NOR gate 32 conductive. Therefore, signal DT ₃ is connected to NOR gate 33 and NOR
A pulse is generated through the gate 32 to bring the signal S ₃ to the "0" level, and a pulse is created through the NAND gate 36 to bring its output S ₂ to the "1" level. The second counter 6 is reset by the pulses of these signals S ₂ and S ₃ , and the contents previously stored in the memory circuit 8 are transferred to the minute counter 7 .

In this timer display mode, switch SW ₂
(T ₂ in Figure 3), the mode selection circuit 17
The signal DT ₅ outputted from the gate goes from the "0" level to the "1" level, and the AND gate 29 becomes conductive due to the signal MD ₁ being at the "1" level.
The output of is set to “1” level. The output "1" of the AND gate 29 makes the AND gate 30 conductive and also sets the flip-flop 26 via the NOR gate 31 to the set state. Therefore, the output DT ₂ of the flip-flop 26 changes from the "1" level to the "0" level and controls the mode selection circuit 17. On the other hand, the correction pulse SET applied to the AND gate 30 is a pulse that is output every time the switch SW ₃ is closed or a pulse that is output while the switch SW ₃ is closed.
0 to the NAND gate 35 and output as signal _S4 .

At this time, the NAND gate 35 is in a conductive state because the signal MD ₁ is at the "1" level and the flip-flop 25 is in the set state, and the applied correction pulse SET is outputted as the signal S ₂ through the NAND gate 35. Ru. Signals S ₂ and S ₄ therefore cause the second counter 6 to be reset and the minute counter 7 to be corrected and its contents to be stored. After the modification is completed, switch
When SW ₂ is closed again (T 3 in Figure ₃ ), the timer correction mode is canceled and the signal DT ₅ becomes "0".
AND gates 29 and 30 are blocked.

When the timer is to be operated, the switch SW ₃ is closed in the above-mentioned state, that is, in the timer display mode (T ₄ in FIG. 3). Then, the signal _DT1 from the mode selection circuit 17 becomes a pulse of "1" level, and the flip-flop 25 is set to the set state.
Therefore, the output of the flip-flop 25 goes to the "0" level and is output as the signal _S1 , making the NOR gate 22 to which the seconds signal is applied conductive, and causing the seconds counter 6 and minute counter 7 to start counting. On the other hand, the output Q of flip-flop 25 becomes "1".
Flip-flop 26 via NOR gate 31
However, since the flip-flop 26 is already in the set state when the timer correction mode is entered, it does not change. However, if the timer correction mode has not been entered, the timer will enter the set state at this point. If switch SW ₁ is closed here (T ₅ in Figure 3), it should normally move to the next mode, such as time adjustment mode, but flip-flop 26 is in the set state and output DT ₂ is at the "0" level. Since the mode selection circuit 17 is controlled, the next mode is not selected and the normal time display mode is set. Therefore, at this time, the signal MD ₁ goes to the "0" level, the flip-flop 26 is reset, and the signal DT ₂ goes to the "1" level.

Next, when the set time elapses and the second counter 6 and minute counter 7 reach zero (T6 in Figure ₃ ), the zero detection circuit 19 outputs a pulse that sets the signal _DT4 to the "1" level. The sound generation circuit 20 generates sound for a certain period of time to notify that the set time has elapsed. On the other hand, the signal DT ₄ is connected to the latch circuit 37 and the NOR gate 3.
4, and a pulse of "1" level is applied to the NOR gate 32. accordingly
The output of the NOR gate 32, ie, the signal _S3 , becomes a pulse of "0" level, and the output of the NAND gate 36, that is, the signal _S2 , becomes a pulse of "1" level. The second counter 6 is reset by the signals S ₂ and S ₃ , and the contents modified in the timer modification mode are transferred from the memory circuit 8 to the minute counter 7 . At this time, the flip-flop 25 is in the set state and the signal _S1 is "0", so the timer operation continues. If the timer is not stopped as it is, the timer operation will be repeated at the same timer time.

When the switch _SW1 for determining the remaining time is closed during the timer operation ( _T7 in FIG. 3), the signal _MD1 goes to the "1" level and the flip-flop 26 is set. At this time, a pulse that goes to the "0" level is output to the signal DT ₃ , but the flip-flop 25 is in the set state while the timer is operating, and the NOR gate 33 is cut off by its "1" level output Q. Therefore, the signals S ₂ and S ₃ do not change.

It is also possible to make corrections while the timer is running. In the above state, when the switch _S2 is closed ( _T8 in Figure 3), the signal _DT5 goes to the "1" level,
Due to the same operation as in the timer correction mode described above, a correction pulse corresponding to the number of opening/closing times or closing time of switch SW ₂ is output to signal S ₄ .
Since the "0" level output of the flip-flop 25 in the set state is applied to the NAND gate 35, the NAND gate 35 is in the cutoff state and no correction pulse is output as the signal _S2 . Therefore, the second counter 6 is not reset and continues to count down, and only the minute counter 7 is corrected and its contents are stored in the memory circuit 8. Further, when the switch SW ₂ is closed (T ₉ in FIG. 3), the signal DT ₅ goes to the "0" level, the timer correction mode is canceled, and the timer display mode is entered.

On the other hand, if the timer operation is to be stopped, switch SW ₃ is closed in the timer display mode (T ₁₀ in Figure 3). As a result, the signal _DT1 becomes a "1" level pulse, and the flip-flop 25 is reset. Therefore, the signal _S1 goes to the "1" level and the application of the second signal to the second counter 6 is cut off, so that the timer operation is stopped. In this state, flip-flop 26 is in the set state and the signal
DT ₂ is at the "0" level. Therefore, when the switch SW ₁ is next closed (T ₁₁ in FIG. 3), the mode selection circuit 17 selects the time display mode as described above, the signal MD ₁ goes to the "0" level, and the flip-flop 26 is reset. The signal DT ₂ goes to the "1" level and returns to the time display state in which no timer operation is performed.

In this way, when the timer display mode is set when the timer is not operating, the contents of the memory circuit 8 are transferred to the minute counter 7 and the second counter 9 is reset, so that the timer time once set can be used any number of times. When the set timer time elapses, the contents of the memory circuit 8 are transferred to the minute counter 7 again, so that the timer becomes a repeating timer based on the same timer time. When correcting the timer time, the second counter 6 is reset, the minute counter 7 is corrected, and its contents are stored; when the timer is corrected while the timer is operating, the second counter 6 remains in operation and is not reset, but the minute counter 7 is corrected and its contents are stored. memory is carried out. Furthermore, when the timer time is adjusted or when the timer is operating, even if switch SW ₁ is closed, the timer display mode does not change to another mode and returns to the time display mode, and all If you switch to the time display mode after switching to the time display mode, the annoyance will disappear.

As described above, according to the present invention, the down counter constituting the timer is provided with a storage circuit, and by controlling the down counter and the storage circuit with a control circuit, the stored timer time can be used any number of times. There is no need to reset the settings each time the timer operates,
Furthermore, since the repeat timer is automatically set, the troublesome operation of switches related to these timers is eliminated.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a logic circuit diagram of the control circuit shown in the embodiment of Fig. 1, and Fig. 3 shows the operation of Figs. 1 and 2. This is a timing chart. 1... Crystal oscillation circuit, 2... Frequency dividing circuit, 3,
4, 5...second counter, minute counter, hour counter, 6,7...second counter, minute counter, 8...
Memory circuit, 9, 10, 11, 12, 13...gate, 14...common line, 15...decoder, 1
6...Display device, 17...Mode selection circuit, 18
... Control circuit, 19 ... Zero detection circuit, 20 ...
pronunciation circuit.

Claims (1)

[Claims] 1. A first counter that counts a 1Hz second signal to obtain the time, a second counter that counts the second signal and operates as a timer, and a selection that selects display mode or correction mode, etc. by opening and closing a switch. In an electronic timer equipped with a circuit, the content of at least a portion of the second counter is stored;
a storage circuit that presets the stored contents in at least a portion of the second counter; and a control circuit that controls the second counter and the storage circuit depending on the state of the mode selection circuit; a gate means for outputting a control signal to which a signal indicating a timer time correction mode and a timer correction pulse are applied from the mode selection circuit to preset the contents of the second counter in the storage circuit; A gate to which a pulse outputted from the mode selection circuit when changing the timer display mode and a pulse outputted when the second counter counts up is applied to output a control signal for presetting the contents of the storage circuit in the second counter. An electronic clock with a timer, characterized in that it is equipped with means.