JPS6156827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data storage device used in a digital arithmetic control device.

As shown in FIG. 1, a conventional digital arithmetic control device includes a terminal unit 11, a direct memory access unit 12 (hereinafter referred to as DMA 12), a main memory 13, a central processing unit 14 (hereinafter referred to as CPU 14), and a common unit. It has a bus 15. In this digital arithmetic and control device,
Terminal unit 11 transfers the received data to DMA 12, which stores the data in memory 13 via common bus 15. This data transfer method can be applied without problems under general usage conditions, but in digital arithmetic control devices such as digital protective relay devices that require high-speed data processing, the following There are some drawbacks.

(1) When transferring data from the DMA 12 to the memory 13, the common bus 15 is used, so the CPU 1
4 temporarily waives the right to use common bus 15.
Give the right to use it to DMA12. Therefore,
While DMA 12 is transferring data to memory 13,
CPU 14 cannot use common bus 15, and CPU
14 processing efficiency decreases.

(2) The DMA 12 transfers (N+1) point data to the designated area of the memory 13 for each scan,
In a digital arithmetic control device in which the CPU 14 performs arithmetic processing using the latest data and old data from a certain period of time ago, the CPU 14 uses the DMA1
It is necessary to sequentially restore the latest data written by 2 to another area of the memory 13, and store the data for a certain period of time before processing.

(3) When the CPU 14 performs arithmetic processing using new and old data stored in a predetermined area of the memory 13, it is necessary to perform address counting each time to clarify the location of the latest data and old data from a certain time ago. , therefore, it takes time to search for the relevant data. In particular, in digital arithmetic control devices that sample and read input data at high speed and perform repetitive arithmetic processing, data storage,
Time is wasted in address calculations and the efficiency of the system is significantly reduced.

SUMMARY OF THE INVENTION An object of the present invention is to store data without using a common bus and apply it to digital arithmetic and control devices that require high-speed data processing, in order to eliminate the drawbacks of the conventional digital arithmetic and control devices described above. too
An object of the present invention is to provide a data storage device that does not cause a decrease in CPU processing efficiency.

The data storage device of the present invention includes a random access memory in which write and read modes are controlled based on a mode control signal, and a data storage location is specified by a channel number and an address within the channel, and input data is sequentially stored for each channel number. a receive data register to be read; a circular counter whose count value changes in synchronization with the read of the input data by the receive data register, and whose count value corresponds to the address within the channel of the random access memory; and the receive data register. a first address conversion circuit that generates a write address signal for data in the random access memory based on the channel number output of and the count value of the circulation counter; and a channel number and intra-channel relative address specified by the central processing unit. a second address conversion circuit that generates a read address signal for data stored in the random access memory; and a second address conversion circuit that selects the write address signal or the read address signal according to an address mode selection signal and supplies it to the random access memory. the mode selector of the random access memory; the mode control signal of the random access memory; a signal that controls reading of the input data by the receive data register; the address mode selection signal of the mode selector; The apparatus is characterized by comprising a control circuit that outputs an interrupt signal to notify the central processing unit when the output data of is stored.

The present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an example of the configuration of a digital arithmetic and control device to which the data storage device 21 according to the present invention is applied. In this digital arithmetic and control device, data received by the terminal unit 11 is directly stored in the data storage device 21, and the data storage device 21 and the CPU 14 are connected via the common bus 15, so DMA is not required. Data storage device 21
has a random access memory (hereinafter referred to as RAM) and an address conversion circuit, and the RAM has a storage area for storing at least (K+1) input data of the (N+1) channels collected by the terminal unit 11, The address conversion circuit is
Based on the designation of the storage location of the latest input data in the RAM and the relative address designation of the CPU 14, it is possible to designate the addresses of the required new and old stored data in the RAM. Terminal unit 11
The data of (N+1) channels is repeatedly taken in continuously at a constant sampling period, but the data storage device 21 is equipped with various error check circuits, and performs channel verification checks, parity checks, etc. when receiving input data. , it is possible to detect one-off errors, and by doing so, CPU1
The configuration is such that the arithmetic processing in step 4 can be continued without being hindered. Using this data storage device eliminates the need for data transfer to the memory 13 by the DMA 12 and complicated data search processing by the CPU 14, which were necessary in conventional digital arithmetic control devices, and the processing efficiency of the CPU 14 is improved.

FIG. 3 is a detailed block diagram of the data storage device 21. The data storage device 21 has a reception data register 31 and a strobe signal detection circuit 32 as an interface for receiving data transfer from the terminal unit 11. The reception data register 31 receives channel number 5 from the terminal unit 11.
1 and data 52 corresponding to the channel number are transferred. The strobe signal detection circuit 32 is
The rise of the strobe signal 53 is detected and a data latch request signal 54 is output to the control circuit 33. The control circuit 33 supplies a data latch signal 55 to the receiving data register 31 in response to the data latch request signal 54 . Therefore, the reception data register 31 reads the channel number 51 and its data 52 transferred from the terminal unit 11.
Regarding channel number 51 and data 52, one scan consists of (N+1) channels as shown in FIG. 4A, and strobe signal 53 has timing as shown in FIG. 4B. Now, assuming that the channel number output 58 of the input data read by the reception data register 31 is "0" indicating a start, the control circuit 33 outputs a control signal 56 and an address mode selection signal 57. Then, in response to the control signal 56, the positive circulation counter 34 increments its contents by "+1", and furthermore, the channel verification check circuit 35 and the status register 36 are reset. At this time, address mode selection signal 57
As shown in FIG. 4C, becomes a write mode selection signal, and therefore the mode selector 37 is switched to the write side. The positive circulation counter 34 adds “+1” every scan (K+1)
The count output 59 is supplied to the first address conversion circuit 38. The first address conversion circuit 38 has a count output 59 of the circulation counter 34.
Based on the channel number output 58 of the reception data register 31, the random access memory 3
9 (hereinafter referred to as RAM 39) address signal 6
Outputs 0. This address signal 60 is supplied to the RAM 37 as a write address signal 61 via the mode selector 37 which is switched to the write side by the write mode selection signal 57. At this time, the RAM 39 receives the output data 62 from the reception data register 31, but
Prior to writing the data 62, the following abnormality check is performed.

(i) The channel verification check circuit 35 performs verification between the channel number output 58 and the count value of the internal channel counter. If they do not match, the channel matching check circuit 35
outputs abnormal signals 63 and 64 to the status register 36 and control circuit 33, respectively.

(ii) Parity check circuit 40 checks the parity of channel number output 58 and data output 62. If there is an abnormality in parity, the parity check circuit 40 sends abnormality signals 64, 65.
are supplied to the control circuit 33 and the status register 36, respectively.

In this way, if there is an abnormality in channel matching and parity, the control circuit 33 will not output the write control signal 66 to the RAM 39, and therefore the RAM 39 will not output the write control signal 66.
37 aborts the write operation and the address signal 61
The old data in RAM 39 specified by is not updated and is saved as is. However, if there is no abnormality in channel verification and parity, the control circuit 33
In order to supply the write control signal 66 to the RAM 39, the RAM specified by the write address signal 61
The output data 62 of the reception data register 31 is sequentially written to the address 39 for each channel number 0 to N. Then, the reception data register 31 reads the final channel number N of one scan and its data 52, and the output data 62 is read into the RAM 3.
9, the control circuit 33 outputs the read mode selection signal 57 to the mode selector 37 to switch the mode selector 37 to the read side, and also notifies the CPU 14 that one scan cycle of data reading has been completed. An interrupt signal 67 is output to the common bus 15. In response to this interrupt signal 67, the CPU 14
Start reading data written to . Therefore, the CPU 14 first refers to the contents of the status register 36 to check whether the skin cycle that completed the data reading was normal. As a result, if there is no abnormality, as shown in FIG. Supplied to circuit 41. The second address conversion circuit 41 includes a subtracter 81, an adder 82, a selector 83, and an address register 84, as shown in FIG. The channel number address CHN of the address signal 68 is input as is to the channel number address designation unit CHM by the address register 84, but the relative address α is converted into an absolute address in the RAM 39. Here, the relative address α is 1, 2, ......, K, with the address of the latest read data being 0.
Specify the in-channel address of the old data in this order. The memory allocation of the RAM 39 is arranged as shown in FIG. 7, for example, with channel numbers 0 to N being arranged from 0 to K
Data based on up to (K+1) scans can be stored. As already mentioned, the data write address is specified by the first address conversion circuit 38 based on the channel number output 58 of the reception data register 31 and the count value of the positive circulation counter 34. Now, if the write address of the latest data is "k" for each channel, the channel number address is determined by the channel number output 58 of the reception data register 31, but the address "k" in each channel is determined by the positive circulation counter 34. The relationship between them is as shown in Figure 7. Here, the hatched area of each channel is address "k", and the latest data is stored in this area. (However, 0
≦k≦K. ) Next, to explain the relative address α in the channel of the CPU 14, when reading the latest data, it is sufficient to set the relative address α = 0, and it is sufficient to set the relative address α = 0.
When reading the old data stored in K), the relative address α=i. Therefore, CPU14 is
There is no need to recognize at which absolute address in the RAM 39 the old data from i times ago is stored and search for data. This is an extremely effective addressing method especially for digital arithmetic control devices that perform arithmetic processing using the latest data and old data, such as digital protective relay devices. This addressing method will now be explained with reference to the flowchart of FIG. First, step 85
Then, the address signal 68 is sent from the CPU 14 to the second address conversion circuit 41. Then, in step 86, the channel number address CHN of the address signal 68 is directly transferred to the channel number address designation section CHM of the address register 84.
However, regarding the intra-channel relative address α, the subtracter 81 performs subtraction A=k−α with the count value k of the positive circulation counter 35. (however,
Enter the absolute address of the latest data as shown in Figure 7.
Let it be k. ) In the next step 87, the subtraction output A
It is determined whether the output is positive or negative, but this means that the output A≧0
In this case, the data that the CPU 14 requests to read is located at 0 in the absolute address space within the channel.
to k (see Figure 7), but A<
0, it is an absolute address space (k+
1) to K, so it is necessary to determine them. Therefore, when the subtracted output A is A≧0, the output A is sent to the in-channel address designation section of the address register 84 via the selector 83 as the operation of step 89.
Enter into MSM. However, when A<0,
In response to the determination signal from the subtracter 81, the selector 83 is switched to receive the output from the adder 82. Then, in step 88, the adder 82 adds the subtracted output A and the constant input (K+1), and in the next step 89, the added output (A+K+1) is sent to the address register 84 to be designated as an in-channel address. Enter the section MSM. That is, the addition output (A+K+1) specifies any data from (k+1) to K in the absolute address space. In this way, address register 84 can obtain the channel number address and intra-channel address, and the address translation operation is completed at step 90. At this time, the control circuit 33 has already selected the mode selector 37.
Since the read mode selection signal 57 is output to the RAM 39 and the read signal 66 is output to the RAM 39, the address signal 69 of the second address conversion circuit 41 is sent to the RAM 39 via the mode selector 37.
address signal 61, and the data 70 of the channel number specified by that address is stored in the RAM 39.
is read from the CPU 1 via the common bus 15.
Transferred to 4.

This data storage device 29 includes a time monitoring timer 42 in addition to a channel checking circuit 35 and a parity check circuit 40 as abnormality monitoring circuits. The time monitoring timer 42 monitors the data reception interval using the control signal 56, and can detect an abnormality in the data sampling interval due to a hardware abnormality or a stop in sampling. When an abnormality is detected, the time monitoring timer 42 transmits the time monitoring abnormality signal 71 to the status register 3.
6 and outputs an interrupt signal 72 to the CPU 14. CPU14 transfers data to RAM3
9, the status register 36 is always checked first. In case of time monitoring abnormality,
Since the CPU 14 cannot continue normal data processing, it performs interrupt processing to remove the failure.

As described above, according to the present invention, input data can be sequentially stored in a predetermined area without going through a common bus, so the processing efficiency of the CPU is improved, and when data is processed by the CPU, data written to RAM is There is no need for relocation. Further, since the data can be specified by a relative address from the CPU, no time is wasted in data storage or address calculation, so the efficiency of the system to which the present invention is applied can be improved. In particular, the data storage device of the present invention is a digital protection relay that performs protection relay calculation control by sampling analog quantities such as voltage and current from the power system at regular intervals and collecting quantized data. The present invention is suitable for digital arithmetic control devices that require repetitive calculations at high speeds, such as devices. Furthermore, by providing input data channel verification, parity check, time monitoring functions, etc., the reliability of the device can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional digital arithmetic and control device, FIG. 2 is a block diagram of a digital arithmetic and control device combined with a data storage device according to the present invention, and FIG.
The figure is a block diagram showing an example of the configuration of the data storage device shown in FIG. 2, FIGS. 4A to 4C are timing charts of the main parts thereof, and FIG. 5 is an addressing format diagram for reading out the data storage device. FIG. 6 is a block diagram of the second address conversion circuit for reading data, FIG. 7 is a block diagram showing memory allocation, and FIG. 8 is an operation flowchart of the second address conversion circuit described above. 11...Terminal unit, 14...Central processing unit (CPU), 15...Common bus, 21...Data storage device, 31...Reception data register, 32...
Strobe signal detection circuit, 33...control circuit, 3
4...First address conversion circuit, 35...Plus circulation counter, 36...Mode selector, 37...
Random access memory (RAM), 38...2nd
Address conversion circuit, 39... Channel verification circuit, 40... Parity check circuit, 41... Time monitoring timer, 42... Status register, 81...
Subtractor, 82... Adder, 83... Selector, 8
4...Address register.

Claims (1)

[Claims] 1. A random access memory in which write and read modes are controlled based on a mode control signal, and a data storage location is specified by a channel number and an address within the channel, and input data is sequentially read for each channel number. a reception data register, a circular counter whose count value changes in synchronization with reading of the input data by the reception data register, and whose count value corresponds to the address in the channel of the random access memory; In order to directly store sequentially read input data into the random access memory each time, the write address of the data in the random access memory is determined based on the channel number output of the receive data register and the count value of the circulation counter. a first address conversion circuit that generates a signal; a second address conversion circuit that generates a read address signal for data stored in the random access memory based on a channel number and an intra-channel relative address specified by a central processing unit; a mode selector that selects the write address signal or the read address signal according to an address mode selection signal and supplies it to the random access memory; a mode selector that selects the write address signal or the read address signal according to an address mode selection signal; When the process of storing a read control signal, the address mode selection signal of the mode selector, and input data from a first channel number to a last channel number into the random access memory via the received data register, A data storage device comprising: a control circuit that outputs an interrupt signal to notify the central processing unit. 2. A channel verification circuit that verifies the count value of the circulation counter and the channel number output of the reception data register, and a parity check circuit that verifies the parity of the data output of the reception data register, When the circuit outputs a channel verification abnormal signal and/or when the parity check circuit outputs a parity abnormal signal, the control circuit does not output the mode control signal for writing to the random access memory. A data storage device according to claim 1. 3. Claim 2, further comprising a timer that monitors the time during which the received data register reads the input data, and outputs an interrupt signal requesting abnormality processing to the central processing unit if an abnormality occurs. Data storage device as described. 4. The data storage device according to claim 3, further comprising a status register that stores the outputs of the channel check circuit, the parity check circuit, and the timer, respectively. 5. The second address conversion circuit includes a subtracter that subtracts the intra-channel relative address from the count value of the circulation counter, and adds the output of the subtracter to a constant obtained by adding 1 to the upper limit count value of the circulation counter. an adder that selects the output of the subtracter when the subtraction result of the subtracter is positive, and a selector that selects the output of the adder when the subtraction result is negative; 2. The data storage device according to claim 1, further comprising an address register that stores the channel number specified by the device and the output of the selector.