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JPS6156875B2 - - Google Patents
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JPS6156875B2 - - Google Patents

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Publication number
JPS6156875B2
JPS6156875B2 JP54163121A JP16312179A JPS6156875B2 JP S6156875 B2 JPS6156875 B2 JP S6156875B2 JP 54163121 A JP54163121 A JP 54163121A JP 16312179 A JP16312179 A JP 16312179A JP S6156875 B2 JPS6156875 B2 JP S6156875B2
Authority
JP
Japan
Prior art keywords
film
deposited
substrate
forming
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54163121A
Other languages
Japanese (ja)
Other versions
JPS5683087A (en
Inventor
Yaichiro Watakabe
Tadao Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16312179A priority Critical patent/JPS5683087A/en
Publication of JPS5683087A publication Critical patent/JPS5683087A/en
Publication of JPS6156875B2 publication Critical patent/JPS6156875B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0912Manufacture or treatment of Josephson-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳細な説明】 この発明は、ブリツジ形のジヨゼフソン素子の
製造方法の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a bridge-type Josephson element.

第1図Aおよび第1図Bはそれぞれブリツジ形
のジヨゼフソン素子の一例を示す平面図、第2図
は第1図Aまたは第1図Bに示すジヨゼフソン素
子の第1図AまたはBの−線における断面
図、第3図は第1図Bに示すジヨゼフソン素子の
斜視図である。第1図、第2図および第3図おい
て、1,2はニオブ(Nb)、鉛(Pb)などの超電
導体からなる超電導膜である。超電導膜1と超電
導膜2とは同種の超電導体からなつていてもよ
く、異種の超電導体からなつていてもよい。3は
超電導体からなり二つの超電導膜1,2を弱く結
びつけている接合部分(くびれ部分)、4はガラ
ス、サフアイヤ、などの絶縁体またシリコンなど
のジヨゼフソン素子の動作温度では絶縁体となる
半導体からなる基板である。
1A and 1B are plan views each showing an example of a bridge-type Josephson element, and FIG. 2 is a - line in FIG. 1A or B of the Josephson element shown in FIG. 1A or FIG. 1B. FIG. 3 is a perspective view of the Josephson device shown in FIG. 1B. In FIGS. 1, 2, and 3, 1 and 2 are superconducting films made of superconductors such as niobium (Nb) and lead (Pb). The superconducting film 1 and the superconducting film 2 may be made of the same type of superconductor or may be made of different types of superconductors. 3 is a joining part (neck part) made of a superconductor and weakly connects the two superconducting films 1 and 2; 4 is an insulator such as glass or sapphire, or a semiconductor such as silicon which becomes an insulator at the operating temperature of the Josephson device. It is a board consisting of.

超電導膜1および2が、それらの状態を異なつ
た位相の波動関数ψ、ψで表わせる程度に弱
く結合されている(結合強度を小さな係数εで表
わす)とすれば、ψ、ψの従う方程式は、結
合を通して侵入する超電導電子を摂動項として加
え、 で表わせるシユレーデインガー方程式である。
If superconducting films 1 and 2 are weakly coupled to the extent that their states can be expressed by wave functions ψ 1 and ψ 2 with different phases (the coupling strength is expressed by a small coefficient ε), then ψ 1 , ψ The equation followed by 2 adds the superconducting electrons entering through the bond as a perturbation term, This is the Schrödinger equation that can be expressed as

ここに、μ、μはそれぞれ超電導膜1,2
の超電導体の電子のエネルギーである。
Here, μ 1 and μ 2 are superconducting films 1 and 2, respectively.
is the energy of the electrons in the superconductor.

超電導膜1,2の超電導体の超電導電子の密度
および位相をそれぞれn1、n2およびθ、θ
すれば、 と書ける。
If the density and phase of superconducting electrons of the superconductors of superconducting films 1 and 2 are n 1 , n 2 and θ 1 , θ 2 respectively, then It can be written as

()式を()式に代入し、n1=n2=nとお
き、実部と虚部とを別に扱つて、 ∂n1/∂t=(2/h)εnsin(θ−θ)=−∂n2/∂t () (∂/∂t)(θ−θ)=−(1/h)(μ−μ) () が導かれる。
Substituting equation () into equation (), setting n 1 = n 2 = n, and treating the real part and imaginary part separately, we get ∂n 1 /∂t=(2/h)εnsin(θ 2 −θ 1 )=-∂n 2 /∂t () (∂/∂t) (θ 2 −θ 1 )=−(1/h)(μ 2 −μ 1 ) () is derived.

超電導膜2から超電導膜1へ向う電流は 2e∂n1/∂t(eは電子の電荷) に等しいから、接合部分3における超電導体の断
面積および体積をそれぞれSおよびVとすれば、
電流密度iは、次記の()式および()式に
よつて表わせる。
The current flowing from superconducting film 2 to superconducting film 1 is equal to 2e∂n 1 /∂t (e is the charge of electrons), so if the cross-sectional area and volume of the superconductor at junction 3 are S and V, respectively,
The current density i can be expressed by the following equations () and ().

i=i0 sin(θ−θ) () i0=4eVεn1/hS () ()式で位相差θ−θ=θが零でなけれ
ば、sinθに比例する超電導電流が流れる。この
超電導電流がジヨゼフソン電流である。
i = i 0 sin (θ 2 - θ 1 ) () i 0 = 4eVεn 1 /hS () In equation (), if phase difference θ 1 - θ 2 = θ is not zero, a superconducting current proportional to sin θ will flow. . This superconducting current is the Josephson current.

第1図、第2図および第3図に示すジヨゼフソ
ン素子は、接合部分3の微細加工がむつかしい。
接合部分3の長さl、幅w、厚さdを制御する必
要がある。長さl、幅wの微細加工は電子ビーム
露光法などにより可能であるが、厚さdを超電導
膜1,2からなる電極部分より薄くすることが困
難である。つまり、接合部分3のみを、エツチン
グで薄くしたり、従来法の蒸着で薄く蒸着するこ
とは困難であつた。そのため、二つの超電導膜
1,2を弱く結合させるために接合部分3を微細
加工で制御性よく形成することが困難であつた。
In the Josephson elements shown in FIGS. 1, 2, and 3, microfabrication of the joint portion 3 is difficult.
It is necessary to control the length l, width w, and thickness d of the joint portion 3. Although fine processing with a length l and a width w is possible by electron beam exposure, etc., it is difficult to make the thickness d thinner than the electrode portion made of the superconducting films 1 and 2. In other words, it is difficult to thin only the joint portion 3 by etching or to thinly deposit it by conventional vapor deposition methods. Therefore, it has been difficult to form the bonding portion 3 with good controllability through fine processing in order to weakly bond the two superconducting films 1 and 2 together.

この発明は、上記の点に鑑みてなされたもので
あり、垂直蒸着法によつて電極部分である二つの
超電導膜とその間の接合部分を厚さを制御して薄
く形成した後、斜め蒸着法によつて電極部分の超
電導膜のみを厚くすることによつて、接合部分の
厚さを精度良く制御することができるジヨゼフソ
ン素子の製造方法を提供することを目的としたも
のである。
This invention was made in view of the above points, and after controlling the thickness of two superconducting films, which are electrode parts, and the bonding part between them by vertical evaporation method, the thickness of the two superconducting films is controlled to be thin, and then by diagonal evaporation method. It is an object of the present invention to provide a method of manufacturing a Josephson device in which the thickness of the bonding portion can be controlled with high precision by thickening only the superconducting film in the electrode portion.

以下、実施例に基づいてこの発明を説明する。 The present invention will be explained below based on examples.

第4図A〜Gはこの発明によるジヨゼフソン素
子の製造方法の一実施例の主要段階を示す切断面
図であり、第5図A〜Dはそれぞれ第4図D〜G
に対応する平面図である。なお、第4図は第3図
に示す−線における切断面図である。
4A to 4G are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a Josephson device according to the present invention, and FIGS. 5A to 5D are sectional views, respectively.
FIG. Note that FIG. 4 is a cross-sectional view taken along the - line shown in FIG. 3.

まず、第4図Aに示すように、例えばシリコン
基板4a上に二酸化ケイ素(SiO2)膜などの基板
表面絶縁膜5、この基板表面絶縁膜5とは異種の
窒化ケイ素(Si3N4)膜などの絶縁膜または多結晶
シリコンなどの半導体膜からなる中間被膜6およ
び絶縁膜からなる上部被膜7を順次形成する。上
部被膜7は基板表面絶縁膜5と同種のものであつ
ても良い。次に、第4図Bに示すように、上部被
膜7上に光用レジスト(例えばAZ−1350)、電子
線用レジスト(例えばPMMA、PBS)などから
なるレジスト膜8を塗布し、光または電子線によ
つて所望のジヨゼフソン素子のパターンを描画す
る。つづいて、第4図Cに示すように、レジスト
膜8を現像して上記パターンを有する開口部81
を形成し、この開口部81を有するレジスト膜8
をマスクとして、湿式エツチングおよび乾式エツ
チングによつて、上部被膜7に開口部81に一致
する開口部71を形成する。次に、第4図Dおよ
び第5図Aに示すように、レジスト膜8または上
部被膜7をマスクとする湿式エツチングおよび乾
式エツチングによつて、中間被膜6をエツチング
してジヨゼフソン素子パタンを有する開口部71
の周縁の外側に周縁を有する開口部61を形成す
る。つづいて、第4図Eおよび第5図Bに示すよ
うに、レジスト膜8を除去した後、シリコン基板
4aの主面に対してほぼ垂直方向に、ニオブ
(Nb)、鉛(Pb)などの超電導体を電子ビーム蒸
着法などによつて蒸着し第1の蒸着膜9を、接合
部分における第1の蒸着膜91の厚さが所望の厚
さになるように形成する。この蒸着により、第1
の蒸着膜91の厚さを数10Åから数100Åの厚さ
に制御することができる。さらに、第4図Fおよ
び第5図Cに示すように、同様の蒸着法により、
接合部分の第1の蒸着膜91上には蒸着されない
ように、同質または異質の超電導体を斜めに蒸着
して第1の蒸着膜9と一体となつた厚さ数1000Å
程度の厚い第2の蒸着膜9aを形成する。最後に
第4図Gおよび第5図Dに示すように、中間被膜
6を湿式エツチングまたは乾式エツチングによつ
てエツチング除去することによつて、上部被膜7
とその上の第2の蒸着膜9aをリフトオフする
と、第3図の一点鎖線にて示す位置においては、
第2の蒸着膜9aが除去され接合部分における第
1の蒸着膜91が残存して接合部分3となる。第
3図に示す一点鎖線に垂直な方向には厚さの厚い
第2の蒸着膜9aも残存して、接合部分3が薄く
電極部分である超電導膜1,2は厚い所望のジヨ
ゼフソン素子を得ることができる。超電導膜1,
2を接合部分3と同様に薄くすれば、膜形成時に
生ずるピンホールにより安定した特性が得られな
かつたり、基板4aから剥離したりする問題があ
るので、超電導膜1,2は厚くしておく必要があ
り、この点から、この発明による方法が有効とな
る。
First, as shown in FIG. 4A, a substrate surface insulating film 5 such as a silicon dioxide (SiO 2 ) film is formed on a silicon substrate 4a, and a silicon nitride (Si 3 N 4 ) film of a different type from the substrate surface insulating film 5 is deposited on a silicon substrate 4a. An intermediate film 6 made of an insulating film such as a film or a semiconductor film such as polycrystalline silicon, and an upper film 7 made of an insulating film are sequentially formed. The upper coating 7 may be of the same type as the substrate surface insulating film 5. Next, as shown in FIG. 4B, a resist film 8 made of a photoresist (e.g. AZ-1350), an electron beam resist (e.g. PMMA, PBS), etc. is coated on the upper coating 7, and Draw the desired Josephson element pattern by lines. Subsequently, as shown in FIG. 4C, the resist film 8 is developed to form an opening 81 having the above pattern.
, and has this opening 81.
Using as a mask, an opening 71 corresponding to the opening 81 is formed in the upper coating 7 by wet etching and dry etching. Next, as shown in FIG. 4D and FIG. 5A, the intermediate film 6 is etched by wet etching and dry etching using the resist film 8 or the upper film 7 as a mask to form an opening having a Josephson element pattern. Section 71
An opening 61 having a periphery outside the periphery of the opening 61 is formed. Subsequently, as shown in FIGS. 4E and 5B, after removing the resist film 8, niobium (Nb), lead (Pb), etc. A superconductor is vapor-deposited by electron beam evaporation or the like to form a first vapor-deposited film 9 such that the first vapor-deposited film 91 has a desired thickness at the joint portion. By this vapor deposition, the first
The thickness of the deposited film 91 can be controlled from several tens of angstroms to several hundreds of angstroms. Furthermore, as shown in FIG. 4F and FIG. 5C, by the same vapor deposition method,
A superconductor of the same or different nature is obliquely deposited so as not to be deposited on the first deposited film 91 at the joint part, and is integrated with the first deposited film 9 to a thickness of several thousand Å.
A second vapor deposited film 9a having a certain thickness is formed. Finally, as shown in FIGS. 4G and 5D, the intermediate coating 6 is etched away by wet etching or dry etching to form the upper coating 7.
When the second vapor deposited film 9a thereon is lifted off, at the position shown by the dashed line in FIG.
The second vapor deposited film 9a is removed, and the first vapor deposited film 91 remains at the joint portion, forming the joint portion 3. A thicker second vapor deposited film 9a also remains in the direction perpendicular to the dashed-dotted line shown in FIG. 3, resulting in a desired Josephson device in which the bonding portion 3 is thin and the superconducting films 1 and 2, which are electrode portions, are thick. be able to. superconducting film 1,
If superconducting films 2 are made as thin as bonding portion 3, there will be problems such as not being able to obtain stable characteristics due to pinholes that occur during film formation, or peeling off from substrate 4a, so superconducting films 1 and 2 should be made thick. This is necessary, and from this point of view, the method according to the present invention is effective.

二つ超電導膜1,2の接合部分3の結合の度合
いは、超電導膜1,2が互いに異なつた位相を示
す程度に弱く、同時に超電導電子の往来を許す程
度に強いものである必要がある。このため、接合
部分3は精度の高い微細加工が必要となる。接合
部分3の長さl、幅wは電子ビーム露光法により
制御できるが、厚さdは蒸着により制御しなけれ
ばならない。近年、高度の蒸着技術により膜厚は
数10〜100Åの制御は可能である。この発明は斜
め蒸着と垂直蒸着とを利用することで接合部分3
は数10〜数100Åの厚さの薄い膜厚が得られ、電
極部分である超電導膜1,2は数1000Åの厚さの
厚い膜厚が得られることが特徴である。この発明
の方法によつて、接合部分3の断面積Sと接合係
数εとが精度良く定まり安定した特性の良いジヨ
ゼフソン素子を形成することができる。
The degree of bonding between the two superconducting films 1 and 2 at the junction 3 needs to be weak enough that the superconducting films 1 and 2 exhibit different phases from each other, and strong enough to allow superconducting electrons to pass back and forth. Therefore, the joint portion 3 requires highly precise micromachining. The length l and width w of the joint portion 3 can be controlled by electron beam exposure, but the thickness d must be controlled by vapor deposition. In recent years, advanced vapor deposition technology has made it possible to control film thicknesses of several tens to 100 Å. This invention utilizes oblique vapor deposition and vertical vapor deposition to
The superconducting films 1 and 2, which are the electrode portions, are characterized in that a thin film thickness of several tens to several hundred angstroms can be obtained, and a thick film thickness of several thousand angstroms can be obtained. By the method of the present invention, the cross-sectional area S of the bonding portion 3 and the bonding coefficient ε can be determined with high accuracy, and a Josephson element with stable characteristics can be formed.

上記の実施例においては、シリコン基板4a上
にSiO2膜からなる基板表面絶縁膜5を形成する
場合について述べたが、この基板表面絶縁膜は必
ずしも必要ではない。
In the above embodiment, a case has been described in which the substrate surface insulating film 5 made of an SiO 2 film is formed on the silicon substrate 4a, but this substrate surface insulating film is not necessarily required.

また、上記実施例においては、中間被膜6が絶
縁膜または多結晶シリコン膜からなり、上部被膜
が絶縁膜からなる場合について述べたが、必ずし
もその必要はなく、これらの二つの被膜が例えば
金属から形成されていてもよい。
Furthermore, in the above embodiments, a case has been described in which the intermediate film 6 is made of an insulating film or a polycrystalline silicon film, and the upper film is made of an insulating film. may be formed.

以上詳述したように、この発明によるジヨゼフ
ソン素子の製造方法においては、ジヨゼフソン素
子のパターンの開口部を有する被膜をマスクとし
て、基板の主面にほぼ垂直な方向の蒸着による厚
さの薄い第1の蒸着膜によつて電極部分となる超
電導膜と接合部分となる超電導膜を形成し、接合
部分には蒸着されないような斜め蒸着による厚さ
の厚い第2の蒸着膜によつて電極部分の厚さを厚
くするので、接合部分を十分に薄くしかも寸法精
度よく形成することができると共に電極部分を厚
く形成することができるから、特性の良いジヨゼ
フソン素子を製造することができる。
As described in detail above, in the method of manufacturing a Josephson device according to the present invention, a thin first layer is formed by vapor deposition in a direction substantially perpendicular to the main surface of a substrate, using a film having openings in the pattern of a Josephson device as a mask. A superconducting film that will become the electrode portion and a superconducting film that will become the bonding portion are formed by the vapor-deposited film, and a thick second vapor-deposited film by diagonal vapor deposition that is not deposited on the bonding portion increases the thickness of the electrode portion. Since the thickness is increased, the joint portion can be formed sufficiently thin and with high dimensional accuracy, and the electrode portion can be formed thick, so a Josephson element with good characteristics can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図AおよびBはそれぞれブリツジ形ジヨゼ
フソン素子の一例の平面図、第2図は第1図Aま
たはBに示すジヨゼフソン素子の断面図、第3図
は第1図Bに示すジヨゼフソン素子の斜視図、第
4図A〜Gはこの発明によるジヨゼフソン素子の
製造方法の一実施例の主要段階を示す切断面図、
第5図A〜Dはそれぞれ第4図D〜Gに対応する
平面図である。 図において、1,2はそれぞれ電極部分である
超電導膜、3は接合部分、4は基板、4aはシリ
コン基板、5は基板表面絶縁膜、6は中間被膜、
61は開口部、7は上部被膜、71は開口部、8
はレジスト膜、81は開口部、9は第1の蒸着
膜、91は接合部分における第1の蒸着膜9、9
aは第2の蒸着膜である。なお、図中同一符号は
それぞれ同一または相当部分を示す。
Figures 1A and B are plan views of examples of bridge-type Josephson elements, Figure 2 is a sectional view of the Josephson element shown in Figure 1A or B, and Figure 3 is a perspective view of the Josephson element shown in Figure 1B. 4A to 4G are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a Josephson device according to the present invention,
FIGS. 5A to 5D are plan views corresponding to FIGS. 4D to G, respectively. In the figure, 1 and 2 are superconducting films that are electrode parts, 3 is a bonding part, 4 is a substrate, 4a is a silicon substrate, 5 is a substrate surface insulating film, 6 is an intermediate coating,
61 is an opening, 7 is an upper coating, 71 is an opening, 8
81 is a resist film, 81 is an opening, 9 is a first vapor deposited film, 91 is a first vapor deposited film 9, 9 in a joint part
a is the second deposited film. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 1 ジヨゼフソン素子の動作温度では絶縁体であ
る基板上に中間被膜を形成しこの中間被膜上にこ
の中間被膜に対するエツチング材によつてはエツ
チングされないかエツチング速度が遅い材料から
なる上部被膜を形成する工程、上記上部被膜上に
レジスト膜を形成する工程、2つの電極部分と該
電極部分を結ぶ接合部分とが平面的に配列された
ジヨゼフソン素子のパターンを有する開口部を上
記レジスト膜に形成する工程、上記レジスト膜を
マスクにしてエツチングし上記上部被膜に上記レ
ジスト膜の上記開口部と一致する開口部を形成す
る工程、上記レジスト膜または上記上部被膜をマ
スクにしてエツチングし上記中間被膜に上記上部
被膜の上記開口部の周縁より外側に周壁を有する
開口部を形成する工程、上記レジスト膜を除去し
た上記上部被膜の上方から上記基板の主面にほぼ
垂直な方向に超電導体を蒸着し上記基板上に蒸着
された第1の部分と上記上部被膜上に蒸着された
第2の部分とからなる第1の蒸着膜を形成する工
程、上記上部被膜の上方から上記第1の蒸着膜の
上記第1の部分のジヨゼフソン素子の接合部分と
なる部分には蒸着されないように上記基板の主面
に対して斜め方向に超電導体を蒸着して第2の蒸
着膜を形成する工程、ならびに上記中間被膜をエ
ツチング除去する工程を順次備えたことを特徴と
するジヨゼフソン素子の製造方法。 2 中間被膜が多結晶シリコン膜であり上部被膜
が二酸化ケイ素膜であることを特徴とする特許請
求の範囲第1項記載のジヨゼフソン素子の製造方
法。 3 基板がシリコン基板とその表面に被着された
二酸化ケイ素とからなることを特徴とする特許請
求の範囲第1項または第2項記載のジヨゼフソン
素子の製造方法。
[Claims] 1. An intermediate film is formed on the substrate which is an insulator at the operating temperature of the Josefson element, and the intermediate film is made of a material that is not etched or has a slow etching rate depending on the etching agent for the intermediate film. a step of forming an upper film, a step of forming a resist film on the upper film, and a step of forming an opening having a pattern of Josephson elements in which two electrode parts and a joint part connecting the electrode parts are arranged in a plane using the resist film. a step of etching using the resist film as a mask to form an opening in the upper film that matches the opening of the resist film; etching using the resist film or the upper film as a mask; forming an opening in the intermediate film having a peripheral wall outside the periphery of the opening in the upper film; a step of forming a superconductor in a direction substantially perpendicular to the main surface of the substrate from above the upper film from which the resist film has been removed; forming a first deposited film consisting of a first part deposited on the substrate and a second part deposited on the upper film; forming a second vapor-deposited film by vapor-depositing a superconductor in a direction oblique to the main surface of the substrate so that the superconductor is not vapor-deposited on a portion of the first portion of the vapor-deposited film that will be a bonding portion of the Josefson element; and a step of sequentially etching away the intermediate film. 2. The method for manufacturing a Josephson device according to claim 1, wherein the intermediate film is a polycrystalline silicon film and the upper film is a silicon dioxide film. 3. The method for manufacturing a Josephson device according to claim 1 or 2, wherein the substrate is made of a silicon substrate and silicon dioxide deposited on the surface of the silicon substrate.
JP16312179A 1979-12-11 1979-12-11 Manufacture of josephson element Granted JPS5683087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16312179A JPS5683087A (en) 1979-12-11 1979-12-11 Manufacture of josephson element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16312179A JPS5683087A (en) 1979-12-11 1979-12-11 Manufacture of josephson element

Publications (2)

Publication Number Publication Date
JPS5683087A JPS5683087A (en) 1981-07-07
JPS6156875B2 true JPS6156875B2 (en) 1986-12-04

Family

ID=15767570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16312179A Granted JPS5683087A (en) 1979-12-11 1979-12-11 Manufacture of josephson element

Country Status (1)

Country Link
JP (1) JPS5683087A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146987A (en) * 1979-05-07 1980-11-15 Fujitsu Ltd Manufacture of tunnel junction type josephson element

Also Published As

Publication number Publication date
JPS5683087A (en) 1981-07-07

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