JPS6156889B2 - - Google Patents
Info
- Publication number
- JPS6156889B2 JPS6156889B2 JP54009451A JP945179A JPS6156889B2 JP S6156889 B2 JPS6156889 B2 JP S6156889B2 JP 54009451 A JP54009451 A JP 54009451A JP 945179 A JP945179 A JP 945179A JP S6156889 B2 JPS6156889 B2 JP S6156889B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- distortion
- circuit
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Radio Relay Systems (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は、無線中継器などにおいて、高周波出
力増幅器で発生する歪を抑えるために、前段の中
間周波数増幅段の信号に、予じめ逆成分の歪を与
えておく場合の、三次歪成分のみを出力させる三
次歪発生器に関する。DETAILED DESCRIPTION OF THE INVENTION In order to suppress distortion generated in a high frequency output amplifier in a wireless repeater or the like, the present invention applies inverse component distortion to the signal of the preceding intermediate frequency amplification stage in advance. This invention relates to a third-order distortion generator that outputs only third-order distortion components.
例えば、マイクロ波帯で用いられる進行波管は
原理的に歪を発生する。そのため、PCM伝送な
どで多値化が進むにつれて、その歪が問題になつ
てくる。そこで、信号に予じめ逆成分の歪を与え
ておくことにより、進行波管高周波増幅器で発生
する歪を補償することが行なわれている。 For example, traveling wave tubes used in microwave bands generate distortion in principle. Therefore, as multi-level transmission advances in PCM transmission, etc., distortion becomes a problem. Therefore, the distortion generated in the traveling wave tube high frequency amplifier is compensated for by applying distortion of an inverse component to the signal in advance.
第１図はこのような逆成分の歪をもつた信号を
得る回路であり、入力信号は入力ハイブリツド１
で２分岐され、分岐された一つの信号は移相器３
により移相され、三次歪発生器４により三次歪に
変換され、増幅器５により適当なレベルまで増幅
される。そして、入力ハイブリツド１で分岐さ
れ、遅延線６を通つてきた他方の信号と出力ハイ
ブリツド２において合成されて、後段の高周波増
幅器で発生する三次歪を抑圧する逆成分の歪をも
つた信号が得られる。なお、この回路で、歪成分
と信号成分の位相関係は移相器３により制御され
る。 Figure 1 shows a circuit that obtains a signal with such inverse component distortion, and the input signal is input hybrid 1.
The branched signal is split into two by the phase shifter 3.
The signal is phase-shifted by the third-order distortion generator 4, converted into third-order distortion by the third-order distortion generator 4, and amplified by the amplifier 5 to an appropriate level. The signal is then branched at the input hybrid 1 and combined with the other signal that has passed through the delay line 6 at the output hybrid 2 to obtain a signal with an inverse component of distortion that suppresses the third-order distortion generated in the high-frequency amplifier at the subsequent stage. It will be done. In this circuit, the phase relationship between the distortion component and the signal component is controlled by the phase shifter 3.
このような前置歪発生装置において、従来の三
次歪発生器は、信号キヤンセル部に、二端子間の
位相差が180゜の四端子ハイブリツドを用い、
又、三次歪発生部には特性のそろつたPNP，
NPNの対になつたトランジスタを用いたもので
構成されており、回路的に複雑となり、部品点数
も多く、調整法も容易でなく、信頼性も劣り、さ
らに高価格になるという欠点があつた。 In such a predistortion generator, a conventional third-order distortion generator uses a four-terminal hybrid with a phase difference of 180° between two terminals in the signal canceling section.
In addition, the tertiary distortion generation section is equipped with PNP, which has uniform characteristics.
It is constructed using a pair of NPN transistors, and has the disadvantages of a complex circuit, a large number of parts, difficult adjustment methods, poor reliability, and high price. .
本発明はこれらの欠点を除くために、主信号キ
ヤンセル部を通常のハイブリツドで、歪発生部を
ダイオードで構成することにより、回路の簡素
化、部品点数の低減、調整の容易化、信頼性の向
上および価格の低廉化が得られる三次歪発生器を
提供するにある。 In order to eliminate these drawbacks, the present invention simplifies the circuit, reduces the number of parts, facilitates adjustment, and improves reliability by configuring the main signal canceling section with an ordinary hybrid and the distortion generating section with a diode. The object of the present invention is to provide a third-order distortion generator that can be improved and lowered in price.
つぎに図面により本発明の実施例を説明する。
第２図は本発明の実施例であつて、１３は巻線比
一対一のオートトランスであり、その一方端１１
は信号入力端子、他方端１２は信号出力端子であ
る。信号入出力端子１１と１２間には特性インピ
ーダンスの２倍の抵抗値の橋絡抵抗１４が接続さ
れ、さらに、中間タツプＣとアース間には特性イ
ンピーダンの1/2の抵抗値の中間タツプ終端抵抗
１５が接続されており、以上の部品構成によりハ
イブリツド回路が形成されている。このハイブリ
ツド回路の中間タツプＣ点とアース間には、直流
阻止用結合コンデンサ１６を介して、逆並列接続
の２個のダイオード１７と１８が接続されてい
る。ダイオード１７の一端を高周波的にアースし
ているコンデンサ２０はダイオード１７と１８に
バイアス電流を供給するためのバイアス電流供給
回路のバイパスコンデンサであり、バイア電流回
路はさらに、バイアス電流電源端子２１と電流調
整用の可変抵抗２２と、高周波チヨークコイル２
３とを含む。 Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 shows an embodiment of the present invention, in which 13 is an autotransformer with a winding ratio of 1:1, and one end 11
is a signal input terminal, and the other end 12 is a signal output terminal. A bridging resistor 14 with a resistance value twice the characteristic impedance is connected between the signal input/output terminals 11 and 12, and an intermediate tap termination with a resistance value 1/2 the characteristic impedance is connected between the intermediate tap C and the ground. A resistor 15 is connected, and a hybrid circuit is formed by the above component configuration. Two anti-parallel diodes 17 and 18 are connected between the intermediate tap point C of this hybrid circuit and the ground via a DC blocking coupling capacitor 16. The capacitor 20, which has one end of the diode 17 grounded at high frequency, is a bypass capacitor of a bias current supply circuit for supplying bias current to the diodes 17 and 18. Variable resistor 22 for adjustment and high frequency chiyoke coil 2
3.
この第２図の回路において、端子１１に入力さ
れた信号は、トランス１３の中間タツプＣ点にの
み出力され、バイアス電流供給回路から適当なバ
イアス電流が供給された逆並列接続の２個のダイ
オード１７と１８により三次歪を受け、出力端子
１２に出力される。 In the circuit shown in Fig. 2, the signal input to the terminal 11 is output only to the intermediate tap point C of the transformer 13, and the two diodes connected in anti-parallel are supplied with an appropriate bias current from the bias current supply circuit. It is subjected to third-order distortion by 17 and 18 and is output to output terminal 12.
つぎに、入力端子１１からの信号が中間タツプ
Ｃ点にのみ出力される原理について説明する。第
３図ａは通常のハイブリツド回路であり、同図ｂ
は本発明にかかわる回路である。図ａにおいて、
通常のハイブリツドの動作により、１１′及び１
２′に入力された信号は抵抗１４′及び１５により
終端され、１１′に入力した信号は１２′には出力
されず、１２′に入力した信号は１１′に出力され
ない。図ｂの回路はａの回路の変成器部をオート
トランスのみに変えたものであり、省略された一
次側は特性インピーダンスの２倍の抵抗１４に変
換されており、ａと同様のことが言え、入力端子
１１に入力した信号は出力端子１２には出力され
ず、抵抗１４及び１５により終端される。 Next, the principle by which the signal from the input terminal 11 is output only to the intermediate tap point C will be explained. Figure 3a shows a normal hybrid circuit, and Figure 3b shows a normal hybrid circuit.
is a circuit related to the present invention. In figure a,
11' and 1 due to normal hybrid operation.
The signal input to 2' is terminated by resistors 14' and 15, the signal input to 11' is not output to 12', and the signal input to 12' is not output to 11'. The circuit in Figure b is the circuit in Figure A except that the transformer section is replaced with an autotransformer, and the omitted primary side is converted to a resistor 14 that is twice the characteristic impedance, so the same thing can be said as in Figure a. , the signal input to the input terminal 11 is not output to the output terminal 12 and is terminated by the resistors 14 and 15.
次に、端子１１より入力された信号が端子Ｃに
出力され、三次歪を発生させる動作について説明
する。第４図はダイオードの入力電圧電流特性で
あり、図における電流立上りのＢ点付近の特性は
三乗特性として近似出来ることが知られている。
すなわち動作点をＢ点に選んだ場合、三次歪が発
生されることになる。また、この時のダイオード
は非常に高いインピーダンスとなる。 Next, a description will be given of an operation in which a signal inputted from the terminal 11 is outputted to the terminal C to generate third-order distortion. FIG. 4 shows the input voltage and current characteristics of the diode, and it is known that the characteristics near point B of the current rise in the figure can be approximated as a cube characteristic.
That is, if point B is selected as the operating point, third-order distortion will be generated. Also, the diode at this time has a very high impedance.
第５図は第４図Ｂ点に動作点を持つダイオード
２個を互いに逆方向に、かつ並列に接続した場合
の入力電圧電流特性である。この時には、原点を
中心とし、正負の方向に三乗特性を示し、交流信
号に対しては動作点が原点となる為、三次歪を発
生する。 FIG. 5 shows the input voltage and current characteristics when two diodes having their operating points at point B in FIG. 4 are connected in parallel in opposite directions. At this time, a cubic characteristic is exhibited in the positive and negative directions with the origin as the center, and since the operating point is the origin for AC signals, third-order distortion is generated.
従つて、第２図において、信号入力端子１１よ
りＣ点に出力された信号は直流阻止コンデンサ１
６を通り、チヨークコイル２３及びバイアス抵抗
２２を通して直流電源端子２１より電流を流すこ
とにより、第５図の特性を持つ様にバイアスされ
たダイオード１７及び１８に入力される。そし
て、前述した動作により三次歪を発生し、その信
号は再び変成器を通り、出力端子１２より出力さ
れる。この時、前述した様に、ダイオードのイン
ピーダンスは非常に高く、ハイブリツト回路の正
常な動作を妨げない為、すべて抵抗１５により終
端され、信号成分は出力端子１２には出力される
ことはない。 Therefore, in FIG. 2, the signal output from the signal input terminal 11 to point C is connected to the DC blocking capacitor 1.
By passing current from the DC power supply terminal 21 through the DC coil 23 and the bias resistor 22, the current is input to the diodes 17 and 18 which are biased to have the characteristics shown in FIG. Third-order distortion is generated by the above-described operation, and the signal passes through the transformer again and is output from the output terminal 12. At this time, as mentioned above, the impedance of the diode is very high, and in order not to interfere with the normal operation of the hybrid circuit, all of the signals are terminated by the resistor 15, and no signal component is output to the output terminal 12.
以上説明した様に、本発明はハイブリツドのア
イソレーシヨン特性を利用し、主信号のキヤンセ
ルを図るとともに、歪発生部にダイオードを使用
することにより、回路の単純化による調整方法の
改善、部品点数の減少による信頼性の向上、価格
の低減が実現出来るという利点がある。 As explained above, the present invention utilizes the isolation characteristics of hybrids to cancel the main signal, and also uses diodes in the distortion generating section to simplify the circuit, improve the adjustment method, and reduce the number of parts. This has the advantage of improving reliability and reducing cost due to the reduction in .
第１図は前置歪発生器のブロツク回路図、第２
図は本発明の一実施例の回路図、第３図は本発明
の動作原理を説明するための図で、図ａは通常の
ハイブリツド回路、図ｂは本発明にかかわるハイ
ブリツド回路を示す図である。第４図は１個のダ
イオードの電圧電流特性図、第５図は逆並列接続
の２個のダイオードの電圧電流特性図である。
１１……入力端子、１２……出力端子、１３…
…オートトランス、１４……オートトランス橋絡
抵抗、１５……中間タツプ終端抵抗、１６……直
流阻止結合コンデンサ、１７，１８……逆並列の
２個のダイオード、２０……バイパスコンデン
サ、２１……バイアス電源端子、２２……チヨー
クコイル、２３……可変抵抗。
Figure 1 is the block circuit diagram of the predistortion generator, Figure 2 is the block diagram of the predistortion generator.
The figure is a circuit diagram of one embodiment of the present invention, Figure 3 is a diagram for explaining the operating principle of the present invention, Figure a is a diagram showing a normal hybrid circuit, and Figure b is a diagram showing a hybrid circuit related to the present invention. be. FIG. 4 is a voltage-current characteristic diagram of one diode, and FIG. 5 is a voltage-current characteristic diagram of two diodes connected in antiparallel. 11...Input terminal, 12...Output terminal, 13...
... Autotransformer, 14 ... Autotransformer bridging resistance, 15 ... Intermediate tap termination resistor, 16 ... DC blocking coupling capacitor, 17, 18 ... Two anti-parallel diodes, 20 ... Bypass capacitor, 21 ... ...Bias power supply terminal, 22...Chiyoke coil, 23...Variable resistor.
Claims (1)
前記入出力端子間に接続された、特性インピーダ
ンスの２倍の抵抗値をもつ抵抗と、前記オートト
ランスの中間タツプとアース間に接続された、特
性インピーダンスの1/2の抵抗値をもつ抵抗とに
より構成されたハイブリツド回路と；このハイブ
リツド回路の前記中間タツプとアースとの間に、
直流阻止コンデンサを介して接続された、バイア
ス電流供給回路をもつた逆並列のダイオードとを
備えたことを特徴とする三次歪発生器。1 An autotransformer with input and output terminals at both ends,
A resistor with a resistance value twice the characteristic impedance connected between the input and output terminals, and a resistor with a resistance value 1/2 the characteristic impedance connected between the intermediate tap of the autotransformer and the ground. between the intermediate tap of this hybrid circuit and the ground,
A third-order distortion generator comprising: antiparallel diodes with a bias current supply circuit connected through a DC blocking capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP945179A JPS55102908A (en) | 1979-01-30 | 1979-01-30 | Ternary distortion generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP945179A JPS55102908A (en) | 1979-01-30 | 1979-01-30 | Ternary distortion generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55102908A JPS55102908A (en) | 1980-08-06 |
| JPS6156889B2 true JPS6156889B2 (en) | 1986-12-04 |
Family
ID=11720647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP945179A Granted JPS55102908A (en) | 1979-01-30 | 1979-01-30 | Ternary distortion generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55102908A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1190607A (en) * | 1983-05-31 | 1985-07-16 | Stephen G. Harman | Signal cuber |
-
1979
- 1979-01-30 JP JP945179A patent/JPS55102908A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55102908A (en) | 1980-08-06 |
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