JPS6158052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a competition control circuit for two mutually asynchronous signals.

The two mutually asynchronous signals include, for example, a signal that instructs a write or read operation in a storage device using a dynamic MOS type IC memory as a storage medium, and a signal that instructs a refresh operation. The storage device executes each operation according to these operation requests, but since it cannot execute two operations at the same time, when two signals occur simultaneously, it selects and executes one operation. This selection is performed by a competition control circuit. The contention control operation in the contention control circuit is performed when the time relationship between the two signals is constant, that is, they are synchronized, for example, when the circuits or devices that generate each signal are operated by the same or synchronized clock signals. It's relatively easy.

However, there are cases where the two signals have to be completely asynchronous. For example, a storage device that uses a magnetic core as a storage medium is called Dynamic MOS.
This is a case where the IC memory must be replaced with a storage device as the storage medium and the conventional interface must be preserved. In such a case, the refresh request generation circuit must be provided inside the storage device, and this refresh request generation circuit has an oscillator built into itself to respond to write or read requests from the outside to the storage device. A refresh request is generated asynchronously and independently of the signal that requires operation.

FIG. 1 shows a conventional contention control circuit in which the read or write request signal and the refresh request signal are completely asynchronous. In FIG. 1, signal A is a signal requesting a read or write operation to the storage device, and is input to a data input terminal D (D terminal) of flip-flop F1. Signal B is a refresh request signal generated within the storage device and is input to the D terminal of flip-flop F2. Clock C
and C are two-phase clock signals shown in FIG. 2 generated within the storage device to perform priority control operations for signals A and B, and are clock signals at the clock terminals of flip-flops F1, F4 and F2, F3, respectively.
Added to CP (CP terminal). When a clock signal is applied to the CP pin of each flip-flop,
It captures the state of the signal being input to the D terminal at that time and outputs it. From clock C to C,
The time from clock C to C is signal A, B,
It is necessary that the time t _t required for the transient phenomenon in flip-flops F1 and F2 caused by the asynchronousness of C and C to subside is sufficiently larger than the time t t . FIG. 3 shows the transient phenomenon of a flip-flop, and shows the relationship between the CP input width and the Q output.

FIG. 2a shows the case where signal A is accepted, and signals A and B arrive simultaneously within the time from the rising edge of clock C to the rising edge of clock C. FIG. Flip-flop F1 is set at clock C and F2 is set at clock C. When F1 is set, AND gate G1 is opened, and F3 is also set at C time. Since F1 is set, F4 is not set because AND gate G2 is closed. FIG. 2b shows the case where signal B is accepted, and signals A and B arrive simultaneously within the time from the rising edge of clock C to the rising edge of clock C. FIG. First, F2 is set, then F1 is set, and then F4 is set, but F3 is
Inhibited by 2 outputs and not set.

If the rising edge of signal A or B and the rising edge of signal C or C are very close to each other, the phenomenon shown in Fig. 3 will appear at the output of F1 or F2, but the time interval between C and C will be different from that described above. If so, only either F3 or F4 will be set no matter what time A and B rise.

Now, in this circuit, the access time of the storage device is lengthened by a maximum of C or a period of C. Therefore, it is desirable that the periods of clocks C and C be as short as possible. Applications such as the main memory of electronic computers usually require a clock frequency of 10-10 _MHZ to several tens of _MHZ , but generating such a high-frequency clock requires an expensive circuit such as a crystal oscillator circuit. It is.

An object of the present invention is to provide a contention control circuit that is independent of clocks.

FIG. 4 shows an embodiment of the present invention. Signals A and B are two signals subject to competition control as in FIG. 1; for example, signal A is a read or write request signal, and signal B is a refresh request signal. Signal A is input to AND gate G3, and signal B is input to AND gate G4 via delay circuit DL, and is inverted by an inverter and input to AND gate G3. The output of AND gate G3 is input to the CP terminal of flip-flop F5. A high level signal indicated by H is always applied to the D terminal of the flip-flop F5, and is set when a signal is applied to the CP terminal. AND gate G3 has signal A and signal B
is opened when not present, sets flip-flop F5, and indicates that signal A is received at set output Q of flip-flop F5. The reset output of flip-flop F5 is applied to AND gate G4, which opens when flip-flop F5 is in the reset state and signal B is applied, setting flip-flop F6.
The delay time of the delay circuit DL is the flip-flop F
5 (t _d in FIG. 5). After receiving and processing one request, flip-flops F5 and F6 are reset by a signal to the reset terminal (R terminal) so as to accept the next request.

In FIG. 4, if signal A is generated first, AND gate G3 is opened, flip-flop F5 is set, and signal A is accepted. By setting flip-flop F5,
AND gate G4 is closed, and even if signal B is generated thereafter, it will not be accepted. Conversely, signal B
is generated first, flip-flop F6 is set through AND gate G4 and signal B is accepted, but signal A is not accepted because AND gate G3 is closed.

The case where signals A and B conflict is shown in the time chart of FIG. As described above, the waveform shown in FIG. 3 is generated at the output of flip-flop F5, but the output level is determined after time t _d (>t _t ) (in this example, F5 is set). )
Signal B is delayed by the delay circuit DL for a period of time td _{or more} and reaches the AND gate G4, but the flip-flop F6 is not set because the input to the AND gate G4 is inhibited by the output signal of the flip-flop F5. Conversely, if flip-flop F5 is not set, flip-flop F6 is set because the input of AND gate G4 is open.

As described above, according to the present invention, mutually asynchronous signals can be reliably controlled competitively without using a clock.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional competition control circuit, FIG. 2 is a time chart explaining FIG. 1, FIG. 3 is a diagram showing the relationship between the input pulse width of a flip-flop and the output waveform, and FIG. A diagram showing an example of
FIG. 5 is a time chart explaining FIG. 4. F1-F6...Flip-flop, G1-G4...
AND gate,...inverter, DL...delay circuit.

Claims (1)

[Claims] 1. A circuit for controlling competition between two mutually asynchronous signals, first and second bistable means each indicating reception of the first and second signals;
means for setting the first bistable means based on an AND condition of the inverted signal of the first signal and the second signal; and a delayed signal of the second signal and the first bistable means. A contention control circuit comprising means for setting the second bistable means based on an AND condition with a reset output signal of the second bistable means.