JPS6158920B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control scheme for shift register-like memories such as magnetic bubble memories and charge-coupled device (CCD) memories.

Conventional addressing methods and access methods will be explained below, taking a magnetic bubble memory device (hereinafter abbreviated as bubble memory) as an example.

FIG. 1 is a block diagram of a bubble chip group of an example of a conventional bubble memory.

Normally, bubble memory is as shown in Figure 1.
It is composed of multiple bubble chips.

In FIG. 1, 1 is a bubble chip, 2 is a bubble chip,
3 is a minor loop for storing information; 4 is a minor loop for transferring information to and from the outside;
is a bubble chip group consisting of a plurality of bubble chips 1.

Within the same bubble chip group 4, memory information located at the same position on the minor loop 2 at the same position on the major loop 3 of each bubble chip 1 is read from and written to an external device at the same timing. In other words, these are the smallest units of access from external devices, and are usually called "words."
It is called.

When accessing bubble memory from an external device, the number of bubble chip group 4 (chip group address
CHA), position number of minor loop 2 in bubble chip 1 (major loop 3) (major address
MJA) and the position number within minor loop 3 (minor address MNA).

The access method is to send these addresses from the external device for each word, and only the first address to be accessed is sent from the external device, the number of words to be transferred is managed by the external device, and the transfer end instruction is sent to the external device. There are two methods, one for sending data from the other. In either case, the information necessary for access is the chip group address CHA, the media address
There are three types of addresses, MJA and minor address MNA, which represent an "address" of memory information.

A specific access operation will be explained using the former method described above.

For example, when writing to address A in FIG. 1 from an external device, it is sufficient to give chip group address #0, major address #2, and minor address #4. In this case, the information contained in the major address #2 and minor address #4 in each chip 1 moves on the minor loop 2 and is simultaneously transferred onto the major loop 3 in each chip 1, When the information of address A passes through position X, all the information is erased. Furthermore, when passing another specific position Y, information from an external device is written. The information on the major loop 3 is transferred to the minor loop 2 again, and this series of operations ends. Furthermore, depending on the method, the series of operations may be completed by moving to the reference position within the minor loop.

On the other hand, with advances in semiconductor technology, bubble chips are becoming increasingly highly integrated, and the technological innovation is remarkable. With this increase in integration, the internal configuration of bubble chips has changed from not only the conventional major-loop/minor-loop bubble chip shown in Figure 1, but also the minor-loop/major-line bubble chip, which is easy to manufacture and requires short access time. It has appeared.

FIG. 2 is a diagram showing the configuration of a bubble chip group as an example of the minor loop/major line system.

Here, 10 is a bubble chip, and 20 is a minor loop, which plays the same role as the conventional example. 30
is a major line for reading, and 40 is a major line for writing.

When using this bubble chip and following the same access method as in the previous example, the control method is as follows.

As in the case of FIG. 1, when writing only address B, the information first moves on the minor loop 20, and all the information of each bubble chip 10 having the same minor address is transferred to the major line 30 for reading. It can be done.

These pieces of information are once taken out of the bubble chip 10 from point K in the figure, and then transferred to the bubble chip 1.
Buffling is performed in the electronic circuit around 0,
With the information from the external device written in a predetermined position, the information is returned to the bubble chip 10 from point L in the figure using the writing major line 40, and is transferred from this major writing line to the minor loop 20. must be done.

Therefore, the electronic circuit around the bubble chip 10 is (number of minor loops in the bubble chip) x (1
This requires a buffer memory equal to the number of bits constituting the word, and also requires a mechanism for accessing the buffer memory, which is a big sacrifice.

As described above, it can be seen that when a minor loop/major line type bubble chip is used, a considerable amount of hardware is required to perform the function of modifying a specific address among information addresses having the same minor address in the bubble memory. Furthermore, as bubble chips become more highly integrated, the amount of these metals increases.
It becomes more of a burden.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide an economical memory access control system for memory devices comprising not only conventional shift register-like memory chips but also new types of chips.

In short, with the aim of realizing a partial rewrite function inside the memory with a small amount of hardware, the main body of the memory is accessed using only the minor address, information at the same minor address is transferred to the host device in bulk, and the information at the same minor address is This method is characterized by rewriting part of the address information with a designated measure address.

The memory access control method according to the present invention uses one or more memory chip groups each consisting of a plurality of memory chips each having one or more shift register-like major addresses, each including a plurality of shift register-like minor addresses. In a memory access control method for a memory device, the memory device has a memory main body composed of two memory chips, and configures memory information of a minor address within the same major address of each memory chip in the same memory chip group as one word of the address. When accessing the memory and reading or writing memory information related to the desired address, specify the memory chip group address and the minor address related to the desired address to the memory main body, and read all major addresses of the memory chip group address. transfers and stores the memory information of the minor address included in the control unit, and the control unit reads out the memory information of the minor address related to the major address among these memory information and transfers it to an external device, or After rewriting, those memory information, conversely,
The information is transferred and stored in the memory itself again.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a bubble memory will be taken up as an embodiment of the present invention and will be described in detail with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the memory access control method according to the present invention.

Here, 100 is a memory section, 101 is a memory main body consisting of a plurality of bubble chips, and 102 is
103 is a transfer control circuit that controls data transfer; 200 is a control unit; 201 is a memory unit 10;
202 is a data register that sends and receives data to and from an external device, for example, a data channel DCH; 203 is a memory data register that sends and receives data to and from the memory data register 20;
1 and an arithmetic circuit 204 that performs calculations and processes related to the contents of the data register 202, is a measure address register that stores a measure address MJA.

FIG. 4 is an operational state diagram of memory data register 201 and data register 202 in FIG. 3.

Here, BREG is the memory data register 20
1, CREG is an abbreviation indicating the data register 202.

Next, the operation of an embodiment of the memory access control method according to the present invention will be described based on FIGS. 3 and 4.

When reading bubble memory from the data channel DCH (not shown), the data channel
Data from DCH is stored in data register 2.
It is received and stored at 02.

This data is processed by the arithmetic circuit 203 and sent to the memory unit 1 via the memory data register 201.
Sent to 00.

First, data channel DCH from bubble memory
When performing a read operation to the data channel
The desired address of the bubble memory is sent from the DCH.

The desired address of bubble memory is the major address.
It consists of MJA, minor address MNA, and chip group address CHA, but major address MJA is
The major address register 204 stores the minor address MNA and chip group address CHA.
are stored at corresponding locations in the address register 102 of the memory section 100, respectively.

Next, in the memory unit 100, based on the chip group address CHA and the minor address MNA stored in the address register 102,
Access to the bubble memory main body is performed, and the designated chip group address is accessed via the transfer control circuit 103.
For all major addresses MJA in the CHA, read data of the same minor address MNA as the designated minor address MNA is transferred to the control unit 200 and stored in the memory data register 201 thereof. This is the state indicated by a in FIG. 4.

Next, as shown in FIG. 4b, from this data, a desired measure address is selected based on the measure address MJA (#3 in the example in FIG. 4) specified in the measure address register 204.
Only the data of the minor address MNA related to MJA is transferred and stored in the data register 202 through the processing of the arithmetic circuit 203.

In the next cycle, the contents of the data register 202 are transferred to the data channel DCH, and the contents of the data register 202 become empty and enter the state c. That is, the data at the desired address has been read out to the data channel DCH.

Furthermore, in the next cycle, the contents of the memory data register 201 are retransferred to the memory main body 101 via the transfer control circuit 103 and restored in the bubble chip. As a result, the memory data register 201 also becomes empty and enters the state d.

When performing a write operation from the data channel DCH to the bubble memory, similarly to the read operation, data from the data channel DCH is first received by the data register 202, and this data is processed through the processing of the arithmetic circuit 203. Out of the desired address data through the memory data register 201,
The measure address MJA is stored in the measure address register 204 as well as the chip group address CHA.
and the minor address MNA are received and stored in the address register 102.

Next, the write data is accumulated in the data register 202 through the processing of the arithmetic circuit 203 based on the contents of the measure address register 204, resulting in a state as shown in e in FIG. 4.

Next, the chip group address CHA and minor address stored in the address register 102 are
Based on MNA, from the bubble memory body 101,
For all major addresses MJA in the specified chip group address CHA, the specified minor address MNA
Data at the same minor address MNA is read out, received and stored in the memory data register 201 via the transfer control circuit 103, resulting in the state shown in FIG. 4f.

Furthermore, the contents of the data register 202 and the memory data register 201 are processed by the arithmetic circuit 203, and the contents of the desired mean address MJA (#5 in the example in FIG. 4) in the memory data register 201 are transferred to the channel data register 203.
The contents of the desired medium address MNA in 2 are rewritten, and the state becomes state g.

The contents of this memory data register 201 are retransferred and stored in the memory main body 101 via the transfer control circuit 103, and the desired data is written to the desired address. As a result, the memory data register 201 and the data register 202 become empty and enter the state h.

Note that, as explained above, the memory unit 100
Data transfer is performed in units of (number of major addresses, ie, minor loops in a bubble chip) x (number of bits constituting one word, ie, number of bubble chips in a group of bubble chips).

As described above in detail, according to the present invention, in particular, the partial write process in the bubble memory is
This can be done by a higher-level external device, such as a data channel device or central processing unit, but
These devices can process data one to two orders of magnitude faster than bubble memory, so there is virtually no hardware burden on the host device, and bubble memory can also be used to increase the amount of hardware. does not require.

Therefore, as an access control method for this type of memory device that requires a large number of systems, its economical effects are extremely significant.

Although the above embodiments have been explained using bubble memories as an example, it is clear that the present invention can also be easily applied to, for example, charge-coupled memories made of chips having the same structure as bubble chips.

[Brief explanation of the drawing]

FIG. 1 is a bubble chip group configuration diagram of an example of a conventional bubble memory, FIG. 2 is a bubble chip group configuration diagram of an example of a minor loop/major line method, and FIG. 3 is an implementation of a memory access control method according to the present invention. The example block diagram, FIG. 4, is an operational state diagram of the bubble data register and channel data register in FIG. 100...Memory part, 101...Memory body,
102...Address register, 103...Transfer control circuit, 200...Control unit, 201...Memory data register, 202...Data register, 20
3...Arithmetic circuit, 204...Measure address register.

Claims (1)

[Scope of Claims] 1. Constructed using one or more memory chip groups each consisting of a plurality of memory chips consisting of one or more shift register-like major addresses each containing a plurality of shift register-like minor addresses. In a memory access control method for a memory device that has a memory body and configures memory information of a minor address within the same major address of each memory chip in the same memory chip group as one word of the address, the memory device is accessed from an external device. , when reading or writing memory information related to the desired address, the memory chip group address and minor address related to the desired address are specified in the memory main body, and the memory information included in all the major addresses of the memory chip group address is specified. After the memory information of the minor address is transferred and stored in the control unit, and the control unit reads out the memory information of the minor address related to the major address among these memory information and transfers it to an external device or rewrites it. , a memory access control method characterized in that, conversely, the memory information is retransferred and stored in the memory main body. 2 In claim 1, the control unit:
At least, specify a data register that transfers and stores data between external devices, a chip group address and a minor address for the memory main body, and also specifies data registers that transfer and store data between the memory main body and the memory main body. A memory access control system that consists of a memory data register for processing, a measure address register for storing measure addresses, and an arithmetic circuit that processes the data in these registers. 3. The memory access control method according to claim 1 or 2, wherein the memory main body is composed of a magnetic bubble memory chip of a major loop/minor loop type or a minor loop/major line type. 4. The memory access control system according to claim 1 or 2, wherein the memory main body is composed of a charge-coupled device memory chip.