JPS6159012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit using a combination of MOS transistors. In particular, the present invention relates to a semiconductor logic circuit suitable for CMOS integrated circuits, which obtains a plurality of logic outputs from a NAND circuit having N (positive integer) inputs.

[Conventional technology]

A conventional configuration diagram of this type of circuit is shown in FIG.
Considering only column a in Figure 1, there are N MOS transistors Q ₁ to Q _N , the drain of transistor Q ₁ is connected to the source of transistor Q ₂ , and the drain of transistor Q ₂ is connected to the same source.
The source of _Q3 is connected in a line up to the transistor _QN . The source of the transistor Q ₁ is connected to ground (or the opposite polarity power supply), and the drain of the transistor Q _N is connected to the power supply V _CC via a load MOS transistor L _N . If the gates of the transistors Q ₁ -Q _N are set as N inputs A ₁ -A _N and the drain of the transistor Q _N is set as the output X _N , an N-input NAND circuit is obtained.

That is, the output X _N is "0" (ground potential) only when all of the inputs A ₁ to A _N are "1", and the output X _N is "1" in other cases. Express this as a logical formula It can be expressed as.

Here, in addition to the output X _N , If this is required, a configuration as shown on the right side of FIG. 1b is required. As an example _, in _the simplest case of _K = ₂ in the above _equation (3), It will be done. The output X ₁ according to FIG. 1d is the inverted signal of the input A ₁ .

[Problem that the invention seeks to solve]

Therefore, if an output X _N is to be obtained in addition to the output X _N , K MOS transistors must be added for each output X _N .

For this reason, a logic circuit has been proposed in which transistors of the same conductivity type are connected in series and a load transistor is connected to each connection point. (For example, IBM Technical Disclosure Bulletin vol.18
(No. 10 March 1976, page 3325) However, it has been proposed to connect this load transistor to each connection point to distribute the load and take out the output.
It is not easy to apply it to CMOS transistors because there is no load in CMOS circuits.

In other words, in the case of a CMOS circuit, an N-type transistor and a P-type transistor are paired, and output is obtained by turning them on and off exclusively, so a pair of N-type and P-type transistors is required. do.

For this reason, conventional logic circuits constructed using CMOS have the disadvantage of having a very large number of elements.

The present invention solves this drawback, and the output X _N
Another object of the present invention is to provide a CMOS logic circuit that can obtain a logic output X _K by adding a small number of CMOS transistors.

[Means for solving problems]

The present invention is characterized in that N pieces of one conductivity type are connected in series.
MOS transistors Q ₁ to Q _N and this one conductivity type
N reverse conductivity type MOS transistors D N1 to _D N connected to one end of the Nth MOS transistor Q _N among the MOS transistors and connected in parallel with each other _.
N , means for applying a first voltage to the N MOS transistors of opposite conductivity type, and means for applying a first voltage to the N MOS transistors of one conductivity type;
means A ₁ to A _N for supplying the same input signal to one of the MOS transistors and one of the N opposite conductivity type MOS transistors, and one end of the first MOS transistor among the one conductivity type MOS transistors; a second voltage applying means for applying a second voltage to the connection point between the K-th one-conductivity type MOS transistor Q _K and the K+1-th one-conductivity type MOS transistor Q _K+1 ; K opposite conductivity types connected in parallel with one voltage application means
MOS transistors D _K1 to D _KK , and the above K
Each of the opposite conductivity type MOS transistors is supplied with the same input signal as the input signal supplied to the first to Kth one conductivity type MOS transistors.

[Effect]

First N-type MOS transistor _Q1 and P-type
Input A ₁ in pair with MOS drive transistor D ₁
The output is taken out to _X1 .

K-th N-type MOS transistor Q _K and K P-type MOS transistors D _K1 ~ D _KK are input A ₁ ~
The output is taken out by configuring a NAND circuit of _AK . In this way, the inputs A ₁ to A _N are input to the outputs X ₁ to X _N
The NAND output of is retrieved.

〔Example〕

Examples of the present invention will be described below.

FIG. 2 shows a circuit diagram of an embodiment using a CMOS transistor of the present invention.

The drains and sources of adjacent N type MOS transistors Q ₁ to Q _N are connected to each other. The drain of the P-type MOS transistor D _N1 is connected to the drain of the Nth transistor Q _N , the gates of both are connected to the same input terminal A _N , and the power supply V _CC is connected to the source of the P-type MOS transistor D _N1 . and both transistors D _N1 and Q _N
constitutes a CMOS inverter. Similarly, drive transistors D 1 _to D _NN of P-type MOS transistors are connected in parallel between the power supply V _CC and the connection point between the N-type MOS transistors Q ₁ to Q _N and the connection point between Q _N and _{D N1} . It is connected. The drive transistors D ₁ to D _NN are each configured to be controlled by an input signal from the previous stage.

That is, the Kth N-type MOS transistor Q _K
K P-type MOS transistors are connected in parallel between the connection point between the K+1 transistor Q _K+1 and the power supply V _CC , and the gate of the P-type transistor D _K1 is connected to the input A Similarly, the _gate of D _K2 is connected to the inputs up to the previous stage, such as the input A _K - ₁ , and is controlled by the drive transistors D _K1 to D _KK and the transistor Q _K
The configuration is such that an output X _K is output from.

With this configuration, the number of drive transistors can be reduced to about half compared to the conventional circuit shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, for the same logic circuit output, MOS
The number of transistors can be reduced.

That is, the number of transistors can be reduced by half compared to the conventional circuit shown in FIG. 1, which has the effect of reducing the number of elements in the CMOS circuit and reducing the area occupied by the integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional circuit. FIG. 2 is a configuration diagram of a circuit according to an embodiment of the present invention.

Claims (1)

[Claims] 1 N MOS transistors of one conductivity type Q ₁ to Q _N connected in series, and connected to one end of the Nth MOS transistor Q _N among these MOS transistors of one conductivity type and connected in parallel with each other. N connected reverse conductivity type MOS transistors D _N1 to D _NN ; means for applying a first voltage to the N reverse conductivity type MOS transistors; and one of the N single conductivity type MOS transistors. and means A ₁ to _{A N} for supplying the same input signal to one of the N reverse conductivity type MOS transistors.
and a second voltage applying means for applying a second voltage to one end of the first MOS transistor of the one conductivity type MOS transistor, and a K-th one conductivity type MOS transistor Q _K
K opposite conductivity type MOS transistors D K1 to D KK connected in parallel between the connection point between the K+1st one conductivity type MOS transistor Q _{K+1 and} the first voltage application _means ; A semiconductor logic circuit, characterized in that each of the K opposite conductivity type MOS transistors is supplied with the same input signal as the input signal supplied to the first to Kth one conductivity type MOS transistors.