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JPS6159675B2 - - Google Patents
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JPS6159675B2 - - Google Patents

Info

Publication number
JPS6159675B2
JPS6159675B2 JP55005845A JP584580A JPS6159675B2 JP S6159675 B2 JPS6159675 B2 JP S6159675B2 JP 55005845 A JP55005845 A JP 55005845A JP 584580 A JP584580 A JP 584580A JP S6159675 B2 JPS6159675 B2 JP S6159675B2
Authority
JP
Japan
Prior art keywords
film
oxide film
silicon nitride
gate
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55005845A
Other languages
Japanese (ja)
Other versions
JPS56104468A (en
Inventor
Masaki Yoshimaru
Masayoshi Ino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP584580A priority Critical patent/JPS56104468A/en
Publication of JPS56104468A publication Critical patent/JPS56104468A/en
Publication of JPS6159675B2 publication Critical patent/JPS6159675B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/13Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Non-Volatile Memory (AREA)

Description

【発明の詳細な説明】 この発明はMOS型半導体装置の製造方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a MOS type semiconductor device.

MOS型半導体装置の従来の製造方法を第1図
により説明する。従来は、まず半導体基板たとえ
ばシリコン基板1上にゲート酸化膜2を300〜
1000Å厚に形成し、その上には不純物を含んだ多
結晶シリコン膜3を3000〜5000Å厚に形成する。
さらに、多結晶シリコン膜3上に200〜500Å厚の
薄い酸化膜4を形成し、その上にはシリコン窒化
膜5を1000〜2000Å厚に形成する。(第1図a参
照) 次に、能動領域6のみを残し、他はシリコン窒
化膜5、薄い酸化膜4、多結晶シリコン膜3、ゲ
ート酸化膜2を順に除去する。また、ゲート酸化
膜2の除去前もしくは除去後に素子間分離のた
め、シリコン基板1と同じ不純物たとえばボロン
を能動領域6以外のシリコン基板1全面にイオン
インプラにより打込み、素子間分離のための不純
物拡散領域7を形成する。(第1図b参照) 次に、素子間分離のための6000〜10000Å厚の
厚い熱酸化膜8をシリコン基板1上に形成する。
この時、多結晶シリコン膜3の側面も酸化されて
しまう。したがつて、能動領域6の幅が小さくな
つてしまう。同時に、多結晶シリコン膜3の側面
が酸化されて膨張することにより酸化膜の突起9
ができてしまう。(第1図c参照) 続いて、能動領域6内でゲート領域10のみを
残し、他の能動領域6に対してはシリコン窒化膜
5、薄い酸化膜4、多結晶シリコン膜3、ゲート
酸化膜2の除去を行う。さらに、全面に不純物た
とえばリンの拡散を行い、ソース・ドレイン領域
となる不純物拡散領域11をシリコン基板1内に
形成する。(第1図d参照) 次に、熱酸化により、ソース・ドレインとなる
不純物拡散領域11上に中間絶縁膜となる酸化膜
12を形成する。この時、ゲート領域10の多結
晶シリコン膜3の側面も酸化されてしまい、ゲー
ト長およびゲート幅が小さくなつてしまう。同時
に、多結晶シリコン膜3の側面が酸化されて膨張
することにより、酸化膜の突起13ができてしま
う。(第1図e参照) 続いて、ゲート領域10上のシリコン窒化膜5
を除去する。また、その下の薄い酸化膜4も除去
する。そして、多結晶シリコン膜3、熱酸化膜8
および酸化膜12上にメタルの配線たとえばAl
配線14を形成することにより、メタル配線とゲ
ートとのセルフアラインコンタクトがなされる。
(第1図f参照) しかるに、このような従来の製造方法では、先
に述べたように、厚い熱酸化膜8の形成時さらに
は酸化膜12の形成時に多結晶シリコン膜3の側
面も酸化されてしまうので、能動領域6の幅さら
にはゲート長、ゲート幅を精度よく制御すること
ができない欠点を有する。また、上記酸化による
多結晶シリコン膜3側面の膨張により突起9,1
3ができるので、表面が凹凸になる欠点を有する
ものである。
A conventional method for manufacturing a MOS type semiconductor device will be explained with reference to FIG. Conventionally, a gate oxide film 2 is first formed on a semiconductor substrate, such as a silicon substrate 1, with a thickness of 300 to 300 nm.
A polycrystalline silicon film 3 containing impurities is formed thereon to a thickness of 3000 to 5000 Å.
Furthermore, a thin oxide film 4 having a thickness of 200 to 500 Å is formed on the polycrystalline silicon film 3, and a silicon nitride film 5 is formed thereon to a thickness of 1000 to 2000 Å. (See FIG. 1a) Next, leaving only the active region 6, the silicon nitride film 5, thin oxide film 4, polycrystalline silicon film 3, and gate oxide film 2 are sequentially removed. In addition, before or after removing the gate oxide film 2, the same impurity as the silicon substrate 1, such as boron, is implanted into the entire surface of the silicon substrate 1 other than the active region 6 by ion implantation in order to isolate the elements. Region 7 is formed. (See FIG. 1b) Next, a thick thermal oxide film 8 having a thickness of 6000 to 10000 Å is formed on the silicon substrate 1 for isolation between elements.
At this time, the side surfaces of the polycrystalline silicon film 3 are also oxidized. Therefore, the width of the active region 6 becomes smaller. At the same time, the side surface of the polycrystalline silicon film 3 is oxidized and expands, causing protrusions 9 of the oxide film.
is created. (See Figure 1c) Next, leaving only the gate region 10 in the active region 6, the other active regions 6 are covered with a silicon nitride film 5, a thin oxide film 4, a polycrystalline silicon film 3, and a gate oxide film. Perform the removal of 2. Further, an impurity such as phosphorus is diffused over the entire surface to form impurity diffusion regions 11 that will become source/drain regions in the silicon substrate 1. (See FIG. 1d) Next, by thermal oxidation, an oxide film 12, which will become an intermediate insulating film, is formed on the impurity diffusion regions 11, which will become the source and drain. At this time, the side surfaces of the polycrystalline silicon film 3 in the gate region 10 are also oxidized, resulting in a reduction in gate length and gate width. At the same time, the side surfaces of the polycrystalline silicon film 3 are oxidized and expanded, resulting in the formation of protrusions 13 of the oxide film. (See FIG. 1 e) Next, the silicon nitride film 5 on the gate region 10 is
remove. The thin oxide film 4 underneath is also removed. Then, polycrystalline silicon film 3, thermal oxide film 8
and metal wiring on the oxide film 12, for example, Al.
By forming the wiring 14, a self-aligned contact between the metal wiring and the gate is made.
(See FIG. 1 f.) However, in such a conventional manufacturing method, as mentioned above, when forming the thick thermal oxide film 8 and furthermore when forming the oxide film 12, the side surfaces of the polycrystalline silicon film 3 are also oxidized. Therefore, there is a drawback that the width of the active region 6, as well as the gate length and gate width cannot be precisely controlled. Further, due to the expansion of the side surface of the polycrystalline silicon film 3 due to the oxidation, the protrusions 9 and 1
3, it has the disadvantage that the surface becomes uneven.

この発明は上記の点に鑑みなされたもので、能
動領域幅さらにはゲート長、ゲート幅の制御を精
度よく行うことができ、しかも表面を滑らかにす
ることができるMOS型半導体装置の製造方法を
提供することを目的とする。
The present invention has been made in view of the above points, and provides a method for manufacturing a MOS type semiconductor device that can accurately control the active region width, gate length, and gate width, and can also have a smooth surface. The purpose is to provide.

以下この発明の実施例を図面を参照して説明す
る。第2図はこの発明の実施例を示す図である。
実施例では、まず半導体基板たとえばシリコン基
板21上にゲート酸化膜22を300〜1000Å厚に
形成し、その上には不純物を含んだ多結晶シリコ
ン膜23を3000〜5000Å厚に形成する。さらに、
多結晶シリコン膜23上に200〜500Å厚の薄い酸
化膜24を形成し、その上にはシリコン窒化膜2
5を1000〜2000Å厚に形成する。(第2図a参
照) 次に、多層膜(ゲート酸化膜22,多結晶シリ
コン膜23,薄い酸化膜24およびシリコン窒化
膜25からなる)を能動領域26のみ残し、他は
シリコン窒化膜25、薄い酸化膜24、多結晶シ
リコン膜23、ゲート酸化膜22を順に除去す
る。また、ゲート酸化膜22の除去前もしくは除
去後に素子間分離のため、シリコン基板21と同
じタイプの不純物たとえばボロンをイオンインプ
ラにより打込み、能動領域26以外のシリコン基
板21に素子間分離のための不純物拡散領域27
を形成する。(第2図b参照) 次に、熱酸化により、多結晶シリコン膜23の
側面に薄い酸化膜28を形成し、さらに全面にシ
リコン窒化膜29を1000〜2000Å厚に形成する。
この場合、薄い酸化膜28は、能動領域26以外
のシリコン基板21表面にもできる。(第2図c
参照) その後、シリコン窒化膜29をドライエツチン
グたとえばスパツタエツチングで除去する。この
場合、条件を適当に選ぶことにより、能動領域2
6の多結晶シリコン膜23の上面にシリコン窒化
膜25を、また側面にシリコン窒化膜29を残す
ことができる。次に、能動領域26以外のシリコ
ン基板21表面の薄い酸化膜28を除去する。
(第2図d参照) 次いで、熱酸化により、素子間分離のための厚
い酸化膜30を、能動領域26周囲のシリコン基
板21表面に形成する。この時、能動領域26内
の多結晶シリコン膜23は、側面もシリコン窒化
膜29で覆われているため横方向酸化がない。し
たがつて、能動領域26の幅が減少せず、また多
結晶シリコン膜23の側面酸化により発生する酸
化膜の突起も発生しない。(第2図e参照) 続いて、能動領域26内でゲート領域31のみ
多層膜を残し、他の能動領域26に対してはシリ
コン窒化膜25,29、薄い酸化膜24、多結晶
シリコン膜23、ゲート酸化膜22の除去を行
う。さらに、全面に不純物たとえばリンの拡散を
行い、ソース・ドレイン領域となる不純物拡散領
域32をシリコン基板21内に形成する。(第1
図f参照) 次に、熱酸化により、ゲート領域31の多結晶
シリコン膜23の側面と不純物拡散領域32上に
薄い酸化膜33を形成し、さらに全面にシリコン
窒化膜34を形成する(第2図g参照)。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the invention.
In this embodiment, first, a gate oxide film 22 is formed to a thickness of 300 to 1000 Å on a semiconductor substrate, such as a silicon substrate 21, and a polycrystalline silicon film 23 containing impurities is formed thereon to a thickness of 3000 to 5000 Å. moreover,
A thin oxide film 24 with a thickness of 200 to 500 Å is formed on the polycrystalline silicon film 23, and a silicon nitride film 2 is formed on it.
5 to a thickness of 1000 to 2000 Å. (See FIG. 2a) Next, the multilayer film (consisting of the gate oxide film 22, the polycrystalline silicon film 23, the thin oxide film 24, and the silicon nitride film 25) is left only in the active region 26, and the remaining parts are the silicon nitride film 25, Thin oxide film 24, polycrystalline silicon film 23, and gate oxide film 22 are removed in this order. In addition, before or after removing the gate oxide film 22, impurities of the same type as the silicon substrate 21, such as boron, are implanted by ion implantation for device isolation into the silicon substrate 21 other than the active region 26. Diffusion area 27
form. (See FIG. 2b) Next, a thin oxide film 28 is formed on the side surface of the polycrystalline silicon film 23 by thermal oxidation, and a silicon nitride film 29 is further formed to a thickness of 1000 to 2000 Å on the entire surface.
In this case, the thin oxide film 28 is also formed on the surface of the silicon substrate 21 other than the active region 26. (Figure 2c
(See) Thereafter, the silicon nitride film 29 is removed by dry etching, such as sputter etching. In this case, by selecting conditions appropriately, the active area 2
The silicon nitride film 25 can be left on the top surface of the polycrystalline silicon film 23 of No. 6, and the silicon nitride film 29 can be left on the side surfaces. Next, the thin oxide film 28 on the surface of the silicon substrate 21 other than the active region 26 is removed.
(See FIG. 2d) Next, a thick oxide film 30 for isolation between elements is formed on the surface of the silicon substrate 21 around the active region 26 by thermal oxidation. At this time, since the side surfaces of the polycrystalline silicon film 23 in the active region 26 are also covered with the silicon nitride film 29, there is no lateral oxidation. Therefore, the width of the active region 26 does not decrease, and no protrusions of the oxide film caused by side oxidation of the polycrystalline silicon film 23 occur. (See FIG. 2e.) Next, in the active region 26, only the gate region 31 is left with the multilayer film, and the other active regions 26 are covered with silicon nitride films 25, 29, a thin oxide film 24, and a polycrystalline silicon film 23. , the gate oxide film 22 is removed. Further, an impurity such as phosphorus is diffused over the entire surface to form impurity diffusion regions 32 that will become source/drain regions in the silicon substrate 21. (1st
(See FIG. (see Figure g).

その後、シリコン窒化膜34をドライエツチン
グたとえばスパツタエツチングで除去する。この
場合、条件を適当に選ぶことにより、ゲート領域
31の多結晶シリコン膜23の上面にシリコン窒
化膜25を、また側面にシリコン窒化膜34を残
すことができる。次に、ゲート領域31以外の薄
い酸化膜33の除去を行う。(第2図h参照) 次いで、熱酸化により、ソース・ドレインとな
る不純物拡散領域32上に、中間絶縁膜となる酸
化膜35を2000〜5000Å厚に形成する。この時、
多結晶シリコン膜23は、側面がシリコン窒化膜
34で覆われているため、側面の酸化がおこらな
い。したがつて、ゲート長、ゲート幅の減少や、
酸化膜の突起がおきない。(第2図i参照) その後、ゲート領域31のシリコン窒化膜2
5,34を除去する。また、薄い酸化膜24,3
3も除去する。そして、多結晶シリコン膜23、
酸化膜30,35上にメタル配線たとえばAl配
線36を形成することにより、メタル配線とゲー
トとのセルフアラインコンタクトがなされる。
(第2図j参照) なお、以上の実施例では、能動領域26および
ゲート領域31の多結晶シリコン膜23側面を酸
化膜28,33で覆い、さらにシリコン窒化膜2
9,34で覆うものであるが、酸化膜28,33
は省略することができる。
Thereafter, the silicon nitride film 34 is removed by dry etching, such as sputter etching. In this case, by appropriately selecting conditions, it is possible to leave the silicon nitride film 25 on the upper surface of the polycrystalline silicon film 23 in the gate region 31 and the silicon nitride film 34 on the side surfaces. Next, the thin oxide film 33 other than the gate region 31 is removed. (See FIG. 2h) Next, by thermal oxidation, an oxide film 35 that will become an intermediate insulating film is formed to a thickness of 2000 to 5000 Å on the impurity diffusion regions 32 that will become the source and drain. At this time,
Since the side surfaces of the polycrystalline silicon film 23 are covered with the silicon nitride film 34, oxidation of the side surfaces does not occur. Therefore, reduction of gate length and gate width,
No protrusions of oxide film are formed. (See FIG. 2i) After that, the silicon nitride film 2 of the gate region 31 is
Remove 5,34. In addition, thin oxide films 24, 3
3 is also removed. And polycrystalline silicon film 23,
By forming a metal wiring, such as an Al wiring 36, on the oxide films 30 and 35, a self-aligned contact between the metal wiring and the gate is made.
(See FIG. 2j.) In the above embodiment, the side surfaces of the polycrystalline silicon film 23 in the active region 26 and gate region 31 are covered with oxide films 28 and 33, and the silicon nitride film 23 is further covered with the silicon nitride film 23.
9 and 34, but the oxide films 28 and 33
can be omitted.

以上実施例で説明したように、この発明の製造
方法では、酸化を行う際に、露出している多結晶
シリコン膜側面をシリコン窒化膜で覆うものであ
る。したがつて、酸化時に多結晶シリコン膜の側
面が酸化されることが防止され、その結果能動領
域幅さらにはゲート長、ゲート幅を精度よく制御
することができる。また、多結晶シリコン膜の側
面酸化による酸化膜の突起の発生を防止し得るの
で、表面を滑らかにすることができる。
As described above in the embodiments, in the manufacturing method of the present invention, the exposed side surfaces of the polycrystalline silicon film are covered with a silicon nitride film during oxidation. Therefore, the side surfaces of the polycrystalline silicon film are prevented from being oxidized during oxidation, and as a result, the active region width, as well as the gate length and gate width, can be precisely controlled. Furthermore, since the formation of protrusions in the oxide film due to lateral oxidation of the polycrystalline silicon film can be prevented, the surface can be made smooth.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aないしfは従来のMOS型半導体装置
の製造方法を示す断面図、第2図aないしjはこ
の発明によるMOS型半導体装置の製造方法の実
施例を示す断面図である。 21……シリコン基板、22……ゲート酸化
膜、23……多結晶シリコン膜、24……酸化
膜、25……シリコン窒化膜、26……能動領
域、28……酸化膜、29……シリコン窒化膜、
30……酸化膜、31……ゲート領域、33……
酸化膜、34……シリコン窒化膜、35……酸化
膜。
1A to 1F are sectional views showing a conventional method for manufacturing a MOS type semiconductor device, and FIGS. 2A to 2J are sectional views showing an embodiment of the method for manufacturing a MOS type semiconductor device according to the present invention. 21... Silicon substrate, 22... Gate oxide film, 23... Polycrystalline silicon film, 24... Oxide film, 25... Silicon nitride film, 26... Active region, 28... Oxide film, 29... Silicon nitride film,
30... Oxide film, 31... Gate region, 33...
Oxide film, 34... silicon nitride film, 35... oxide film.

Claims (1)

【特許請求の範囲】 1 ゲート酸化膜、その上に形成された不純物を
含んだ多結晶シリコン膜、その上に形成された薄
い酸化膜、その上に形成されたシリコン窒化膜か
らなる多層膜を半導体基板表面の選択された領域
に形成する工程と、上記多層膜の側面に薄い酸化
膜を形成する工程と、上記多層膜の全表面にシリ
コン窒化膜を形成する工程と、上記多層膜周囲の
上記半導体基板表面に酸化膜を形成する工程とを
具備してなるMOS型半導体装置の製造方法。 2 ゲート酸化膜、その上に形成された不純物を
含んだ多結晶シリコン膜、その上に形成された薄
い酸化膜、その上に形成されたシリコン窒化膜か
らなる多層膜を半導体基板表面の選択された領域
に形成する工程と、上記多層膜の全表面にシリコ
ン窒化膜を形成する工程と、上記多層膜周囲の上
記半導体基板表面に酸化膜を形成する工程とを具
備してなるMOS型半導体装置の製造方法。
[Claims] 1. A multilayer film consisting of a gate oxide film, a polycrystalline silicon film containing impurities formed on it, a thin oxide film formed on it, and a silicon nitride film formed on it. a step of forming a thin oxide film on the side surface of the multilayer film; a step of forming a silicon nitride film on the entire surface of the multilayer film; and a step of forming a silicon nitride film on the entire surface of the multilayer film. A method of manufacturing a MOS type semiconductor device, comprising the step of forming an oxide film on the surface of the semiconductor substrate. 2. A multilayer film consisting of a gate oxide film, a polycrystalline silicon film containing impurities formed on it, a thin oxide film formed on it, and a silicon nitride film formed on it is deposited on a selected surface of the semiconductor substrate. a step of forming a silicon nitride film on the entire surface of the multilayer film; and a step of forming an oxide film on the surface of the semiconductor substrate around the multilayer film. manufacturing method.
JP584580A 1980-01-23 1980-01-23 Manufacture of mos semiconductor device Granted JPS56104468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP584580A JPS56104468A (en) 1980-01-23 1980-01-23 Manufacture of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP584580A JPS56104468A (en) 1980-01-23 1980-01-23 Manufacture of mos semiconductor device

Publications (2)

Publication Number Publication Date
JPS56104468A JPS56104468A (en) 1981-08-20
JPS6159675B2 true JPS6159675B2 (en) 1986-12-17

Family

ID=11622344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP584580A Granted JPS56104468A (en) 1980-01-23 1980-01-23 Manufacture of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS56104468A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632778U (en) * 1986-06-18 1988-01-09

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840839A (en) * 1981-09-04 1983-03-09 Toshiba Corp Manufacture of semiconductor device
JPS6473772A (en) * 1987-09-16 1989-03-20 Nec Corp Manufacture of semiconductor storage device
JPH088312B2 (en) * 1989-03-02 1996-01-29 三菱電機株式会社 Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632778U (en) * 1986-06-18 1988-01-09

Also Published As

Publication number Publication date
JPS56104468A (en) 1981-08-20

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