JPS6159863B2 - - Google Patents
Info
- Publication number
- JPS6159863B2 JPS6159863B2 JP53045671A JP4567178A JPS6159863B2 JP S6159863 B2 JPS6159863 B2 JP S6159863B2 JP 53045671 A JP53045671 A JP 53045671A JP 4567178 A JP4567178 A JP 4567178A JP S6159863 B2 JPS6159863 B2 JP S6159863B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- digital signal
- circuit
- processor
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Machine Tool Copy Controls (AREA)
- Numerical Control (AREA)
- Control Of Position Or Direction (AREA)
Description
【発明の詳細な説明】
本発明は、経済的な構成によつて倣い制御を行
なわせる倣い制御方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tracing control system that performs tracing control with an economical configuration.
倣い制御は、モデルの形状を検出しながら加工
するもので、モデルの形状が一般には大きな形状
変化部分を持たないので、倣い演算を行なうプロ
セツサは、それほど高速の演算機能を持たないも
のでも充分であつた。しかし、モデルによつては
コーナ部のようにモデル形状の急変部分を有する
ので、この急変部分に対応する倣い演算は高速で
行なわなければならないことになり、結局高速演
算機能を有するプロセツサを用いて、モデル形状
の急変部分に対処しなければならなかつた。従つ
て高価なプロセツサを設けることになり、装置全
体が高価なものとなる欠点があつた。 Tracing control involves processing while detecting the shape of the model, and since the shape of the model generally does not have large changes in shape, it is sufficient to use a processor that performs the tracing calculations even if it does not have very high-speed calculation functions. It was hot. However, some models have sudden changes in the model shape, such as corners, so the tracing calculations corresponding to these sudden changes must be performed at high speed. , I had to deal with sudden changes in the model shape. Therefore, an expensive processor is required, resulting in the disadvantage that the entire device becomes expensive.
本発明は、前述の如き従来の欠点を改善したも
ので、通常の形状変化の急変部分を有しないモデ
ルに対する倣い演算速度のプロセツサでもつて、
モデル形状の急変部分に対しても倣い演算を実行
し得るようにして、経済化を図ることを目的とす
るものである。以下実施例について詳細に説明す
る。 The present invention improves the above-mentioned conventional drawbacks, and provides a processor with high scanning speed for models that do not have sudden changes in shape.
The purpose of this is to make it possible to perform copying calculations even on parts where the model shape changes suddenly, thereby achieving economy. Examples will be described in detail below.
本発明は、モデル形状の急変部分を検出し、そ
の急変部分の倣い送り速度を通常の倣い送り速度
よりも遅くなるようにして、低速の演算速度のプ
ロセツサでも倣い演算を実行し得るようにしたも
のであり、第1図は本発明の実施例のブロツク線
図である。同図に於いて、THはトレーサヘツ
ド、ADX,ADY,ADZはAD変換器、ARCは倣
い演算回路、DCは分配回路、ADDは加算器、
DAX,DAYはDA変換器、DVX,DVYは駆動回
路、MX,MYはモータ、MTは機械可動部、SEL
1,SEL2はセレクタ、READは読込回路、
ARTは演算回路、ACCは累算回路、COMPは比
較回路、REG,REG1,REG2はレジスタ、
MULは乗算器、Fは送りパルス回路であり、倣
い演算回路ARC、分配回路DC等がプロセツサに
相当するものである。 The present invention detects a sudden change in the model shape, and sets the copying feed rate for the sudden change to be slower than the normal copying feed speed, so that even a processor with a low calculation speed can execute the copy calculation. FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, TH is a tracer head, ADX, ADY, and ADZ are AD converters, ARC is a copy calculation circuit, DC is a distribution circuit, ADD is an adder,
DAX, DAY are DA converters, DVX, DVY are drive circuits, MX, MY are motors, MT is mechanical moving parts, SEL
1, SEL2 is the selector, READ is the reading circuit,
ART is an arithmetic circuit, ACC is an accumulation circuit, COMP is a comparison circuit, REG, REG1, REG2 are registers,
MUL is a multiplier, F is a feed pulse circuit, and the copying calculation circuit ARC, distribution circuit DC, etc. correspond to the processor.
トレーサヘツドTHによりモデルの形状を検出
し、各軸方向の変位信号εx,εy,εzはAD変換
器ADX,ADY,ADZによりデイジタル信号に変
換され、倣い演算回路ARCはその演算速度に対
応した周期でデイジタル信号を読込む。この倣い
演算回路ARCに倣いて、変位方向信号sinθ,
cosθ、変位量信号ε=√x 2+y 2+z 2、
基準変位量ε0との差信号Δε=ε−ε0、及び
その差信号の絶対値信号|Δε|=|ε−ε0|
を求め、法線方向速度信号VN=KN(ε−ε0)
及び接線方向速度信号VT=−KT・|ε−ε0|
を演算して分配回路DCに加える。このような演
算は周知のデイジタル演算手段によつて行なうこ
とができる。 The shape of the model is detected by the tracer head TH, and the displacement signals ε x , ε y , ε z in each axial direction are converted into digital signals by the AD converters ADX, ADY, ADZ, and the tracing calculation circuit ARC adjusts the calculation speed. Read the digital signal at the corresponding period. Following this tracing calculation circuit ARC, the displacement direction signal sinθ,
cosθ, displacement signal ε=√ x 2 + y 2 + z 2 ,
Difference signal Δε=ε−ε 0 with reference displacement amount ε 0 and absolute value signal of the difference signal |Δε|=|ε−ε 0 |
Find the normal direction velocity signal V N =K N (ε−ε 0 )
and tangential velocity signal V T =−K T · |ε−ε 0 |
is calculated and added to the distribution circuit DC. Such calculations can be performed by well-known digital calculation means.
分配回路DCは法線方向速度信号VN接線方向速
度信号VTとを変位方向信号sinθ,cosθとによ
りX軸速度信号VXとY軸速度信号VYとに分配
し、DA変換器DAX,PAYによりアナログ信号に
変換してモータMX,MYを駆動回路DVX,DVY
により駆動する。 The distribution circuit DC distributes the normal velocity signal V N and the tangential velocity signal V T into an X-axis velocity signal V X and a Y-axis velocity signal V Y using the displacement direction signals sin θ and cos θ, Drive circuits DVX and DVY convert motors MX and MY to analog signals using PAY.
Driven by
演算回路ARTは、セレクタSEL1により選択
されたAD変換器ADX,ADY,ADZの出力デイジ
タル信号を読込むものであるが、AD変換器
ADX,ADY,ADZの出力デイジタル信号を倣い
演算回路ARCが読取つて速度信号VX,VYが出
力される1サイクル期間より短い周期でn回読込
むものであり、例えば第2図に示すX軸変位信号
εxに対して、演算回路ARTは、
Δεxi=εxi-1−εxi ……(1)
の演算を行なう。このような演算はレジスタ
REG1,REG2にεxi,εxi-1をセツトし、n回
の累算を累算器ACCを用いて行なうことができ
る。 The arithmetic circuit ART reads the output digital signals of the AD converters ADX, ADY, ADZ selected by the selector SEL1.
The output digital signals of ADX, ADY, and ADZ are read by the arithmetic circuit ARC and read n times at a cycle shorter than the one cycle period in which the speed signals V X and V Y are output. For the displacement signal ε x , the calculation circuit ART calculates Δε xi = ε xi-1 −ε xi ……(1) Perform the calculation. Such operations are performed using registers.
By setting ε xi and ε xi-1 in REG1 and REG2, n-time accumulation can be performed using the accumulator ACC.
又レジスタREGには任意数の設定値がセツト
されており、比較回路COMPに於いてこの設定値
と累算器ACCの内容とを比較し、その比較結果
に基いてセレクタSEL2を制御する。セレクタ
SEL2にはオーバライド値A、B、Cが加えられ
ており、比較回路COMPの出力によつて選択され
たオーバライド値が乗算器MULに加えられる。
例えば、A>B>C>Dとして
A≦Δεx<BのときA%(例えば90%)
B≦Δεx<CのときB%(例えば70%)
C≦Δεx<DのときC%(例えば50%)
の如くそれぞれの条件に対応した%のオーバライ
ドをかけるものである。 Further, an arbitrary number of setting values are set in the register REG, and the comparison circuit COMP compares this setting value with the contents of the accumulator ACC, and controls the selector SEL2 based on the comparison result. selector
Override values A, B, and C are added to SEL2, and the override value selected by the output of the comparison circuit COMP is added to the multiplier MUL.
For example, as A>B>C>D, A% when A≦Δε x <B (for example, 90%) B% when B≦Δε x <C (for example, 70%) C% when C≦Δε x <D (for example, 50%), a percentage override is applied that corresponds to each condition.
乗算器MULは送りパルス回路Fからの一定の
値の信号に対してオーバライド値を乗算し、その
結果を加算器ADDにより接線方向速度信号VTに
加算する。この場合の接線方向速度信号VTは前
述の如くVT=−KT・|ε−ε0|で表わされる
ので、乗算器MULの出力が加算されることによ
り分配回路DCに加えられる速度信号は小さい値
となる。即ちモータMX,MYによる倣い送り速
度が減速されることになる。 The multiplier MUL multiplies the constant value signal from the feed pulse circuit F by an override value, and the adder ADD adds the result to the tangential velocity signal V T . In this case, the tangential speed signal V T is expressed as V T =-K T · |ε-ε 0 | as described above, so the speed signal is applied to the distribution circuit DC by adding the output of the multiplier MUL. is a small value. In other words, the scanning feed speed by motors MX and MY is reduced.
又累算器ACCのn回の累算値はモデルの形状
の変化が少なければ小さな値となり、前述の比較
回路COMPに於ける条件の何れも満足しないの
で、乗算器MULの出力は零となり、倣い演算回
路ARCの出力の接線方向速度信号VTがそのまま
分配回路DCに加えられるので、通常の倣い送り
速度となる。なお累算器ACCの内容はn回毎ク
リヤされる。又オーバライドの条件が所定回数続
いて発生しなかつたとき、前述のオーバライドを
解除することが好適であり、このような手段は比
較回路COMPによるオーバライド条件の判定結果
をカウントするカウンタを設けて容易に実現する
ことができる。 Also, the n-time accumulated value of the accumulator ACC will be a small value if there is little change in the shape of the model, and none of the conditions for the comparison circuit COMP mentioned above is satisfied, so the output of the multiplier MUL will be zero, Since the tangential velocity signal V T output from the copying calculation circuit ARC is directly applied to the distribution circuit DC, the normal copying feed speed is achieved. Note that the contents of the accumulator ACC are cleared every n times. Furthermore, it is preferable to cancel the above-mentioned override when the override condition does not occur a predetermined number of times in succession. It can be realized.
以上説明したように、本発明は、プロセツサが
入力デイジタル信号を読込んで演算結果を出力す
る1サイクルの間に、トレーサヘツドTHからの
アナログ変位信号を変換したデイジタル信号を、
前記1サイクルより短い周期で読取つて、デイジ
タル信号の増分を演算回路ART等により求め、
この増分が設定値より大きくなつたとき、即ちモ
デル形状の急変部分に相当するとき、倣い送り速
度にオーバライドをかけて減速するものであるか
ら、急変部分の倣い送り速度が遅くなり、プロセ
ツサは充分に倣い演算を実行して倣い制御を行な
わせることができ、通常の倣い送り速度に対応し
た演算速度のプロセツサでもつて形状急変部分に
対する倣い制御を高精度で実行することができ
る。従つて廉価なマイクロプロセツサを採用する
ことができるので、経済的な構成とすることがで
きる利点がある。 As explained above, the present invention converts the analog displacement signal from the tracer head TH into a digital signal during one cycle in which the processor reads the input digital signal and outputs the calculation result.
The digital signal is read at a cycle shorter than the one cycle, and the increment of the digital signal is determined by an arithmetic circuit such as ART,
When this increment becomes larger than the set value, that is, when it corresponds to a sudden change in the model shape, the profiling feed speed is overridden and decelerated, so the profiling feed speed for the sudden change becomes slower and the processor is not able to process enough data. It is possible to carry out scanning control by executing scanning calculations, and even with a processor whose calculation speed corresponds to the normal scanning feed rate, scanning control can be performed with high precision for a portion of sudden shape change. Therefore, since an inexpensive microprocessor can be used, there is an advantage that the configuration can be made economical.
第1図は本発明の実施例のブロツク線図、第2
図は変位信号の説明図である。
THはトレーサヘツド、ADX,ADY,ADZは
AD変換器、ARCは倣い演算回路、DCは分配回
路、DAX,DAY,DAZはDA変換器、DVX,
DVYは駆動回路、MX,MYはモータ、MTは機械
可動部、ARTは演算回路、REG,REG1,REG
2はレジスタ、ACCは累算器、COMPは比較回
路、MULは乗算器、ADDは加算器である。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of a displacement signal. TH is tracer head, ADX, ADY, ADZ are
AD converter, ARC is copy calculation circuit, DC is distribution circuit, DAX, DAY, DAZ is DA converter, DVX,
DVY is the drive circuit, MX, MY is the motor, MT is the mechanical moving part, ART is the calculation circuit, REG, REG1, REG
2 is a register, ACC is an accumulator, COMP is a comparison circuit, MUL is a multiplier, and ADD is an adder.
Claims (1)
イジタル信号に変換し、該デイジタル信号を演算
して各軸の速度信号を求めるプロセツサを有し、
該プロセツサの出力信号をアナログ信号に変換し
てモータを駆動して倣い送りを行なう倣い制御方
式に於いて、前記プロセツサが前記デイジタル信
号を読込んで演算を行ない、その結果を出力する
1サイクルの間に、前記デイジタル信号を前記1
サイクルより短い周期で読取つて該デイジタル信
号の増分を求め、該増分が設定値を越えたときに
倣い送り速度を減速させることを特徴とする倣い
制御方式。1. It has a processor that converts the analog displacement signal from the tracer head into a digital signal and calculates the speed signal of each axis by calculating the digital signal.
In a copying control method in which the output signal of the processor is converted into an analog signal to drive a motor to perform copying feed, during one cycle in which the processor reads the digital signal, performs calculations, and outputs the result. , the digital signal is
A scanning control method characterized by determining an increment in the digital signal by reading it at a shorter period than a cycle, and decelerating the scanning feed speed when the increment exceeds a set value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4567178A JPS54137783A (en) | 1978-04-18 | 1978-04-18 | Profiling control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4567178A JPS54137783A (en) | 1978-04-18 | 1978-04-18 | Profiling control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54137783A JPS54137783A (en) | 1979-10-25 |
| JPS6159863B2 true JPS6159863B2 (en) | 1986-12-18 |
Family
ID=12725839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4567178A Granted JPS54137783A (en) | 1978-04-18 | 1978-04-18 | Profiling control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54137783A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58217246A (en) * | 1982-06-11 | 1983-12-17 | Daihatsu Motor Co Ltd | Control method of tool slide in nc lathe |
| JPS59124552A (en) * | 1982-12-29 | 1984-07-18 | Fanuc Ltd | Copying control device |
| JPS6043707A (en) * | 1983-08-19 | 1985-03-08 | Hitachi Ltd | Industrial robot control device |
| JPS6224947A (en) * | 1985-07-22 | 1987-02-02 | Fanuc Ltd | Tracing control device |
| JPS62221704A (en) * | 1986-03-24 | 1987-09-29 | San Esu Shoko Co Ltd | Numerical control method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4881186A (en) * | 1971-12-31 | 1973-10-30 | ||
| JPS6026663B2 (en) * | 1975-11-04 | 1985-06-25 | 富士通フアナツク株式会社 | Corner cut-in reduction control method |
-
1978
- 1978-04-18 JP JP4567178A patent/JPS54137783A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54137783A (en) | 1979-10-25 |
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