JPS6160367B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital thermometer using a thermistor as a temperature sensor.

In general, temperature measurement such as body temperature requires high accuracy (0.1℃) and fast temperature measurement speed, so digital thermometers, such as the one shown in Figure 1, that use a thermistor as a temperature sensor are commercially available. I started to do that.

In FIG. 1, Rth is a thermistor as a temperature sensor, and constitutes a bridge circuit 1 together with resistors R1, R2, and R3. The voltage between a and b of this bridge circuit, that is, the unbalanced voltage, is amplified by the preamplifier 2, and a voltage Eo proportional to the temperature is generated.
get. This analog voltage Eo is converted into a digital value by a double integration type analog-to-digital converter (hereinafter referred to as an A/D converter), and the temperature is displayed on the digital display 6. For example, adjust the bridge circuit 1 in advance so that the bridge output voltage is 0V at 0°C, and adjust the preamplifier gain so that the preamplifier output terminal voltage Eo is 200mV at 20°C. decide. Then, if this Eo is displayed as "20.0" with an A/D converter, the temperature can be displayed.

The double integration type A/D converter uses operational amplifier 4.
It is composed of an integrating circuit 3 and a control circuit 5. The input terminal of the operational amplifier 4 can be connected to the output voltage Eo of the preamplifier by means of a switch S', and by means of another switch S'' the reference voltage E _R
It is now possible to connect to. This switch
The on/off of S' and S'' is controlled by the control circuit 5 as follows. That is, during the input integration period, the switch S' is on (S'' is off), and the resistor Ri and capacitor C control the input voltage. Integrate the voltage Eo over a certain period of time. Next, switch S'' is turned on (S' is turned off) during the reference integration period, and the voltage E _R , which has the opposite polarity to the input voltage Eo, is integrated until the integral output voltage becomes zero. In this case, the integral output Since the slope of is constant, the reference integration time is proportional to the input voltage.The number of clock pulses within this time is counted by a counter in the control circuit 5 and latched to obtain a digital output.This double integration method has the advantage that fluctuations in the clock period and circuit elements Ri, Re, and C do not cause errors.

However, in a digital thermometer as shown in FIG. 1, in order to improve its measurement accuracy, it is important that the output voltage Eo of the preamplifier A1 be proportional to the measured temperature. However, since the resistance of a thermistor changes logarithmically with temperature, in order to make the output voltage Eo of preamplifier A1 proportional to temperature as described above, for example, a correction resistor must be inserted in parallel with the thermistor Rth. Improve the linearity of the bridge circuit with respect to temperature, or further improve the preamplifier A1.
It was necessary to take measures such as keeping the degree of amplification stable against temperature changes.

In addition, a general thermometer must be able to measure and display plus or minus temperatures at 0°C.

It is an object of the present invention to provide a digital thermometer that has a relatively simple structure, has high measurement accuracy, and is capable of measuring both plus and minus temperatures.

The present invention will be explained below with reference to the illustrated embodiments.

FIG. 2 is a block diagram showing the temperature measurement principle of the present invention. Thermistor Rth is a normal thermistor with negative characteristics, one end of which is connected to a constant DC voltage Ei
(negative voltage in this example), and the other end is connected to the input terminal of the operational amplifier 10 via the switch S1. Therefore, the thermistor Rth functions as one element constituting the first integrating circuit together with the capacitor C connected between the input and output terminals of the operational amplifier 10. Between the input and output terminals of the operational amplifier 10,
A series circuit of switch S2 and resistor Ro is connected in parallel, and a discharge path (second
It is now possible to configure an integral circuit (integrator circuit).

First, as shown in FIG.
Close and perform the first integral. When a negative voltage is applied to Ei, the output voltage E1 of the operational amplifier 10 has a positive voltage waveform along the function of Ei/Rth·Ct as shown in FIG. When the counter of the control circuit 50 counts the number of pulses N, the output signal from the counter opens the switch S1 and closes the switch S2. That is, the first
The amount of electricity charged in the capacitor C during integration is discharged through a predetermined resistor Ro. Capacitor C
Since the voltage changes exponentially with time t, this voltage is compared with a predetermined reference voltage E _R by a comparator in the control circuit 50 to find a matching point. The temperature is displayed on the digital display 60 when the ratio of the time from the start of integration until the second index changes (number of pulses N) to the time until the voltage comparison matches (number of pulses Nx) is expressed as a number of pulses. can be done.

However, unlike thermometers, thermometers must be able to measure negative temperatures as well. For this reason, in the present invention, a 0°C reference counter is especially provided. That is, the 0°C reference counter is started at the same time as the second integration starts, and a predetermined count value of this counter, for example, the 1000th count, is associated with 0°C, and when this count value is reached, the 0°C reference counter ends. Generate a pulse. Then, at the time when this end pulse is generated, it is determined whether the second integration has ended or is continuing, and the minus or plus of the temperature is determined.

In principle, the absolute value of the temperature can be determined by anti-coinciding the 0° C. counter output and the second integral output using a suitable logic circuit and counting the clock pulses during the duration of the gate output pulse. Figure 4a
is the case of negative temperature, and the pulse of the second integral is 0.
Since the time width is shorter than the 0° C. counter pulse, the anti-coincidence gate output occurs already before the end of the 0° C. counter pulse. In addition, in the case of positive temperature, the fourth
As shown in Figure b, the gate output occurs after the end of the 0°C pulse because the second integral pulse has a longer time width than the 0°C counter pulse. Next, regarding the sign of the temperature, check the presence or absence of the output pulse of the second integral at the falling edge of the pulse of the 0°C counter.
The polarity may be displayed depending on its presence or absence. For example, as shown in Figure 5, when a D-type flip-flop is used and an H level signal (second integral pulse) comes to the D input terminal, the rising edge (trailing edge) of the 0°C counter pulse For example, output terminal Q is set to H level, and a lamp is lit by this Q output.

Next, the circuit example shown in FIG. 6 will be specifically explained.

S1 and S2 are the switches explained in Fig. 2, and S3
are switches for shorting the capacitor C of the integrating circuit, and these switches are analog switches using semiconductors.

20 is the terminal voltage E1 of the capacitor C when the accumulated charge of the capacitor C flows out through the resistor Ro.
This is a comparator that checks whether E1 has fallen to a predetermined value E _R and produces an output when E1 reaches E _R . 21 is a waveform shaping circuit that converts the comparison match output of the comparator 20 into a pulse with a relatively short pulse width, and 22 is a flip-flop that is reset by the waveform-shaped comparison match output pulse. This flip-flop 22
While in the reset state, the output of the flip-flop turns on switch S3 and shorts capacitor C. As a result, comparator 20 does not operate. 25 is a set Q output of the flip-flop 22 and a gate 32 which will be described later.
This AND gate 25 has two inputs: the inverted signal of the output of the flip-flop 22 (the output of the inverter 24), and the set output Q of the flip-flop 22.
The on/off operation of the switch S2 by the gate 32 is prohibited while the output of the gate 32 is generated.
It works to make it valid when the output disappears.

30 is a clock generator with a clock frequency o;
A counter 31 counts clock pulses from the generator 30. The counter 31 is constructed by adding two stages of 1/2 counting circuits 31A and 31B to a three-stage 1/10 counting circuit. Therefore, the previous stage 1/2 counting circuit 31A is turned on when 1000 clock pulses are counted. However, 31B turns on when the count reaches 2000. 33 is a flip-flop which is inverted and set by the output of the 1/2 counting circuit 31B at the 2000th count. The aforementioned gate 32 connects the Q output of this flip-flop 33 and the 1/2 counting circuit 3.
This is an AND gate that takes the outputs of 1A and 31B as 3 inputs. Therefore, this AND gate has the following values:
Output occurs until less than 4000 counts. This gate output is sent to switch S1, closing it. The output of this gate 32 thus defines the first integration interval.

34 is a flip-flop which performs inversion operation at the rising edge of the output of the flip-flop 33; 35 is a 0° C. counter which is reset at the rising edge of the output of the flip-flop 34; 0℃ counter 35
starts counting the clock pulses of the clock generator 30 from the time when the flip-flop 34 is set at the end of the first integration and the output of the flip-flop disappears, and at the 1000th count, its Q output becomes L level. This falling portion to the L level is extracted as a thin pulse (0° C. pulse) P1 through a single pulse forming circuit 36 which is a combination of an RC integration circuit, an inverter and an AND gate, and resets the flip-flop 34. In other words, the flip-flop 34 is exactly 1000 after the first integration.
The count interval is set and then reset. In this example, the reset point is 0°C.
It corresponds to When the flip-flop 34 is reset, the 0°C counter 35 is also reset by its output. 37 is a circuit that generates the pulse (second integration end pulse) P2 of the falling part of the Q output of the flip-flop 22, one input terminal is directly connected to the output terminal of the flip-flop 22, and the other input terminal is used for CR integration. It is connected to the Q output terminal of the flip-flop 22 through the circuit.
It consists of AND gate 38. flipflop 2
2 is set at the rising edge of the gate 32 and the comparator 20
Since it is reset by the comparison match output from
A single pulse occurs at the AND gate 38 at the end of the second integration.

39 is a D flip-flop for determining the polarity of the measured temperature; its D input terminal is connected to the Q output terminal of flip-flop 22; its clock input terminal is connected to the output terminal of flip-flop 34; and its Q output terminal is connected to the output terminal of flip-flop 34. 60 is connected to the polarity indicating segment of the device 60.

41 is a reset gate circuit that generates a reset pulse for the counter 31, and 42 is a reset gate circuit for the counter 31.
This is a latch gate circuit that generates a latch pulse that causes the latch circuit 40 to read and hold the contents of the latch circuit.
The reset gate circuit 41 is connected to the flip-flop 3
An AND gate 43 which has two inputs, the Q output of 4 and the second integration end pulse P2, and a flip-flop 2.
2 Q output and 0°C pulse P1 as 2 inputs.
AND gate 44 and both AND gates 43
and an OR gate 45 which leads the output of 44 to the reset input terminal of the counter 31. On the other hand, the latch gate circuit 42 has an AND gate 46 which has two inputs, which are the output of the flip-flop 34 and the second integration end pulse P2, and which has two inputs, the output of the flip-flop 22 and the 0°C pulse P1.
AND gate 47 and OR gate 4 which leads the outputs of both gates to the operating input terminal of latch circuit 40.
It consists of 8.

Next, the operation of the above circuit will be explained with reference to the time chart shown in FIG.

At the same time as the power switch is turned on, the counter 31 starts counting by a pulse from the clock generator 30. 1/2 counting circuit 31A at 1000th count
turns on, and at the 2000th count, 1/2 counting circuit 3
1B is turned on (a in Figure 7). The fall of the pulse of this 1/2 counting circuit 31B inverts the flip-flop 33 and puts it in the set state, causing the Q output to become
is applied to AND gate 32 (FIG. 7b). Then, when we reached the second 3000 count,
All three inputs of the AND gate 32 become H level, and the output of the gate rises (c in FIG. 7). The flip-flop 22 is set by the rising edge of the output of the gate 32, its output disappears and the switch S3 is turned off, and the output of the gate 32 closes the switch S1.

From the moment switch S1 is turned on, the DC voltage
Ei causes capacitor C to pass through thermistor Rth.
The terminal voltage of the capacitor increases in the form of Ev/Rth Ct.

Next, when the 4000th count (point d in Figure 7) is reached, the outputs of the 1/2 counting circuits 31A and 31B are turned off, the flip-flop 33 is reset, and the output of the AND gate 32 disappears.
Switch S1 turns off. When the output of the AND gate 32 disappears, the output of the inverter 24 becomes H level, so that an output is generated to the AND gate 25.
This is because flip-flop 22 is still in the set state at this point. gate 2
The output of 5 causes switch S2 to close in place of S1. Therefore, at the 4000th count (N=1000), the first integration automatically ends, and then the second integration starts, in which the charge accumulated in the capacitor C up to that point is discharged through the resistor Ro.

Now, if the clock frequency of the clock generator 30 is o and the number of pulses defining the interval of the first integration is N, then the capacitor C at the end of the first integration is
The terminal voltage E _N has the following value.

E _N =Ei/Rth・C・N/o (1) As time t elapses, this voltage becomes exponential function e
It decreases according to 1/Ro·Ct.

The discharge voltage E1 is the reference voltage E of the comparator 20.
When descending to _R (point e in Figure 7), the comparator 20
The output changes from on to off, and at this time a pulse is generated in the waveform shaping circuit 21. This circuit 21
The compare match pulse from the flip-flop 22 is sent to the reset input terminal of the flip-flop 22 to reset the flip-flop, and its output causes the switch S3 to be reset.
Turn on to short-circuit the integrating circuit. Further, when the Q output of the flip-flop 22 falls, a second integration end pulse P2 is taken out.

On the other hand, at the rising edge of the output of the flip-flop 33, that is, at point d in FIG.
4 is inverted and enters the set state. That is, at the same time as the first integration ends, the Q output of the flip-flop 34 becomes H level, and the output becomes L level. Due to the disappearance of the output of the flip-flop 34, the temperature rises to 0°C.
The reset state of the counter 35 is released and the counter 35 starts counting clock pulses. 1000
At the pulse number, the Q output of the 0° C. counter 35 falls to the L level, and therefore a thin 0° C. pulse P1 is generated (point f in FIG. 7).

Whichever of the 0° C. pulse P1 and the second integration end pulse P2 occurs first serves as a reset pulse for the counter 31, and the one that occurs later serves as a latch pulse for the latch circuit 40.

For example, if the second integration end pulse P2 occurs while the flip-flop 34 of the 0°C counter is still in the set state, that is, in the case of negative temperature (d, e, f in FIG. 7), the AND gate 43, OR
Counter 3 is activated by pulse P2 through gate 45.
1 is reset, then AND gate 47, OR
A 0°C pulse P1 through gate 48 activates latch circuit 40 to store and display the count value during that time on display 60.

However, conversely, if the second integration end pulse P2 has already reset the flip-flop 34 of the 0°C counter by the 0°C pulse P1, then
In other words, in the case of positive temperature (d', f', e' in Figure 7)
, the counter 31 is reset by the pulse P1 via the AND gate 44 and the OR gate 45,
Next, the count value until the latch circuit 40 is activated by the pulse P2 is displayed on the display 60 through the AND gate 46 and the OR gate 48.

The polarity of the temperature is displayed by flip-flop 3 while the Q output of flip-flop 22 is at H level.
If there is a rising edge of 4, that is, if the 0° C. counter counts up during the second integration period, the D flip-flop 39 determines that it is positive, and causes the display 60 to display.

Now, set this latch and the displayed count value to
If Nx is the time from the start of counting Nx to the end of the second integral, tx is as shown in Figure 3, then tx=RoC log E _N /E _R ...(2), and from this, equation (1) is obtained. Substituting tx=Ro C log(Ei N/Rth C fo E _R
)…(3) becomes. Therefore, since Nx=fo tx, Nx=foRoC log(Ei N/Rth C fo E _R
)…(4) becomes. Since fo, Ro, C, N, Ei, and E _R are constant, Nx is proportional to the logarithm of the change in 1/Rth, as seen from equation (4). In other words, since log1/Rth is proportional to temperature, the count value of Nx represents temperature.

In the above, the 0°C counter was explained using 1000 counts, but this can be arbitrarily selected. In order to obtain a thermometer that can measure down to -100.0°C with a resolution of 0.1°C, 1000 counts is preferable. However, in reality, a thermistor's measurement limit is -50°C, so a 500-count counter will suffice.

If we do not consider the usable range of the thermistor and assume that the 0°C counter has 1000 counts, it is possible to measure from -100°C to +599.9°C, and it is possible to measure from 0°C to +599.9°C.
Depending on how the counter is set, measurements can be made from -200°C. In other words, since the temperature can be measured up to an absolute width of 700°C, any temperature measurement range can be determined by changing the 0°C reference.

As described above, since the thermometer of the present invention measures the resistance value of the thermistor without correcting its logarithmic characteristic and directly measures the temperature, it has extremely high measurement accuracy. Neither a bridge circuit nor a preamplifier as shown in the conventional FIG. 1 is required. It is possible to measure temperatures both plus and minus 0°C, and it is possible to define any measurement range by adjusting the 0°C standard.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a conventional digital thermometer, Figure 2
The figure is a schematic diagram of the digital thermometer of the present invention, FIG. 3 is a diagram for explaining the principle of operation of the digital thermometer, and FIG.
5 and 5 are diagrams for explaining the principle of measuring plus and minus temperatures of the present invention, FIG. 6 is a block diagram of the digital thermometer of the present invention, and FIG. 7 is a time chart of each part thereof. 10... operational amplifier, 20... comparator, 21
...Waveform shaping circuit, 22, 33, 34...Flip-flop, 30...Clock generator, 31...Counter, 32...AND gate, 35...0°C counter,
39...D flip-flop, 40...latch circuit,
41...Reset gate circuit, 42...Latch gate circuit, 60...Display device.

Claims (1)

[Claims] 1. A main counter for counting clock pulses; a first switch that is turned on while the value of the main counter is within a predetermined first numerical range; connected in series with an integrating capacitor by the switch; A thermistor that integrates a constant DC voltage;
a second switch that is turned on immediately when a predetermined first numerical range of the main counter has elapsed;
A resistor of a predetermined value is connected to the capacitor by a switch and discharges the charge accumulated in the capacitor during the integration process; during this discharge, the voltage of the capacitor is compared with a predetermined reference voltage, and when they match, a comparison match output is provided. a comparator that generates a 0°C pulse; a 0°C counter that counts clock pulses from the time when a predetermined first numerical width of the main counter has elapsed and outputs a 0°C pulse when a predetermined count value is reached; circuit means for taking out a signal that occurs early among the °C pulse and the comparison match output as a reset signal for the main counter, and taking out a signal that occurs late as a latch signal for a latch circuit that latches the contents of the main counter; 1. A digital thermometer comprising: a display device that displays a count value latched to a circuit.