JPS6160466B2 - - Google Patents
Info
- Publication number
- JPS6160466B2 JPS6160466B2 JP57178028A JP17802882A JPS6160466B2 JP S6160466 B2 JPS6160466 B2 JP S6160466B2 JP 57178028 A JP57178028 A JP 57178028A JP 17802882 A JP17802882 A JP 17802882A JP S6160466 B2 JPS6160466 B2 JP S6160466B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- digital input
- input circuit
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Input From Keyboards Or The Like (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
この発明は、マイクロコンピユータシステムま
たは制御用コンピユータシステムに使用されるデ
ジタル入力回路の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in digital input circuits used in microcomputer systems or control computer systems.
第１図は本発明のデジタル入力回路が適用され
るコンピユータシステムの全体構成を示すもの
で、１は中央処理装置CPO、２はメモリ、３は
デジタル出力回路、４はデジタル入力回路、５は
CPUと各装置部とを接続するバス、６はCPU、
メモリ、デジタル出力回路、およびデジタル入力
回路へ供給される５〔Ｖ〕の直流電源装置、７は
５〔Ｖ〕の電源ライン、８は5V直流電源へ供給
されるAC100〔Ｖ〕ラインであり、本発明ではデ
ジタル入力回路４の接点間に印加する電源として
も使用されているものである。 FIG. 1 shows the overall configuration of a computer system to which the digital input circuit of the present invention is applied, in which 1 is a central processing unit CPO, 2 is a memory, 3 is a digital output circuit, 4 is a digital input circuit, and 5 is a
A bus connecting the CPU and each device section, 6 is the CPU,
A 5 [V] DC power supply device that is supplied to the memory, digital output circuit, and digital input circuit, 7 is a 5 [V] power supply line, 8 is an AC 100 [V] line that is supplied to the 5V DC power supply, In the present invention, it is also used as a power source applied between the contacts of the digital input circuit 4.
しかし乍ら、従来のこの種のデジタル入力回路
として第２図に示すものがあつた。この第２図に
おいて、１１，１１Ａ…１１ｎはオン・オフ情報
を取り込もうとする無電圧接点、１２，１２Ａ…
１２ｎはフオトカツプラ、１３，１３Ａ…１３ｎ
はコンデンサ、１４は交流電源電圧を全波整流す
るためのダイオード、５は例えば第１図の交流電
源から導入してきた交流電源であり、Ｄ０〜Ｄ７
はデータ入力信号名または出力端子名を示す。 However, there is a conventional digital input circuit of this type as shown in FIG. In this FIG. 2, 11, 11A...11n are non-voltage contacts that try to capture on/off information, and 12, 12A...
12n is Foto Katsupura, 13, 13A...13n
is a capacitor, 14 is a diode for full-wave rectification of the AC power supply voltage, 5 is an AC power supply introduced from the AC power supply in Fig. 1, and D0 to D7.
indicates the data input signal name or output terminal name.
次に動作について説明する。入力接点１１，１
１Ａ…１１ｎがオン状態の場合、フオトカツプラ
に電流が流れて作動しロー信号がCPUに伝達さ
れ、また入力接点がオフ状態の場合フオトカツプ
ラもオフ状態になりハイ信号がCPUに伝達され
る。この場合コンデンサ１３，１３Ａ…１３ｎは
接点に印加される電圧が全波整流電圧であるため
に付加されている。 Next, the operation will be explained. Input contact 11,1
When 1A...11n is in the on state, current flows through the photo coupler and it is activated, and a low signal is transmitted to the CPU, and when the input contact is in the off state, the photo coupler is also in the off state and a high signal is transmitted to the CPU. In this case, the capacitors 13, 13A, . . . , 13n are added because the voltage applied to the contacts is a full-wave rectified voltage.
しかし乍ら、第２図に示す如きデジタル入力回
路では、交流電源１５に瞬時の停電が起つた場合
に不都合が生ずる。第３図は、この不具合の様子
を示す信号波形図である。すなわち5Vの直流電
圧は、直流電源の装置内のコンデンサによつて交
流電源１５が瞬時停電されても電圧保持時間が長
く保たれるが、交流電源１５の瞬時停電が生じた
場合は、入力接点１１，１１Ａ…１１ｎがオン状
態になつているにも拘わらずデータ入力が出力端
子Ｄ０〜Ｄ７においてハイ信号に形成され、
CPUがデータ入力を読み誤ることがある。この
ような場合に従来のデジタル入力回路では、以上
のように構成されているので、交流電源の瞬時停
電の時に入力データの誤認に対して正確に対処で
きない欠点がある。 However, in the digital input circuit as shown in FIG. 2, a problem occurs when an instantaneous power outage occurs in the AC power supply 15. FIG. 3 is a signal waveform diagram showing this problem. In other words, the 5V DC voltage can be maintained for a long time even if there is a momentary power outage in the AC power supply 15 due to the capacitor in the DC power supply device, but if a momentary power outage occurs in the AC power supply 15, the input contact 11, 11A...11n are in the on state, the data input is formed into a high signal at the output terminals D0 to D7,
The CPU may misread data input. In such a case, the conventional digital input circuit, which is configured as described above, has the disadvantage that it cannot accurately deal with misidentification of input data in the event of a momentary power outage of the AC power supply.
この発明は上記のような従来のものの欠点を除
去するためになされたもので、交流電源電圧をコ
ンパレータの入力としてその出力信号により入力
データをラツチするようにしたデジタル入力回路
を提供することを目的とする。 This invention was made in order to eliminate the drawbacks of the conventional circuits as described above, and an object thereof is to provide a digital input circuit in which an AC power supply voltage is input to a comparator, and input data is latched by the output signal of the comparator. shall be.
以下、この発明の一実施例を図について説明す
る。第４図において、１１，１１Ａ…１１ｎは無
電圧接点、１２，１２Ａ…１２ｎはフオトカツプ
ラ、１４はダイオードブリツジ、１５は交流電
源、１６，１６Ａ…１６ｎは入力データをラツチ
する。Ｄフリツプフロツプ、１７はコンパレー
タ、１８はトランス、１９はダイオードブリツジ
であり、Ｄ０〜Ｄ７は入力データ信号名または出
力端子名を、またＸはコンパレータ出力信号名で
ある。 An embodiment of the present invention will be described below with reference to the drawings. In FIG. 4, 11, 11A...11n are non-voltage contacts, 12, 12A...12n are photocouplers, 14 is a diode bridge, 15 is an AC power supply, and 16, 16A...16n are used to latch input data. D flip-flop, 17 is a comparator, 18 is a transformer, 19 is a diode bridge, D0 to D7 are input data signal names or output terminal names, and X is a comparator output signal name.
次に動作について説明する。第５図はコンパレ
ータ１７の出力信号Ｘと交流電源１５との関係を
示す信号波形図であり、上述したデジタル入力回
路４の動作を第５図とともに説明する。いま交流
電源１５に瞬時停電がなく正常な時には、その交
流電源１５からトランス１８を経てダイオードブ
リツジ１９より全波整流波形の電圧が出力され、
この整流波形のピーク値、すなわち交流電圧の絶
対値が一番高くなる付近で、タイミング・パルス
Ａがコンパレータ１７の出力信号Ｘとして送出さ
れる。このタイミングパルスＸによつてフリツプ
フロツプ１６がその時の入力データを一旦ラツチ
する。これを繰り返えすことによつて出力端子Ｄ
０〜Ｄ７にはそれぞれの入力データが正常に伝送
される。 Next, the operation will be explained. FIG. 5 is a signal waveform diagram showing the relationship between the output signal X of the comparator 17 and the AC power supply 15, and the operation of the digital input circuit 4 described above will be explained with reference to FIG. When the AC power supply 15 is normal and there is no instantaneous power outage, a full-wave rectified waveform voltage is output from the AC power supply 15 via the transformer 18 and from the diode bridge 19.
Timing pulse A is sent out as output signal X of comparator 17 near the peak value of this rectified waveform, that is, near where the absolute value of the AC voltage is the highest. This timing pulse X causes the flip-flop 16 to temporarily latch the input data at that time. By repeating this, the output terminal D
Each input data is normally transmitted to 0 to D7.
一方、交流電源１５が時点Ｂのとき瞬時停電が
起こつた場合には、その瞬時コンパレータ１７の
一側入力端は０〔Ｖ〕であり、また＋側入力端は
第１図の直流整流電源６の内部で電圧保持時間を
所定時間以上は保持されるように構成されている
ので、正電圧が瞬時停電の期間中は印加されてい
る。このためコンパレータ１７の出力Ｘはハイ信
号Ｃの状態になる。つまり、フリツプフロツプ１
６，１６Ａ…１６ｎへのタイミングパルスが送出
されなくなり、入力データＤ０〜Ｄ７は交流電源
が再び立ち上がるまで保持されることになる。そ
の結果、この瞬時停電の期間中に従来のデジタル
入力回路の構成上発生した様な誤信号の伝送が阻
止できることになる。 On the other hand, if a momentary power outage occurs when the AC power supply 15 is at time B, one side input terminal of the instantaneous comparator 17 is 0 [V], and the + side input terminal is the DC rectification power supply 6 in FIG. Since the voltage is maintained internally for a predetermined time or longer, positive voltage is applied during the momentary power outage. Therefore, the output X of the comparator 17 becomes the high signal C state. In other words, flip-flop 1
Timing pulses to 6, 16A, . As a result, transmission of erroneous signals, which occurs due to the configuration of conventional digital input circuits, can be prevented during this instantaneous power outage period.
以上のように、本発明によれば、交流電源電圧
をコンパータの入力とし、更にその出力信号によ
り入力データをラツチするように構成したので、
交流電源の瞬時停電時に生ずるデジタル入力デー
タの読み誤りを確実に防止できる優れた効果があ
る。 As described above, according to the present invention, since the AC power supply voltage is input to the converter and the input data is latched by the output signal,
This has an excellent effect of reliably preventing misreading of digital input data that occurs during a momentary power outage of the AC power supply.
第１図は本発明のデジタル入力回路が適用され
るシステム全体の構成図、第２図は従来のデジタ
ル入力回路の接続図、第３図はそのデジタル入力
回路の瞬時停電時の信号の様子を表わしたタイミ
ング図である。また、第４図は、本発明の一実施
例のデジタル入力回路の接続図、第５図は同実施
例のデジタル入力回路の瞬時停電時の信号の様子
を表わしたタイミング図である。
１…中央処理装置（CPU）、２…メモリ、３…
デジタル出力回路、４…デジタル入力回路、５…
バス、６…5V直流電源、７…5V電源ライン、８
…交流電源ライン、１１，１１Ａ…１１ｎ…無電
圧接点、１２，１２Ａ…１２ｎ…フオトカツプ
ラ、１３，１３Ａ…１３ｎ…コンデンサ、１４…
ダイオード、１５…交流電源、１６，１６Ａ…１
６ｎ…Ｄフリツプフロツプ、１７…コンパレー
タ、１８…トランス。なお、図中、同一符号は同
一または相当部分を示す。
Fig. 1 is a block diagram of the entire system to which the digital input circuit of the present invention is applied, Fig. 2 is a connection diagram of a conventional digital input circuit, and Fig. 3 shows the state of signals in the digital input circuit during a momentary power outage. FIG. Further, FIG. 4 is a connection diagram of a digital input circuit according to an embodiment of the present invention, and FIG. 5 is a timing chart showing the state of signals in the digital input circuit of the embodiment at the time of a momentary power outage. 1...Central processing unit (CPU), 2...Memory, 3...
Digital output circuit, 4...Digital input circuit, 5...
Bus, 6...5V DC power supply, 7...5V power line, 8
...AC power line, 11,11A...11n...Voltageless contact, 12,12A...12n...Photo coupler, 13,13A...13n...Capacitor, 14...
Diode, 15...AC power supply, 16, 16A...1
6n...D flip-flop, 17...comparator, 18...transformer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
を供給されるコンピユータ装置のデジタル入力回
路において、前記直流電圧によつて付勢されるコ
ンパレータの第１の入力に前記直流電圧を分圧さ
れた基準電圧を、また第２の入力に前記交流電源
に基づく電圧をそれぞれ接続し、前記コンパレー
タの出力信号によりデータ入力情報をラツチする
ように構成したことを特徴とするデジタル入力回
路。1. In a digital input circuit of a computer device that is supplied with DC voltage from an AC power supply via a DC rectification power supply, a reference voltage obtained by dividing the DC voltage is applied to a first input of a comparator energized by the DC voltage. A digital input circuit, characterized in that the digital input circuit is configured to connect a voltage based on the AC power source to a second input, and to latch data input information by an output signal of the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57178028A JPS5968031A (en) | 1982-10-09 | 1982-10-09 | Digital input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57178028A JPS5968031A (en) | 1982-10-09 | 1982-10-09 | Digital input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5968031A JPS5968031A (en) | 1984-04-17 |
| JPS6160466B2 true JPS6160466B2 (en) | 1986-12-20 |
Family
ID=16041319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57178028A Granted JPS5968031A (en) | 1982-10-09 | 1982-10-09 | Digital input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5968031A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486236A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Single chip microcomputer |
-
1982
- 1982-10-09 JP JP57178028A patent/JPS5968031A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5968031A (en) | 1984-04-17 |
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