JPS6161199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor circuit constructed of semiconductor elements.

The following explanation uses a typical MOS transistor (hereinafter referred to as MOST) among insulated gate field effect transistors, and uses an N-channel transistor.
The high level is a logic "1" level and the low level is a logic "0" level. However, circuit-wise, the P channel MOST is essentially the same.

The development of IC memory using large-scale integrated circuits (LSI) has made rapid progress and is about to enter an era from 16K to 64K. In dynamic memories, the mainstream is a multiple address system in which operations are performed using two external control signals: a row address strobe (hereinafter referred to as) and a column address strobe (hereinafter referred to as). In multi-address memory, the row address buffer,
The row decoder performs a refresh (rewrite) operation on a series of memory cells connected to the row line selected by the row decoder, and transfers (rewrites) data between the memory cells and circuits external to the chip using signals. It is designed to control write and read operations. Since the internal operations of the row address system and the column address system can be separated in this way, multiple sets of memory cells connected to the row line can be sent to By sequentially adding column address signals and signals, it has become possible to perform write and read operations on a plurality of memory cells within the activation period of one signal. Hereinafter, this operation will be referred to as page mode. First, the operation of a column decoder in a conventional circuit system will be explained using FIG. FIG. 2 shows the waveforms of each contact when selected, and FIG. 3 shows the waveforms when not selected. In Figure 1, MOST
Q1 is a precharge transistor,
MOST Q4, Q5, and Q6 are input transistors whose gate inputs are the true complementary outputs IN ₁ . . . IN _o of the address buffer. MOST Q3 is a column line driving transistor, and MOST Q2 is a transistor for impedance conversion. When the signals are in the reset state, internal signals φ ₂ and φ ₃ are both at the “1” level, and contacts 1 and 2 are precharged to “1”. Also, the column line drive signal Dout is “0” because _φ1 is “0” and MOST Q3 is conductive.
It is becoming a state. However, MOST Q ₁ , Q ₄ , Q ₅ ,
The input signal IN ₁ of the NOR circuit consisting of Q ₆ ,
IN ₂ , ..., IN _o must become "0" at the time of reset. The signal is activated and the precharge signal _φ3 becomes "0", after which the true complement signal of the address buffer is determined according to the column address signal. The potential of contacts 1 and 2 of the selection decoder is the input signal
Since IN ₁ , IN ₂ , ..., IN _o are all "0", they remain "1", and that of the unselected decoder is connected to ground through that transistor because at least one of the input signals is "1". It is discharged to a potential and becomes "0". _φ1 is activated to “1” after the potentials of contacts 1 and 2 are determined, and the MOST Q of the selection decoder
Only 3 becomes conductive (ON) and its output becomes "1". Since contact 2 of the non-selected decoder is set to “0”, it becomes non-conducting (OFF) and its output is “0”.
It remains as it is. This state continues until the signal is reset, and when the signal is reset, the input signals IN ₁ , IN ₂ , ..., IN _o become "0", φ ₁ becomes "0", and then φ ₃ becomes "1". Then, contacts 1 and 2 are precharged and one cycle is completed. In the page mode, the above operation is performed for multiple column address signals in an attempt to shorten the cycle time, but the reset operations, that is, the reset and precharge of the column address buffer and the reset and precharge of the column decoder, take time. A significant reduction in cycle time has not yet been achieved.
Furthermore, a large current is required to precharge the column decoder at the time of resetting, and the peak current becomes extremely large because the charging current of the data bus line, output circuit, and input circuit overlaps in time. This peak current becomes a problem especially when the number of column decoders increases as the capacity of the memory increases. The increase in peak current not only makes it difficult to design systems using IC memory, but also reduces reliability.

An object of the present invention is to provide a semiconductor circuit that suppresses peak current and improves reliability.

The semiconductor circuit according to the present invention includes a decoder circuit that precharges the precharge contact during the inactive period of the strobe signal and generates an output during the active period of the strobe signal, and the decoder circuit includes precharge means for precharging the precharge contact. an output transistor; connection means for connecting the gate of the output transistor and the precharge contact; logic means for receiving a plurality of input signals and selectively discharging the charge precharged to the precharge contact; and the strobe signal. means for determining the gate potential of the output transistor by the logic means through the connection means which is in a conductive state when the output transistor enters an active period; means for generating a corresponding decoder output; means for electrically disconnecting the gate of the output transistor from the precharge contact by rendering the connection means non-conducting during the active period of the strobe signal; and means for inactivating the logic means to initiate precharging of the precharge contact after the logic means is disconnected from the gate of the precharge contact.
According to the present invention, in order to start precharging of the precharge contact in parallel during the period when the output of the decoder is being generated, the decoder is brought into the output generation state immediately after the output period of the decoder ends, that is. , it is possible to significantly shorten the apparent precharge period from the outside and enable high-speed operation.

The semiconductor circuit according to the present invention can be used as a column decoder of a multi-address dynamic memory circuit having two external signals, a row address strobe and a column address strobe. The column address and
The reset and precharge operations of the buffer and column decoder can be performed in parallel within the signal activation period, making it possible to realize a high-speed memory circuit.

In accordance with the present invention, the input clocks include a row address strobe and a column address strobe, and after one row address strobe, data input/output is performed sequentially for a series of memory cells in an addressed row line. In a random access memory that has the function of sequentially applying multiple sets of column addresses and column address strobes and sequentially transferring data between a multi-bit column register and chip external circuits, it is possible to reset the column address buffer and column decoder, A memory circuit is obtained in which the precharge operation is performed during the activation period of the column address strobe clock, and data can be written and read during the activation period of the column address strobe clock.

According to the invention, a row and a row address buffer;
In a memory circuit having a row decoder, a signal for controlling memory cell refresh, and a signal for controlling a column and a column address buffer, a column decoder, a read/write control circuit, an input/output data generation circuit, an output buffer, and an output buffer control circuit. Column address buffer, column decoder reset precharge
During the active period of the strobe clock, after the column decoder output is determined, the column address buffer is reset and precharged, and the column decoder is
A semiconductor memory circuit is obtained in which the NOR circuit is separated from the column line drive circuit and the NOR circuit is precharged.

The basic circuit system of the invention will be explained below with reference to the drawings.

The basic circuit is shown in FIG. 4, and FIGS. 5 and 6 show the waveforms of the contacts of the selected decoder and non-selected decoder, respectively. Here, the selected decoder is in the selected state, that is, the level of the NOR input is all “0”,
A non-selected decoder means a non-selected state, that is, a decoder in which at least one NOR input level is "1". The potential of each contact and the level of each control signal in the reset state are the same as the conventional one shown in Fig. 1. Contact 1 is precharged to "1" by _φ3 , and contact 2 is similarly precharged to "1" by MOST _Q4 . , NOR input signal IN ₁ , IN ₂ , …, IN _o (IN ₃ …
Regarding IN _o (not shown), it is "0". Also, the column line drive signal Dout is “0” because _φ1 is “0” and MOST _Q5 is “ON”.
It is becoming a state. The signal is activated,
The precharge signal _φ3 of the NOR circuit becomes “0”, and then the column address and
The true complementary signal of the buffer is determined. Contacts 1 and 2 of the NOR circuit whose NOR circuit inputs are all "0" are kept at "1", and the column line drive signal is set to "1" by _φ1 . On the other hand, when at least one of the NOR circuit inputs becomes "1", contacts 1 and 2 of the decoder become "0" and even if _φ1 is activated thereafter, the output remains "0". It is necessary to maintain this potential until the column line drive signal is reset. However, the potential of contact 1 can be separated from the operation of MOST Q5 after turning off MOST Q4. MOST by setting _φ2 to “0”
Turn off Q4 and input the NOR circuit inputs IN ₁ , IN ₂ ,...,
After setting IN _o to the reset state (“0”), changing _φ3 to “1” is the operation of MOST Q5.
It does not affect the potential of the column line drive signal in any way. After entering the reset state and _φ1 becomes “0” level, φ
₂ is set to "1", contact 2 is precharged, and one cycle is completed.

The basic operation of the circuit system of the present invention has been described above, and it has the following characteristics.

(1) Since it is not necessary to charge the column decoder at the time of reset, the reset time and cycle time in page mode can be shortened.

Only contact 2 is charged at the time of reset (2), making it possible to reduce and disperse the peak current.

Next, an embodiment of the present invention will be described with reference to FIGS. 7 and 8.

Blocks B1 and B2 are part of a column decoder circuit, and their number is 2 ^N if there are N column address signals. Outputs 3 and 6 are connected to the gates of MOSTs Q14 and Q22, which control the connections between the respective digit lines 7 and 8 and the data bus line 10. Row line 9 is selected according to the row address signal during the page mode cycle, and digit lines 7,
8 has a level corresponding to the information of the memory cell. When resetting in the page mode, the true complement output of the address buffer is “0”, contacts 1, 2, 4, 5.
is precharged to “1” in MOST Q7 and Q15, column line control signals 3 and 6 are in “0” state because _φ3 is “0”, and MOST Q14 and Q22 are
It's off. When the signal is activated, the address buffer control signals φ ₁ and φ ₂ are activated in sequence, and the true complement signal corresponding to the column address signal is output.
Appears in A ₀ ′, ₀ ′, A ₁ ′, ₁ ′, …, A′ _N , ′ _N. At the same time, the precharge signal of the column decoder becomes "0", and the potentials of contacts 1, 2, 4, and 5 change in accordance with the address correction output. Now Block B
If we assume that the inputs ₀ ′, ₁ ′, …, ′ _N of the decoder 1 are all “0”, contacts 1 and 2 are “1”
Keep the level the same. On the other hand, the precharge levels of the other column decoders change to "0" because at least one column address complement output is "1". In one of the non-selected decoders B1, the precharge level at contacts 4 and 5 becomes "0".
Subsequently, _φ3 is activated, the column drive signal 3 of the selected decoder becomes "1", and the other column drive signals 6 become "0".
It remains as it is. After that, by turning off the transfer gate transistors Q12 and Q20, the NOR circuits Q7, Q8, Q9, and Q1 of the column decoder are
0, Q11; Q15, Q16, Q17, Q18,
Q19 and column drive transistors Q13 and Q21 can be completely separated. At the same time as setting _φ5 to “0”, reset the address buffer by setting _φ1 and _φ2 to “0” and setting _φ6 to “1”, then set _φ4 to “1” to deselect. Pre-charging of contact 4 of the decoder can be performed. Column drive signals 3 and 6 are
Since the gate potentials of MOST Q13 and Q21 do not change, the state after activation is maintained as is.
When the circuit enters the reset state, first, _φ3 becomes "0" and the contact 3 also changes to the "0" level.
Thereafter, the contacts 2 and 5 can be precharged by turning MOST Q12 and Q20 "ON" using _φ5 . The stray capacitance of contacts 2 and 5 is the same as that of contacts 1 and 4.
It is smaller than the previous model and its charging time is short. Therefore, the reset time can be shortened compared to the conventional circuit system in which the minimum value of the reset time in the page mode is limited by the precharge of the column decoder. At the same time, since the charging current of the decoder can be carried out within the activation period, it is also effective in smoothing the peak current of the power supply.

As described above, by employing the circuit system of the present invention, the reset time in page mode can be shortened by performing the precharge operation of the column address buffer and column decoder within the activation period.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional semiconductor circuit, Figure 2 is a circuit diagram showing a conventional semiconductor circuit.
3 and 3 are diagrams showing the operating waveforms of the circuit in FIG. 1, FIG. 4 is a circuit diagram showing the basic circuit system of the semiconductor circuit of the present invention, and FIGS. 5 and 6 are the circuits in FIG. 4. FIG. Further, FIG. 7 is a configuration diagram showing a semiconductor circuit according to an embodiment of the present invention, and FIG. 8 is a diagram showing its operating waveforms. Symbols in the figure, Q ₁ to Q ₂₂ : MOS transistor, φ
₁ ~ φ ₃ : Control signal, IN ₁ ~ IN _o : Address input,
Dout: Column line drive signal.

Claims (1)

[Claims] 1. A decoder circuit that precharges a precharge contact during an inactive period of the strobe signal and generates an output during an active period of the strobe signal, the decoder circuit comprising a precharge means for precharging the precharge contact, an output transistor, connection means for connecting the gate of the output transistor and the precharge contact; logic means for receiving a plurality of input signals and discharging the charge precharged to the precharge contact in accordance with the logic values of the plurality of input signals; means for determining the gate potential of the output transistor by means of the logic means via the connection means when the strobe signal enters the active period; means for generating a decoded output; means for electrically disconnecting the gate of the output transistor from the precharge contact by rendering the connection means non-conductive during the active period of the strobe signal; and means for inactivating the logic means and starting precharging of the precharge contact after the logic means is disconnected from the circuit.