JPS6161250B2 - - Google Patents
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- JPS6161250B2 JPS6161250B2 JP52137474A JP13747477A JPS6161250B2 JP S6161250 B2 JPS6161250 B2 JP S6161250B2 JP 52137474 A JP52137474 A JP 52137474A JP 13747477 A JP13747477 A JP 13747477A JP S6161250 B2 JPS6161250 B2 JP S6161250B2
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- semiconductor
- substrate
- single crystal
- plane orientation
- temperature
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- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は、半導体基板の所定領域を選択的に所
定面方位の単結晶に再結晶せしめる半導体の再結
晶法に係わる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor recrystallization method for selectively recrystallizing a predetermined region of a semiconductor substrate into a single crystal with a predetermined plane orientation.
従来、多くの半導体素子、例えばシリコン半導
体素子は{111}面方位をもつたシリコンウエー
ハが使用される。この理由は、{111}面が最も安
定した面であり、エピタキシヤル成長時に、他の
面方位をもつシリコンウエーハよりも結晶性が良
い等の理由によるものである。しかしMOS構造
(金属―酸化膜―半導体構造)の素子の場合は、
素子の機能が動作し始める最低の電圧であるしき
い電圧(Vth)に関係する表面準位が{111}面
より{100}面の方が少ないために{100}面ウエ
ーハが良く使われる。このように各素子にはそれ
ぞれの機能を発揮するのにふさわしい面方位が存
在する。しかし、いろいろな機能を有した素子を
内蔵した集積回路(IC)、あるいは大規模集積回
路(LSI)においては、一枚のウエーハ或は一つ
のチツプの中に各種の面方位をもつたウエーハを
作る事が出来ず、従つていずれかの素子の機能を
犠牲にせざる得ないのが現状である。 Conventionally, many semiconductor devices, such as silicon semiconductor devices, use silicon wafers with {111} plane orientation. The reason for this is that the {111} plane is the most stable plane and has better crystallinity during epitaxial growth than silicon wafers with other plane orientations. However, in the case of elements with MOS structure (metal-oxide film-semiconductor structure),
{100} plane wafers are often used because the {100} plane has fewer surface states related to the threshold voltage (Vth), which is the lowest voltage at which the device's function begins to operate, than the {111} plane. In this way, each element has a plane orientation suitable for performing its respective function. However, in integrated circuits (ICs) or large-scale integrated circuits (LSIs) that incorporate elements with various functions, wafers with various surface orientations are used in one wafer or one chip. Currently, the function of one of the elements must be sacrificed.
また、半導体素子を作る場合、多くは単結晶ウ
エーハが使用されるも、半導体素子がその機能を
発揮するのに必要な部分は、この単結晶ウエーハ
のほんの一部分である。しかし、この一部分のた
めに莫大なエネルギーを費して、ウエーハ全体を
単結晶にせざるを得ないのが現状である。 Further, when manufacturing semiconductor devices, a single crystal wafer is often used, but only a small portion of the single crystal wafer is necessary for the semiconductor device to perform its functions. However, the current situation is that a huge amount of energy is expended for this portion, and the entire wafer has to be made into a single crystal.
上述の前者の場合には、1枚のウエーハ或は1
つのチツプ内の任意の部分を選択的に各素子の機
能に適した任意の面方位に変えることが出来れ
ば、各素子共に充分な機能を発揮させることがで
きるので極めて好ましい。また後者の場合には、
多結晶、非晶質、焼結体等の単結晶でない基板の
必要な部分のみに、必要な面方位をもつた単結晶
を形成できれば、単結晶引上げという莫大な電力
を必要とする工程がなくなり、工程の短縮とエネ
ルギーの節約ができ、さらに不必要な部分を多結
晶にしておけば各素子間の電気的絶縁性も良く、
半導体素子を作る上でも好ましい。 In the former case, one wafer or one
It is extremely preferable if any part of a single chip can be selectively changed to any surface orientation suitable for the function of each element, since this will allow each element to perform its function satisfactorily. Also, in the latter case,
If single crystals with the required plane orientation can be formed only in the necessary portions of non-single crystal substrates such as polycrystals, amorphous materials, sintered bodies, etc., the process of pulling single crystals, which requires an enormous amount of power, can be eliminated. , it shortens the process and saves energy, and if unnecessary parts are made of polycrystalline, the electrical insulation between each element is also good.
It is also preferable for making semiconductor devices.
本発明は、上述の点に鑑み、簡単な方法で半導
体基板内の必要な領域部に選択的な所定面方位の
単結晶領域を形成できるようにした、半導体の再
結晶法を提供するものである。 In view of the above-mentioned points, the present invention provides a semiconductor recrystallization method that enables selectively forming a single crystal region with a predetermined plane orientation in a necessary region in a semiconductor substrate using a simple method. be.
以下、本発明による半導体の再結晶法を説明す
る。 Hereinafter, a semiconductor recrystallization method according to the present invention will be explained.
先づ、第1図を用いて本発明の原理を説明す
る。本発明は、第1図に示すように{hkl}面方
位の半導体基板1を設け、この基板1上に部分的
に薄い金属片2を形成し、さらにこの金属片2上
に{h′k′l′}面方位で基板1と同一材料の半導体
片3を形成する。この半導体試料を金属―半導体
の共晶点の温度Tcより高く且つ半導体の融点Ts
より低い温度Tx(Tc<Tx<Ts)に保ち、同時
にその温度Txを中心に基板1側の温度が高く、
半導体片3側の温度が低くなる様な、即ち図示の
ようにTx1>Tx2>Tx3となるような温度勾配を
付ける。かくすると、金属片2附近の温度が金属
片2の融点より低い時は金属―半導体との二つの
境界面から溶けはじめ、又金属片2附近の温度が
金属片2の融点より高い場合は金属片全体が溶け
はじめる。液体となつた金属或は固溶体と、固体
半導体との二つの境界面のうち温度の高い方で
は、温度の低い方より半導体をより多く溶解でき
る。そして、この溶解された半導体が温度の高い
境界面から温度の低い境界面へと拡散し、その温
度の低い境界面に達すると、ここでは温度の高い
境界面ほどには半導体を溶解することが出来ない
から、この温度の低い境界面で半導体が析出す
る。この時、種結晶があれば、それと同じ面方位
を受け継いで単結晶が成長する。従つて図示の場
合には液体金属、厳密には金属―半導体の溶融物
が半導体基板1中を温度の高い方へ移動する事に
なり、移動した後の半導体の面方位は温度の低い
方の半導体片3の面方位{h′k′l′}となる。 First, the principle of the present invention will be explained using FIG. In the present invention, as shown in FIG. A semiconductor piece 3 made of the same material as the substrate 1 is formed with the plane orientation 'l'. This semiconductor sample is heated to a temperature higher than the metal-semiconductor eutectic point Tc and the semiconductor melting point Ts.
While maintaining a lower temperature Tx (Tc<Tx<Ts), at the same time the temperature on the substrate 1 side is high around that temperature Tx,
A temperature gradient is created so that the temperature on the semiconductor piece 3 side becomes lower, that is, Tx 1 > Tx 2 > Tx 3 as shown in the figure. Thus, when the temperature near the metal piece 2 is lower than the melting point of the metal piece 2, melting starts from the two metal-semiconductor interfaces, and when the temperature near the metal piece 2 is higher than the melting point of the metal piece 2, the metal begins to melt. The entire piece begins to melt. Of the two interfaces between the liquid metal or solid solution and the solid semiconductor, more semiconductor can be dissolved at the higher temperature interface than at the lower temperature interface. Then, this melted semiconductor diffuses from the high-temperature boundary surface to the low-temperature boundary surface, and when it reaches the low-temperature boundary surface, it is not able to melt the semiconductor as much as the high-temperature boundary surface. Since this is not possible, semiconductors precipitate at this low-temperature interface. At this time, if there is a seed crystal, a single crystal will grow by inheriting the same plane orientation. Therefore, in the case shown in the figure, the liquid metal, strictly speaking, the molten metal-semiconductor, moves in the semiconductor substrate 1 toward the higher temperature side, and after moving, the plane orientation of the semiconductor is the one at the lower temperature side. The surface orientation of the semiconductor piece 3 is {h′k′l′}.
第1図では半導体基板1を{hkl}面方位の単
結晶基板を用いたが、その他半導体基板1を多結
晶半導体基板に置き代えても、その溶融物が移動
した後の半導体の結晶方位は半導体片3の方位
{h′k′l′}を引きつぐ。 In Fig. 1, a single crystal substrate with {hkl} plane orientation is used as the semiconductor substrate 1, but even if the semiconductor substrate 1 is replaced with a polycrystalline semiconductor substrate, the crystal orientation of the semiconductor after the melt moves The orientation {h′k′l′} of the semiconductor piece 3 is inherited.
本発明は、以上の原理にもとづいて、半導体基
板上に選択的に基板と異なる所望面方位をもつ単
結晶領域を形成するものである。 The present invention is based on the above principle to selectively form a single crystal region on a semiconductor substrate having a desired plane orientation different from that of the substrate.
次に、本発明の実施例を述べる。 Next, examples of the present invention will be described.
実施例 〔〕
第2図Aに示すように{111}面方位をもつ厚
さ約300μmのシリコン単結晶基板10上に、通
常の真空蒸着法により選択的にシルミニウム
(Al)を蒸着して厚さ約30μmのアルミニウム層
11a及び11bを形成し、更に夫々のアルミニ
ウム層11a及び11b上に{100}面方位をも
つシリコン単結晶片12及び{110}面方位をも
つシリコン単結晶片13を物理的に載せ、かかる
試料全体の平均温度が1000℃〜1050℃となるよう
にする。さらに、この試料に対して基板10側が
シリコン片12,13側より高温となるように約
100℃/cmの温度勾配を付し、1時間、真空中で
アルミニウム層11a,11bを熱移動させた。
この処理で試料は第2図Bの如き構造となつた。
次いで、この試料を、その基板10上に選択的に
存する{100}面方位及び{110}面方位のシリコ
ン片12及び13と、基板10の裏側に熱移動し
たアルミニウム層11a,11bとが無くなるよ
うに、上下両面から鎖線14の位置まで機械的に
カツテイング又は削り取り、透過ラウエ写真を撮
つた結果、第2図Bの領域Aは{111}面方位を
もつ単結晶であり、領域Bは{100}面方位をも
つ単結晶であり、領域Cは{110}面方位をもつ
単結晶であることが認められた。[Example] As shown in FIG. 2A, on a silicon single crystal substrate 10 having a {111} plane orientation and a thickness of approximately 300 μm, silminium (Al) was selectively deposited by a normal vacuum evaporation method to increase the thickness. Aluminum layers 11a and 11b with a thickness of about 30 μm are formed, and a silicon single crystal piece 12 having a {100} plane orientation and a silicon single crystal piece 13 having a {110} plane orientation are further formed on the aluminum layers 11a and 11b, respectively. The average temperature of the entire sample is 1000°C to 1050°C. Furthermore, for this sample, approximately
A temperature gradient of 100° C./cm was applied, and heat was transferred between the aluminum layers 11a and 11b in a vacuum for 1 hour.
Through this treatment, the sample had a structure as shown in FIG. 2B.
Next, the silicon pieces 12 and 13 with the {100} plane orientation and the {110} plane orientation selectively present on the substrate 10 and the aluminum layers 11a and 11b that have been thermally transferred to the back side of the substrate 10 are removed from this sample. As a result of mechanically cutting or scraping from both the upper and lower surfaces to the position of the chain line 14 and taking a transmission Laue photograph, the results show that region A in FIG. 2B is a single crystal with {111} plane orientation, and region B has { It was confirmed that it was a single crystal with a {100} plane orientation, and region C was a single crystal with a {110} plane orientation.
実施例 〔〕
第3図に示すように、{100}面方位をもつ厚さ
約300μmのシリコン単結晶基板15上に、通常
の真空蒸着法により選択的に錫(Sn)を蒸着し
て厚さ約30μmの錫層16a及び16bを形成
し、更に夫々の錫層16a及び16b上に
{111}面方位をもつシリコン単結晶片17及び
{110}面方位をもつシリコン単結晶片18を物理
的に載せ、かかる試料全体の平均温度が1000℃〜
1050℃となるようにする。さらに、この試料に対
して基板15側がシリコン片17,18側より高
温となるように約100℃/cmの温度勾配を付し、
10分間、高純度N2雰囲気中で錫層16a,16
bを熱移動させた。この処理で試料は第3図Bの
如き構造となつた。次いで、基板15上の
{111}面方位のシリコン片17及び{110}面方
位のシリコン片18が無くなる鎖線19の位置ま
で基板15の表面を機械的にカツテイング又は削
り取り、反射ラウエ写真を撮つた結果、第3図B
の領域A′は{100}面方位をもつ単結晶であり、
領域B′は{111}面方位をもつ単結晶であり、領
域C′は{110}面方位をもつ単結晶であることが
認められた。[Example] As shown in FIG. 3, tin (Sn) was selectively vapor-deposited using a normal vacuum evaporation method on a silicon single-crystal substrate 15 having a {100} plane orientation and a thickness of approximately 300 μm. Tin layers 16a and 16b with a thickness of approximately 30 μm are formed, and a silicon single crystal piece 17 having a {111} plane orientation and a silicon single crystal piece 18 having a {110} plane orientation are formed on the tin layers 16a and 16b, respectively. The average temperature of the whole sample is 1000℃~
The temperature should be 1050℃. Furthermore, a temperature gradient of approximately 100° C./cm was applied to this sample so that the substrate 15 side was higher than the silicon pieces 17 and 18 side.
Tin layers 16a, 16 in a high purity N2 atmosphere for 10 minutes
b was thermally transferred. Through this treatment, the sample had a structure as shown in FIG. 3B. Next, the surface of the substrate 15 was mechanically cut or scraped to the position of the chain line 19 where the silicon pieces 17 with the {111} plane orientation and the silicon pieces 18 with the {110} plane orientation on the substrate 15 disappeared, and a reflection Laue photograph was taken. Result, Figure 3B
Region A′ is a single crystal with {100} plane orientation,
It was recognized that region B' was a single crystal with {111} plane orientation, and region C' was a single crystal with {110} plane orientation.
実施例 〔〕
第4図Aに示すように、通常の真空蒸着法で厚
さ約20μmのアルミニウム層21a及び21bを
蒸着した夫々{100}面方位をもつシリコン単結
晶片22及び{111}面方位をもつシリコン単結
晶片23を、厚さ約500μmの多結晶シリコン基
板20上に該夫々のアルミニウム層21a及び2
1bが基板20に接するように選択的に接触さ
せ、かかる試料全体の平均温度が1050℃〜1100℃
になるようにする。さらにこの試料に対して多結
晶基板20側が単結晶片22,23側より高温と
なるように約100℃/cmの温度勾配を付し、1時
記、高純度N2雰囲気中でアルミニウム層21
a,21bを熱移動させた。この処理で試料は第
4図Bの如き構造となつた。次いで、この試料の
表裏両面を鎖線24まで機械的にカツテイング又
は削り取り、透過ラウエ写真を撮つた結果、第3
図Bの領域A″は多結晶であり、領域B″は{100}
面方位をもつ単結晶であり、領域C″は{111}面
方位をもつ単結晶であることが認められた。[Embodiment] As shown in FIG. 4A, a silicon single crystal piece 22 having a {100} plane orientation and a {111} plane orientation were deposited with aluminum layers 21a and 21b having a thickness of about 20 μm by a normal vacuum evaporation method. A silicon single crystal piece 23 having an orientation is placed on the respective aluminum layers 21a and 2 on a polycrystalline silicon substrate 20 with a thickness of approximately 500 μm.
1b is brought into selective contact with the substrate 20, and the average temperature of the entire sample is 1050°C to 1100°C.
so that it becomes Furthermore, a temperature gradient of about 100°C/cm was applied to this sample so that the polycrystalline substrate 20 side was higher than the single crystal pieces 22 and 23 side, and the aluminum layer 21 was heated in a high-purity N 2 atmosphere for 1 hour.
a, 21b were subjected to heat transfer. Through this treatment, the sample had a structure as shown in FIG. 4B. Next, both the front and back sides of this sample were mechanically cut or scraped down to the chain line 24, and a transmission Laue photograph was taken.
Area A″ in Figure B is polycrystalline, and area B″ is {100}
It was confirmed that it was a single crystal with a plane orientation, and that region C'' was a single crystal with a {111} plane orientation.
実施例 〔〕
第5図に示すように、通常の真空蒸着法で厚さ
20μmのアルミニウム層26a及び26bを蒸着
した夫々{100}面方位をもつシリコン単結晶片
27及び{111}面方位をもつシリコン単結晶片
28を、厚さ約500μmの多結晶シリコン基板2
5上に該アルミニウム層26a,26bが基板2
5に接するように選択的に接触させ、かかる試料
全体の平均温度が1050℃〜1100℃になるようにす
る。さらに、この試料に対して、多結晶基板25側
が単結晶片27,28側より高温となるように約
100℃/cmの温度勾配を付し、10分間、1×
10-5Torrの真空中でアルミニウム層26a,2
6bを熱移動させた。この処理で試料は第5図B
の如き構造となつた。次いで、この試料の単結晶
片27,28側の表面を鎖線29の位置までカツ
テイング又は削り取り、反射ラウエ写真を撮つた
結果、第5図Bの領域A″は多結晶であり、領域
B″は{100}面方位をもつ単結晶であり、領域
C″は{111}面方位をもつ単結晶であることが認
められた。Example [] As shown in Figure 5, the thickness was
A silicon single crystal piece 27 having a {100} plane orientation and a silicon single crystal piece 28 having a {111} plane orientation, on which aluminum layers 26a and 26b of 20 μm are deposited, are placed on a polycrystalline silicon substrate 2 with a thickness of approximately 500 μm.
The aluminum layers 26a and 26b are on the substrate 2
5 so that the average temperature of the entire sample is 1050°C to 1100°C. Furthermore, with respect to this sample, approximately
1× for 10 minutes with a temperature gradient of 100℃/cm
Aluminum layers 26a, 2 in a vacuum of 10 -5 Torr
6b was thermally transferred. With this treatment, the sample is shown in Figure 5B.
It became a structure like this. Next, the surface of this sample on the side of the single crystal pieces 27 and 28 was cut or scraped to the position of the chain line 29, and a reflection Laue photograph was taken. As a result, the region A'' in FIG.
B″ is a single crystal with {100} plane orientation, and the area
It was confirmed that C″ is a single crystal with {111} plane orientation.
尚、上記の{111}という記号は(111),
(111),(111),(111),(111),(111),(111
),
(111)面の総称である。 The symbol {111} above is (111),
(111), (111), (111), (111), (111), (111
),
It is a general term for (111) planes.
同様に、{100}は(100),(010),(001),
(100),(010),(001)面の総称であり、{110}は
(110),(101),(011),(110),(110),(101
),
(101),(011),(011),(110),(101),(011
)面
の総称である。 Similarly, {100} is (100), (010), (001),
(100), (010), (001) planes, {110} is (110), (101), (011), (110), (110), (101
),
(101), (011), (011), (110), (101), (011
) is a general term for surfaces.
又、上記実施例においては、半導体としてSiを
用い、液体となる物質としてAl,Sn等を使用し
たが、本発明はこれに限るものではない。例えば
半導体としてはSiの他、Ge,GaAs,GaP,SiC
等を用いることが出来る。又液体となる物質とし
ては必ずしも半導体よりも融点が低い必要はな
く、半導体と固溶体を作りその共晶点における温
度が半導体の融点より低い物質であれば良い。さ
らに、この液体となる物質は1種類に限らず、2
種類以上使用することも出来る。 Furthermore, in the above embodiments, Si was used as the semiconductor and Al, Sn, etc. were used as the liquid substance, but the present invention is not limited thereto. For example, in addition to Si, semiconductors include Ge, GaAs, GaP, and SiC.
etc. can be used. Further, the substance that becomes a liquid does not necessarily have to have a melting point lower than that of the semiconductor, but may be any substance that forms a solid solution with the semiconductor and whose temperature at the eutectic point is lower than the melting point of the semiconductor. Furthermore, the substance that becomes this liquid is not limited to one type, but two types.
It is also possible to use more than one type.
上述せる如く、本発明によれば、所定の面方位
をもつ半導体単結晶基板に対してその任意の部分
を選択的に任意の面方位に再結晶させることが出
来る。従つてこれを半導体集積回路等に適用した
場合、1枚の半導体ウエーハ或は1つのチツプ内
に各素子の機能に適した面方位を形成することが
でき、各素子共に充分な機能を発揮するすぐれた
半導体集積回路が得られる。 As described above, according to the present invention, any part of a semiconductor single crystal substrate having a predetermined plane orientation can be selectively recrystallized into any plane orientation. Therefore, when this is applied to semiconductor integrated circuits, etc., it is possible to form a surface orientation suitable for the function of each element within one semiconductor wafer or one chip, and each element can perform its full function. An excellent semiconductor integrated circuit can be obtained.
又、多結晶半導体基板に対しても、その任意の
部分を選択に必要な面方位をもつ単結晶を形成で
きるので、この場合には単結晶引上げという莫大
な電力を必要する工程が省略され、エネルギーの
節約が出来ると同時に、さらに不必要部が多結晶
として残存するので各素子間の電気的絶縁性が良
くなり信頼性の高い半導体素子が得られるもので
ある。 Furthermore, since it is possible to form a single crystal with the necessary plane orientation in any part of a polycrystalline semiconductor substrate, in this case, the process of pulling the single crystal, which requires an enormous amount of power, is omitted. Not only can energy be saved, but since unnecessary portions remain as polycrystals, electrical insulation between each element is improved and a highly reliable semiconductor element can be obtained.
第1図A及びBは本発明の原理的説明に供する
工程図、第2図A及びB乃至第5図A及びBは
夫々本発明の実施例を示す工程図である。
1は半導体基板、2は金属片、3は所定面方位
をもつ導体片である。
FIGS. 1A and 1B are process diagrams for explaining the principle of the present invention, and FIGS. 2A and B to 5A and B are process diagrams showing embodiments of the present invention, respectively. 1 is a semiconductor substrate, 2 is a metal piece, and 3 is a conductor piece having a predetermined surface orientation.
Claims (1)
に所定の面方位をもつた上記基板と同一材料の単
結晶半導体片を設け、上記基板を金属―半導体の
共晶点以上の温度にし、且つ基板裏面の温度を基
板表面の温度より高くして上記金属一半導体の溶
融物を基板裏面側に移動させ、選択的に上記所定
面方位の単結晶を再結晶させることを特徴とする
半導体の再結晶法。1. A thin metal piece and a single crystal semiconductor piece made of the same material as the substrate and having a predetermined plane orientation are provided on a selected portion of the surface of the semiconductor substrate, and the temperature of the substrate is raised to a temperature equal to or higher than the metal-semiconductor eutectic point, and Semiconductor re-crystallization, characterized in that the temperature of the back surface of the substrate is made higher than the temperature of the surface of the substrate, the metal-semiconductor melt is moved to the back surface of the substrate, and the single crystal with the predetermined plane orientation is selectively recrystallized. Crystal method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13747477A JPS5470764A (en) | 1977-11-16 | 1977-11-16 | Recrystallization method for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13747477A JPS5470764A (en) | 1977-11-16 | 1977-11-16 | Recrystallization method for semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5470764A JPS5470764A (en) | 1979-06-06 |
| JPS6161250B2 true JPS6161250B2 (en) | 1986-12-24 |
Family
ID=15199449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13747477A Granted JPS5470764A (en) | 1977-11-16 | 1977-11-16 | Recrystallization method for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5470764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6414436U (en) * | 1987-07-14 | 1989-01-25 |
-
1977
- 1977-11-16 JP JP13747477A patent/JPS5470764A/en active Granted
Non-Patent Citations (2)
| Title |
|---|
| JOURNAL OF APPLIED PHYSICS=1964 * |
| SOLID STATE PHYSICS=1975 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6414436U (en) * | 1987-07-14 | 1989-01-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5470764A (en) | 1979-06-06 |
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