JPS6161309B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronizer that temporarily stores an input video signal from, for example, another station in a buffer memory and synchronizes the input video signal with a reference, for example, a synchronization sequence of a key station.

A frame synchronizer obtains data synchronized with a reference synchronization signal by supplying a reference synchronization signal sequence to the read side of the buffer memory. First, a frame synchronizer proposed by the applicant will be described.

As shown in FIG. 1, the main memory device includes M ₀ ,
It consists of four memories: M ₁ , M ₂ , and M ₃ . The total memory capacity of the memories M ₀ to _{M 3} is set to be equal to or more than one frame of digital video signal (data). Serial-to-parallel converters S/P ₀ to S/P ₃ are provided as input buffers for each memory, and a predetermined number of samples of the input digital video signal (input data) Din are sequentially supplied to each memory. ₀
~ _M3 , a predetermined number of samples are written in parallel. R/ in relation to each of the memories M ₀ to M ₃
W (write, read) control circuit 1a, 1b, 1
c and 1d are provided, from which write signals WE ₀ to WE ₃ and read signals RE ₀ to _{RE 3} are generated for the corresponding memories. Memory M ₀ and
The data read from M ₂ is fed to the parallel-to-serial converter P/S ₀ as an output buffer, and the data read from the memory M ₁
The data read from M3 and _M3 is supplied to the parallel-to-serial converter P/ _S1 as an output buffer. The serial outputs of the parallel-to-serial converters P/S ₀ and P/S ₁ are taken out alternately by the multiplexer 2, thereby obtaining a digital video signal (output data) Dout synchronized with the reference synchronization series.

The input data Din is sequentially supplied to the above-mentioned serial-parallel converters S/P ₀ to S/P ₃ in units of a predetermined number of samples. When digitizing an NTSC color video signal, if the sampling frequency fs is increased by four times the color subcarrier fsc, the data period in one line section 1H includes 910 samples of data. Therefore, if writing to and reading from memories _M0 to _M3 is performed with 7 samples as one block, there will be 130 blocks in 1H. In order to sequentially input each block of this input data Din to the serial/parallel converters S/P ₀ to S/P ₃ , the supply of the write clock WC is controlled by gate circuits G ₀ to _{G 3} .

The configuration that generates the gate pulses WEN ₀ to WEN ₃ for controlling the gate circuits G ₀ to G ₃ and other necessary pulses and the address signals AD ₀ to AD ₃ for the blocks (horizontal direction) of the memories M ₀ to M ₃ is the first one. This is shown in Figure 2. The write clock WC of the bit period extracted from the input data Din is the write cycle counter.
WCC is supplied to form a write cycle clock WCC having a block period, and this cycle clock WCC is supplied to the write side address counter PAW. In addition, the read clock RC synchronized with the reference synchronization signal is the read cycle counter RCC.
A read cycle clock RCC with a block period is formed, and this cycle clock
RCC is supplied to the read side address counter PAR. One of the write-side and read-side address codes generated from address counters PAW and PAR, respectively, is taken out by selectors 3a, 3b, 3c, and 3d and applied to a decoder (not shown), from which memory M ₀ Block address signals AD ₀ -AD ₃ for M ₃ are generated.
Selection of a write or read address by the selectors 3a to 3d corresponds to a write or read operation of the memories _M0 to _M3 .

A pulse WENBL that becomes "1" corresponding to the 1H data period of the input data Din is supplied to the multiplexer 4a, and the cycle counter
WCC borrow signal WCCBR is supplied to multiplexer 4b. The lower two bits of address counter PAW become an address specifying memories _M0 to _M3 , and the upper bits become a write block address. By switching the multiplexers 4a and 4b using these lower two bits, the pulse WENBL becomes a pulse with a width of one block.
The borrow signal WCCBR is divided into four phases WEN ₀ to WEN ₃ , and the borrow signal WCCBR is divided into four phases of borrow signals WCBR ₀ to WCBR ₃ , each having an interval of one block. Since the gate circuits G ₀ to _{G 3} are turned on by the pulses WEN ₀ to WEN ₃ , the input data Din is
One block is serially input to S/P ₀ to S/P ₃ .
Furthermore, input during a write operation is prohibited by write pulses WE ₀ to _{WE 3} .

For simplicity, if we consider the case where the input data Din has no frequency deviation from the reference synchronization sequence and is simply asynchronous, the operation of the frame synchronizer described above is as follows:
This is shown in the time chart of FIG. Cycle clock WCC of block period, cycle counter
WCC borrow signal WCCBR, borrow signal
WCBR ₀ to WCBR ₃ have the timing relationship shown in Figure 3, and the input data Din is connected to the serial/parallel converter S/P _i
(i=0 to 3) are input sequentially.

In addition, the cycle clock RCC from the read cycle counter RCC is
data is written and read in synchronization with the cycle clock RCC. The lower 2 bits of the address counter PAR (memory M ₀
~ _M3 ) is used to control multiplexer 5, and the borrow signal of cycle counter RCC is
RCCBR is divided into four-phase borrow signals RCBR ₀ to RCBR ₃ , and each is applied to memory control circuits 1a to 1d. The timing for loading data read from memories M ₀ to _{M 3} into parallel-to-serial converters P/S ₀ and P/S ₁ is defined by load pulses PSLD ₀ and PSLD ₁ , and the timing for serial output is determined by read clock RC. is defined by pulses PSEN ₀ and PSEN ₁ . Since the data from the memories M ₀ and M ₂ are loaded into the parallel-serial converter P/S ₀ , the OR output of the read signals RE ₀ and RE ₂ and the AND output of the borrow signal RCCBR are performed as shown in FIG. is the load pulse
PSLD is assumed to be ₀ . Similarly, read signals RE ₁ and
The AND output of the OR output of RE ₃ and the borrow signal RCCBR is used as the load pulse PSLD ₁ . In addition, the pulses PSEN ₀ and PSEN ₁ are the address counter PAR
PSEN ₀ may be used as the pulse for switching the multiplexer 2 for output data extraction.

Referring again to FIG. 3, the input data taken into the serial/parallel converter S/P _i in synchronization with the cycle clock WCC is the write signal WE formed from the borrow signal WCBR _i and the cycle clock RCC. are sequentially written into memories M ₀ to M ₃ by . Furthermore, the read signal RE formed from the borrow signal RCBR _i and the cycle clock RCC is delayed.
Data is sequentially read out from memories M ₀ to M ₃ by , and is alternately loaded into parallel-to-serial converter P/S _j by load pulse PSLD _j (j=0, 1).
Then, output data Dout is taken out from the parallel-serial converter P/S _j via the multiplexer 2.

The time chart in Figure 3 shows that there is no frequency deviation between the input side and the output side, and the cycle clock
This shows the case where the periods t _W and t _R of WCC and RCC are (t _W = t _R . On the other hand, the time chart in FIG. 4 explains the case where (t _W < t _R ). The time chart in Fig. 5 is (t _W >
t _R ).

As described above, for example, seven samples of the input data Din are sequentially input to the serial-to-parallel converter S/P _i by the write clock WC.

In the case of (t _W <t _R ), read access may be executed to two memories simultaneously. In the diagram of [S/P _i →M _i ] in FIG.
This is the case when two numbers are entered during one cycle. Furthermore, as shown in [M _i →S/P _i ], there are cycles in which read access is executed to two memories at the same time, and cycles in which read access is suspended. This series parallel converter S/P
The data read from memory at _j is a pulse
It is regularly output in series by PSEN ₀ and PSEN ₁ , and output data Dout is obtained.

Furthermore, in the case of (t _W >t _R ), as shown in the diagram [S/P _j →M _i ] in FIG. 5, a cycle may occur in which no write access is executed.
However, similarly to the above, the data read from the memory to the serial/parallel converter S/P _j is a pulse
It is regularly output in series by PSEN ₀ and PSEN ₁ . In this manner, the frame synchronizer described above simultaneously executes read access or write access to two memories.
For this reason, an address register (not shown) is provided to hold the block address signals supplied to the memories _M0 to _M3 .

In the frame synchronizer described above (the same applies to frame synchronizers with other configurations), the frequency deviation (t _W <t _R , t _W >
t _R ) causes the problem of "occurrence of overtaking". For the sake of simplicity, it is assumed that one frame is composed of five lines 0 to 4, and that detection of "occurrence of overtaking" and countermeasures are performed line by line. It is also assumed that the capacity of the memory section of the frame synchronizer exceeds one frame, and that a method is adopted in which the start address of each frame is not fixed and circulates on the memory.

The transmission rate of the input data Din is the output data Dout
If it is higher than that, as shown in Figure 6A, there will be data that is written and picked up without being read once, and in the opposite case, the same data will be written twice as shown in Figure 6B. Reading happens. Figure 6A
In either case, when overtaking is detected, the start address of the line stored on the write side is loaded into the address counter on the read side.

Further, when the input data Din is switched to another data midway through a cut, an unnaturalness occurs at the next cut. To explain with reference to FIG. 7, the screen with the letter "A" (one screen represents one field) shows the input data of the channel, and the screen with the letter "B" shows the input data of the other channel. , and when the cut is switched, the input data Din from one channel to the other channel is changed as shown in FIG. 7A.
The switching is made. Cut switching is said to be synchronized with the field pulse of a new channel after a cut switching request occurs, but since there is no signal synchronization relationship between both channels, the signal for both line and field is synchronized. There is a discrepancy. Further, a write clear pulse of a frame period is formed in synchronization with a frame pulse of input data Din, whereas a read clear pulse is formed in synchronization with a frame pulse formed from a reference signal. If the input data Din is switched and the write and read operations are continued as they are, the image based on the read data (output data Dout) will appear after the top of the screen "A" as shown in FIG. 7A. One field of the "B" screen with a shift in the line direction continues, and then the lower part of the "A" screen based on the data read twice in the remaining period of one frame continues, and the next field is It becomes unnatural.

Figure 7C that does not cause such unnatural seams
It is desired that the screen changes as shown in the figure below. For this purpose, the following processing is required.

(1°) When a cut switching request occurs, the input data Din is switched in synchronization with the field pulse FLDP of other channels. Along with this, writing to the memory is prohibited.

(2°) On the read side, after reading partway through the last frame of the channel, which is the write-inhibited period, the line following the previous frame is read to prevent unnatural joints.

(3゜) This write protection is applied to the next write clear pulse (frame pulse) of other channels.
FRMP). At the start of writing after this release, the start address of the frame immediately before entering the inhibited state is saved and loaded into the address counter on the writing side.

Attempting to implement the processing required at the time of overtaking or cut switching as described above using a logic circuit centered on a counter would be extremely complicated, and the wiring between each IC circuit would also be complicated.

The present invention uses RAM (random access memory) to construct an address map, thereby making it possible to easily implement the processing required when overtaking occurs or when a cut is changed.

An embodiment in which the present invention is applied to a frame synchronizer as described above will be described below. FIG. 8 shows an example in which an address control circuit according to the present invention is added to the read/write address counters PAW and PAR shown in FIG. The block diagram of the address signal generation circuit shown in FIG. In FIG. 8, 6 indicates an address map composed of RAM. The starting address of each line of one frame is written into the address map 6. The address code generated from the block address counter PAW is held by a register 7, and the output of this register 7 is used as a parallel input to the address map 6. The address signal from the decoder 8 specifies the write or read address of the address map 6. Address map 6 is
It has addresses corresponding to 525 lines from 0 to 524. A line clock LAWCK synchronized with the input digital video signal of the frame synchronizer is supplied to the line address counter LAW, and the frame pulse of the input digital video signal is
Counter LAW is cleared by FRMPW. Also, the line clock LARCK formed from the reference synchronization signal is used as the line address counter LARK.
is supplied, and the line address counter LAR is cleared by the frame pulse FRMPR, which is also formed from the reference synchronization signal.
One of the outputs of the line address counters LAW and LAR is selected by the multiplexer 9 and supplied to the decoder 8. Multiplexer 9 outputs the address counter within one period of the cycle clock RCC.
The LAW and LAR outputs are alternately given to the decoder 8.

The address counter PAW on the write side counts the cycle clock WCC passed through the multiplexer 10 within the "1" period of the pulse WENBL, as explained with reference to FIG. The multiplexer 10 is provided because it is necessary to supply one cycle clock when a specific start address is loaded into the address counter PAW by a load pulse PAWLD generated at the time of cut switching, which will be described later. Read side address counter PAR
is to count the cycle clock RCC within the period of "1" of the pulse RENBL. As described above, the clock address code generated from the address counters PAW and PAR is provided to the memory of the frame synchronizer.

A write pulse is generated from the NAND gate 11 at a predetermined timing in order to write the first address to the address map 6. nand gate 1
1 includes cycle clock RCC, pulse WMR,
A write inhibit pulse is provided. A write command WM is generated from the flip-flop 12a, and a cycle clock is generated by the flip-flop 12b.
A write command WMR synchronized with RCC is generated. The write inhibit pulse is "1" except when switching the cut.

A load pulse PARLD for loading the first address into the address counter PAR is generated by supplying a read command RM from the flip-flop 13a to the flip-flop 13b.

At the time of cut switching, a write inhibit pulse and a load pulse PAWLD are generated by the circuit configuration shown in FIG. 10, as described later. Operations other than when switching the cut will be explained with reference to the time chart of FIG.

As shown in FIG. 9, consider frame pulses FRMPW and line pulses _HW synchronized with the input digital video signal. 1 line 1 by line pulse H _W
The H period is determined, and the pulse WENBL becomes "1" during the period in which data exists within 1H. However, in FIG. 9, the length of 1H is shown to be much shorter than it actually is to simplify the explanation. Line address clock LAWCK is line pulse H
It has a phase that is more advanced than _W , and rises when the pulse WENBL falls, and this rise causes the line address counter LAW to increment.

In addition, the input digital video signal and the reference synchronization signal are asynchronous, and the frame pulse FRMPR and line pulse H _R are formed from the reference synchronization signal.
is asynchronous with FRMPW and H _W. The pulse RENBL becomes "1" during the data period of the 1H period defined by the line pulse H _R , and at its fall, the line clock LARCK rises, and this rise increments the line address counter LAR.
Various pulses are generated based on the cycle clock RCC shown in FIG. The multiplexer 9 provides the output of the address counter LAW to the decoder 8 during the "1" period (indicated by W) of the cycle clock RCC, and provides the output of the address counter LAR to the decoder 8 during the "0" period (indicated by R) of the cycle clock RCC. Give to 8.

Flip-flop 12a is triggered by the rising edge of line address clock LAWCK, and a write command WM is generated at its output, which is applied to flip-flop 12b. cycle clock
Since RCC is supplied as a clock input to flip-flop 12b, write command WMR
is “1” during one period of the cycle clock RCC.
becomes. Therefore the line address clock LAWCK
The starting address of the line is written to the address map 6 at the line address determined by .

Furthermore, the flip-flop 13a is triggered by the rising edge of the line pulse H _R and a read command RM is generated. Read command RM is flip-flop 1
3b. A cycle clock is supplied as a clock input to the flip-flop 13b, and a load pulse PARLD which becomes "1" is generated in one cycle of the cycle clock. Therefore, the first address of the line address determined by the line address clock LARCK is loaded into the address counter PAR at the rising edge of the load pulse PARLD. After that, as the pulse RENBL becomes “1”,
Address counter by cycle clock RCC
PAR is incremented.

As understood from the above explanation, the address map 6 determined by the line address clock LAWCK
The start address of each line is sequentially written to addresses 0 to 524 of the address map 6, which is determined by the line address clock LARCK.
Starting from address 524, the start address of each line is sequentially loaded into the address counter PAR. This operation is performed continuously. Therefore, if there is a frequency deviation between the input digital video signal and the reference synchronization signal, the address map 6
An overtake occurs between the write address (output of line address counter LAW) and the read address (output of line address counter LAR). As shown in FIG. 6A, when the transmission rate of the input digital video signal is higher than the standard, the write address in the address map 6 precedes the read address, and the difference between the two widens, causing the write address to outpace the read address. As a result, a leading address is generated that is not loaded into the address counter PAR. This results in data being written rather than read from the frame synchronizer memory. Further, as shown in FIG. 6B, if the transmission rate of the input digital video signal is lower than the standard, the read address of the address map 6 will overtake the write address. Therefore, a leading address is generated which is read twice from the address map 6 and loaded into the address counter PAR. This results in data being read twice from the frame synchronizer memory.

Next, the cut switching time will be explained with reference to FIGS. 10 and 11. Cut switching request CUTR
When this occurs, the input data Din to the frame synchronizer is switched to that of another channel. The RS flip-flop 14a is triggered by the cut switching request CUTR, and its output _Q1 becomes "1" as shown in FIG. When the field pulse FLDP and frame pulse FRMPW of new input data have the timing shown in FIG. 11, the output Q ₂ of the flip-flop 14b
becomes “1” in synchronization with this field pulse FLDP.
becomes. The output _Q2 of the flip-flop 14b is supplied to the NOR gate 15, and a write inhibit pulse obtained at the output of the NOR gate 15 inhibits writing of new input data to the memory. At the same time, writing of the start address to the address map 6 is also prohibited. Figure 7C above
As shown in FIG. 3, data is read from the memory of the frame synchronizer while the cut is switched in synchronization with the field pulse of new input data on the "B" screen and writing is prohibited. During this read operation, the address counter
As described above, the start address of each line is sequentially loaded into PAR. Therefore, as shown in FIG. 7C, the predetermined length of data of the previous channel shown on the screen "A" is read out twice, and the seam does not look unnatural. After that, new input data is read.

Before this, the write prohibition period is canceled. In other words, the period from after the field pulse after cut switching until the next frame pulse is the write inhibit period. When the frame pulse FRMPW is supplied to the clear terminal of the flip-flop 14b, its output _Q2 becomes "0". The output _Q2 of the flip-flop 14b is supplied to the flip-flop 16a, and the output _Q3 is supplied to the flip-flop 16b.
supplied to This flip-flop 16a,1
Since the cycle clock RCC (see FIG. 11) is supplied to the flip-flop 6b as a clock input, the output Q ₂ of the flip-flop 14b is synchronized with the cycle clock RCC, and the output Q ₃ , ₃ is in turn synchronized with the cycle clock RCC. output delayed by one period of
Q ₄ and ₄ occur as shown in Figure 11. Then, the output ₃ of the flip-flop 16a and the output _Q4 of the flip-flop 16b are supplied to the AND gate 17, thereby forming a load pulse PAWLD. Further, the output Q ₄ is supplied to the NOR gate 15 to form a write inhibit pulse. In this way, when the write protection is released, the start address loaded into the read side address counter PAR (this matches the start address of the frame immediately before entering the write protection state) is loaded into the read side address counter PAW. Loaded by load pulse PAWLD. The first line of data of one frame of new input data is written from this loaded top address. Furthermore, the line address counter LAW is cleared by the frame pulse FRMPW, and the writing of the starting address to the address map 6 below is the same as described above. This behavior causes
As shown in FIG. 7C, it is possible to prevent the seams on the screen from becoming unnatural when the cut is switched.

As understood from the embodiment of the present invention described above, according to the present invention, at least one frame of the start address of input data is stored in the address map, so overtaking due to frequency deviation between input and output is avoided. It is extremely easy to deal with the occurrence of an outbreak. Furthermore, when a cut is made to switch the input data from one channel to another, it is possible to prevent the next screen from becoming unnatural. Furthermore, by using the address map,
The configuration can be much simpler than configuring a logic circuit using addresses or the like.

In the above embodiment, a frame synchronizer consisting of four memory banks each having an input buffer and two output buffers has been described, but the present invention can be applied to other frame synchronizers. For example, one memory cycle is divided into three phases, the third phase is dedicated to read access, and the others are allocated for write access.When a write access request occurs in the first phase, it is executed in the second phase, and the other phase is allocated for write access. The present invention can also be applied to a frame synchronizer that executes in the first phase of the next memory cycle if it is two-phase, and if there is a write access request in the third phase, executes it repeatedly in the first and second phases. can be applied with similar benefits. Furthermore, when a cut switching request is generated, the cut switching is performed in synchronization with the field pulse, and when a write inhibit operation is entered, the release may be performed using the field pulse instead of the frame pulse. Moreover, it can be applied not only to digital video signals but also to cases where other information digital signals are handled.

[Brief explanation of the drawing]

1 and 2 are block diagrams schematically showing the configuration of an example of a frame synchronizer to which the present invention can be applied, and FIGS. 3 to 5 are time charts used to explain the operation of this frame synchronizer, and FIGS. 7 and 7 are time charts used to explain the present invention, FIGS. 8 and 10 are block diagrams of one embodiment of the present invention, and FIGS. 9 and 11 are used to explain one embodiment of the present invention. It is a time chart. _M0 to _M3 are memories, 1a to 1d are R/W control circuits, PAW is a block address counter on the write side, PAR is a block address counter on the read side, 6 is an address map, and LAW and LAR are line address counters. .

Claims (1)

[Scope of Claims] 1. Retrieving a clock signal associated with an input digital signal, supplying this clock signal to a write address counter, thereby forming a write address signal, and transferring the input digital signal to a main memory by the write address signal. Write to the device, supply the reference clock signal to the read address counter,
A read address signal is formed from this, and the input digital signal is read from the main memory device using the read address signal, and
The input digital signal is divided into predetermined lengths to form an address signal indicating the divided unit, and the address signal is transferred to an address map memory in synchronization with writing of the input digital signal of the predetermined length to the main memory device. and read out the address signal from the address map memory in synchronization with the reading of the input digital signal of the predetermined length, so that overtaking occurs at least between both the write operation and the read operation to the main memory device. At times, the memory control device loads an address signal read from the address map memory into the read address counter. 2. The above address signal is constituted by a leading address signal for the input digital signal of the predetermined length, and this leading address signal is loaded into the read address counter for each block into which the input digital signal is divided. A memory control device according to claim 1.