JPS6210406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting the imaging state of an image, and more specifically, the present invention relates to a method for detecting the imaging state of an image, and more specifically, a method for detecting an image forming state by receiving an image formed by an imaging optical system and using an array of a plurality of photoelectric conversion elements. The present invention relates to an imaging state detection method for an image, in which a signal regarding the imaging state of each minute portion of the image is obtained based on a photoelectric conversion signal from the photoelectric conversion element obtained at this time.

The above image formation state detection method is used, for example, in a so-called image sharpness detection type focus detection device applied to optical equipment such as a camera, and this type of focus detection method has already been used. proposed in the device. For example, the present applicant has proposed a CCD photo sensor, a BBD photo sensor, a photo diode array, or a CCD photo sensor consisting of a combination of a CCD and a photo diode as an array of the plurality of photoelectric conversion elements. A scanning signal of the image is obtained by scanning the image formed by the imaging optical system using an image sensor known as a diode, and based on the scanning signal. to obtain a signal about the illuminance change between two pixels close to each other in the image, that is, a signal about the imaging state of each minute part of the image, and convert this signal into an absolute value and a non-linear conversion signal. A patent application is filed for a focus detection device that, after performing absolute value and nonlinear conversion, integrates this using an integrating circuit to finally obtain an output corresponding to the sharpness of the above image on the above image sensor. The device proposed in Sho 53-92099 is capable of obtaining an image signal that accurately corresponds to the image formation state of the image by scanning the image using an image sensor. Therefore, we can expect a dramatic improvement in the accuracy of sharpness detection and, therefore, focus detection.

By the way, for this type of device, for example,
When considering application to a camera, even if the actual distance is relatively far from the main object whose focus is to be detected within the field of view, the relative positional relationship in the vertical and horizontal directions is There are many cases where a secondary object is located relatively close to the main object, and in such cases, when the focus image of the main object is formed, the above For secondary objects, a defocus image is formed due to the difference in distance between them, but in such a case, the effective receiving area of the array of photoelectric conversion elements is Even if the image is limited to a relatively small size so as to detect only the image, a part of the defocus image of the secondary object will enter the effective receiving area of the photoelectric conversion element array due to the expansion of the defocus, Therefore, there is a great concern that this may impede the detection of the imaging state of the image of the main object, making accurate detection difficult.

Furthermore, in addition to the secondary image on the photoelectric conversion element, interference with image formation state detection is caused by noise contained in the photoelectric conversion element. occurs in each element independently.

In this way, the factors that inhibit the detection of the image formation state are those caused by secondary images on the photoelectric conversion element, that is, noise levels that differ depending on the position of the photoelectric conversion element, and those that are unrelated to the position of the photoelectric conversion element. There are two possible types: one that occurs in

The present invention was made in view of the above-mentioned matters, and aims to simultaneously remove the above two types of noise components by the same processing, and has a structure that uses photoelectric conversion and different levels determined depending on the position of the photoelectric conversion element. Only when the photoelectric conversion element output level is higher than the sum level with a constant level unrelated to the position of the element, a signal with a value determined according to the difference between the above sum level and the photoelectric conversion element output level is photoelectrically converted. This is what is sent out as the output of the element. In this case, as shown in the embodiments detailed below, for example, the nonlinear conversion circuit may have a circuit configuration that utilizes the input-output square characteristic of a field effect transistor (FET). By appropriately adjusting the source potential of this FET using the FET, it is possible to adopt a configuration in which the operating input level of the conversion circuit is appropriately changed. Furthermore, the above-mentioned effects can be easily achieved by using a circuit configuration that is more suitable for integration.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the embodiments of the present invention are described in the image sharpness detection type focus detection apparatus as exemplified above.

FIG. 1 is a conceptual diagram for explaining the imaging state of an image by an imaging optical system, where 1 is an imaging lens and 2 is an optical axis of the lens. The lens forms an image of an object (not shown) at position 3 on the optical axis 2. In this case, considering points 4 and 5 that are equidistant in front and back of position 3, if an image is formed at 3, then
The imaging conditions, especially the sharpness, of the images at the 4th and 5th positions are almost the same. In reality, they are not exactly equal due to spherical aberration and chromatic aberration of the lens. If the imaging point of the line is closer to 4, the sharpness at 4 will be higher than that at 5, and conversely, if the imaging point of the image is closer to 5, the sharpness at 5 will be higher than that at 4. Therefore, by comparing the sharpness of 4 and 5 in some way, the imaging position of the line can be detected. Furthermore, when performing such detection, if 3 is a position equivalent to the expected focal plane where the film or imaging surface of a camera is placed, then by comparing the sharpness at 4 and 5, The imaging positional relationship with respect to the above-mentioned predetermined focal plane is detected, making it possible to demonstrate automatic focus adjustment and the like.

Based on the concept described in Figure 1, Figure 2 shows an example of the arrangement of an optical system for specifically performing focus detection or other information detection, and a light receiving element for detecting an image signal. FIG. 6 in the same figure
is an imaging lens whose optical axis is 7, and 8 is
This is the expected focal plane of the lens, and it is assumed that a film or imaging surface (not shown) is placed thereon. 9
is a semi-transparent mirror that splits a part of the luminous flux that enters through the lens, and the luminous flux reflected by the semi-transparent mirror passes through the luminous flux separation prism 1 disposed below.
At 0, the beam is further separated into two beams. 10' is a semi-transmissive surface, and 10'' is a total reflection surface. 11 and 12 are light-receiving elements. The light-receiving elements are located at equal distances in front and behind a position optically equivalent to the planned focal plane 8, respectively. When the light beam separated by the semi-transparent mirror 9 is further divided into two, an appropriate optical path difference is provided between the two light beams reaching the light receiving element 11 and the light receiving element 12. , an optically equivalent relationship is obtained in which the two light receiving elements are arranged at positions 4 and 5 in FIG.
When performing focus adjustment, if you compare the image formation state generated based on the output of each of the light receiving elements, especially the signals corresponding to the sharpness, it will be determined that the in-focus position is on the expected focal plane. mosquito. Or, it is possible to distinguish whether it is before or after that.

FIG. 3 is a block diagram showing the concept of an embodiment of the present invention for detecting the imaging state of an image and the in-focus position of an image using front and rear light receiving elements. In the figure, numerals 10, 11 and 12 are the aforementioned light beam separating prism and light receiving element, respectively. The light receiving element is composed of, for example, a plurality of photoelectric conversion elements, and has a function of generating the photoelectric output of each element as a time series signal.
It is configured as a photodiode array (MOS image sensor) or a charge transfer device such as a CCD or BBD. In the figure, in order to express these in an integrated manner, 13
It is expressed as The output of the photoelectric output generator 13, that is,
A time-series signal output from each photoelectric conversion element is input to a photoelectric output control section 14 for level control or sample-holding of the signal. The level control described above is described in detail later, but by forming the summation output of multiple photoelectric conversion elements in accordance with the control command of the controller described later, the level control is performed to produce images of the same brightness at different levels. It is possible to generate output. The output of the photoelectric output control section 14 having various functions becomes a time-series signal of the illuminance distribution of the image. Hereinafter, this output will be referred to as an image signal. The image signal lens is controlled by the photoelectric output control section described above, and also by controlling the time for accumulating the photoelectric conversion signal of the image illuminance in each photoelectric conversion element (hereinafter referred to as accumulation time). The following will be done. Generally, the above-mentioned MOS image sensor and charge transfer device have a function of outputting the photoelectric conversion output of each photoelectric conversion element after accumulating it for a predetermined period of time, and in the present invention, as a light receiving element, It is preferable to use such a device.

The accumulation time must be controlled according to the brightness of the image so that the image signal level is always at an appropriate level. In this example, the output of the photoelectric output control section 14 is It is led to the accumulation time control section 15 to perform the above operation. On the other hand, the output of the photoelectric output control section 14, that is, the image signal, is input to an image signal change detection section 16 that detects a change in the signal in order to extract sharpness information therefrom. Specifically, the detection section 16 is constructed of a differentiating circuit or a combination of a delay circuit and a differential circuit, as will be described later. The output of the image signal change detection unit 16 corresponds to an alternating current component other than the direct current component in the image signal, and the amplitude of the alternating current component increases as the clarity increases. The output is inputted to an emphasizing circuit 17 which functions to emphasize components with large amplitudes among these components and to press components with small amplitudes. The output of the enhancement circuit is therefore very sensitive to sharpness. In other words, when the clarity is high and the level difference between brightness and darkness of the image becomes large,
The amplitude of the AC component increases. The larger the amplitude, the more emphasized it becomes, and conversely, the sharpness decreases.If the amplitude of the above-mentioned alternating current component becomes small, the emphasis circuit will be suppressed, and as a result, the sharpness will decrease. As the value increases, the output of the emphasizing circuit increases rapidly. 18 is an emphasis characteristic control for changing the input level at which the emphasis is performed by the emphasis circuit, or changing the degree of the emphasis effect according to the position of the photoelectric conversion element in the image receiving area which is the total of each photoelectric conversion element; Department. Reference numeral 19 denotes a double integration circuit that integrates and inversely integrates the output of the emphasizing circuit 17 over a predetermined image receiving area. The basic operation of the circuit is that the light receiving elements 11 and 1
The output of the image signal corresponding to one of the receptive areas (hereinafter referred to as the visual field) processed up to the enhancement circuit is integrated, and from this integrated value, it is inversely integrated at a predetermined decay rate with respect to time. Therefore, the level of the above integral value is specified. This action is sequentially performed on the outputs of the two light receiving elements that have been processed up to the image signal enhancement circuit, and the respective results are input to the subsequent display control section 20. As can be understood from the above explanation, the above integral value corresponds to the sharpness of the image in the field of view of each light receiving element, so the double integration circuit 19 for each light receiving element field of view
The display control section 20 compares the outputs of the two, and based on the comparison results, a display is performed on the display means 21 such as an LED. By doing so, it is not only possible to know the in-focus position by recognizing the display state of the display means 21, but also it is possible to accurately focus the imaging lens on the predetermined focal plane. be. The above-mentioned light reception and various signal processing or controls are performed according to a predetermined order, and these are performed according to the control output of the controller 22. The specific structure and operation of each of the above parts will be explained below.
The explanation will be given according to detailed drawings.

FIG. 4 shows the generation of photoelectric output and the main signal processing of the output, excluding most of the display control section 20, the display means 21, the controller 22, and the accumulation time control section 15 among the various parts in FIG. FIG. 2 is a circuit diagram showing signal exchange terminals between the system, each part, and other circuits to be described later.

In the figure, the number of each block indicated by a dashed line is
This corresponds to each part of the circuit indicated by the numbers shown in the third figure.
That is, 13 is a photoelectric output generator, and control terminals 22, 23, 24 and FET switches, 26, 2
7 has the function of providing a controlled input to an analog shift register 28 or a CCD, BDD serial input terminal 29 having an equivalent function. That is, a zero set terminal 25 and a full set terminal 24 are provided, and by setting 25 to high, the FET switch 27 is turned on, and the series input terminal 29 is grounded, providing a reference for the minimum level of the output of the photoelectric conversion element described later. . Also, by setting 24 to high, turn on the FET switch of 26,
The reference voltage terminal set corresponding to the maximum output voltage of the photoelectric conversion elements 23 and the series input terminal 29 are short-circuited to provide a maximum level reference for the photoelectric conversion elements and the analog shift register 28.

30 is a plurality of independent photoelectric conversion elements,
Through photoelectric conversion of these elements, a photocharge or photovoltage is generated between each of the 31 points and GND, and the structure can be held or accumulated by junction capacitance and wiring capacitance, and the holding can be released. In order to do this, each of them has a FET-SW 32, and the above-mentioned holding state is released by setting the common control terminal (hereinafter abbreviated as ICG-PS) of the anti-pluming gate indicated by 33 to HIGH. That is, when the anode of the photoelectric conversion element 30 is connected to GND as shown in the figure,
At the 31st point, that is, on the cathode side, a charge or voltage is generated in the direction that the brighter it is with respect to GND, the higher the voltage. The photoelectric conversion element 30
The same number of FETs as 31 points, which are the output points of each
-SW 34 is provided, and has a common control terminal (hereinafter referred to as a shift gate) indicated by 35, and by setting the terminal 35 to HIGH, each photoelectric output is sent through the parallel input terminal 36 of the analog shift register 28. and is transferred to the analog shift register 28.

The analog shift register 28 is a one-way transfer device that has the aforementioned serial input terminal 29 and parallel input terminal 36 and transfers the analog quantity to the right in the figure.
Input clock 37 (φ ₁ ) and output clock 38
(φ ₂ ), and outputs an analog tenter from the serial output terminal shown at 39. This corresponds to a rotating body imaging device such as a CCD or BBD, and the above-mentioned 30, 32, and 34 may also be included in the CCD.

14 is a photoelectric output control unit that receives the output from the image time series of the analog shift register 28 and controls the output, and controls the time series output from 39, that is, the charge or voltage of the output of each photoelectric conversion element. The diode 40 and the resistor 41 convert the charge or current into a voltage, which is stored in a capacitor 42 and added.

Note that if only the charge can be transferred correctly, the diode 40 and the resistor 41 are unnecessary.

The end of addition is reset by turning on the FET-SW 43, and this FET-SW 43 is turned on, ie, reset, by setting its control input terminal 44 to HIGH.

The addition result is sent to the sample hold circuit 47 by a source follower consisting of FET 45 and resistor 46.
can be conveyed to.

The sample hold circuit 47 turns the FET-SW 43 ON when the output, which is the potential of the resistor 46, is at the end of addition, that is, when the terminal indicated by 44 is at HIGH.
This is to prevent the voltage from dropping to 0 volts.

When the control terminal 48 of the sample hold circuit 47 is set to LOW, the sample and hold circuit 47 outputs
A hold value is generated and the next new signal is sampled when the terminal 48 goes HIGH. 4
9 is a power supply terminal of the FET.

Although the photoelectric output generating section 13 and the photoelectric output controlling section 14 described above are illustrated as if they were separate devices in this example, the photoelectric output controlling section 14 is provided as an independent circuit from the photoelectric output generating section 13, that is, as an external circuit. What is provided is a MOS image sensor or a floating gate charge transfer device, and in the so-called voltage output type charge transfer device, the photoelectric output control section 14 is integrally configured as a device, Alternatively, the photoelectric output control section excluding the sample and hold circuit 47 may be configured integrally with the photoelectric output generation section 13 as a device, but its function, basic configuration, and connection relationship may be different from those illustrated here. However, the signal processing method of the present invention can be applied in all cases.

16 is related to the illuminance on the photoelectric conversion element mentioned above, and based on the signal obtained by converting the position of each element into the order of the time series signal, the illuminance according to the temporal change of the time series signal, that is, the position of the photoelectric conversion element This is an image signal change detection unit that extracts changes.

After the terminal 49 becomes HIGH, the sample hold output that is updated when the terminal indicated by 49 is HIGH is changed to 5 until the terminal 49 becomes HIGH next time.
It has a function of keeping the signal at 1 at the same potential as the output signal of the sample hold circuit 47 at that time.

As a result, the output signal is sampled and held by the sample-and-hold circuit 50 at a certain point in time, and subsequent changes in the output signal are caused between the two inputs of the differential amplifier 52. A terminal indicated by 53 is a terminal for controlling the output of the differential amplifier 52, and only when a HIGH signal is applied to the terminal 53, the differential amplifier 52 is activated.
It has the function of allowing output to be generated from other sources, and suppressing the same output to zero otherwise. By temporally masking and eliminating the adverse effects of the transient characteristics of the output due to the sample-and-hold circuits 47, 50 and other circuits described above by the terminal 53, a stable signal is transmitted to the output terminal of the differential amplifier 52. It has the effect of causing

Reference numeral 17 denotes an illuminance change emphasizing circuit, which converts the output signal of the differential amplifier 52, which is the output of the image signal change detecting section 16, into an absolute value, suppresses minute signals, and emphasizes the signal, as described below. This is a circuit that converts current information suitable for an integrator.

Reference numeral 54 denotes a differential output type operational amplifier, and by connecting the positive output indicated by 55 to the inverting input terminal of the amplifier 54, the positive output 55 is output from the differential amplifier 52. The negative going output, which is equal to the non-inverting input of the differential amplifier 52 and shown at 56, produces an output that is inverted in polarity with respect to the non-inverting input from the differential amplifier 52.

57 and 58 are FETs each having the same characteristics, which perform voltage-current conversion, suppression of minute signals, and signal enhancement.

In other words, the gate potential is [source potential] +Vp (Vp
This takes advantage of the characteristics of the device: when the drain current is lower than the pinch-off voltage, almost no drain current flows, and when the gate potential exceeds this, a current flows that is proportional to the square of the exceeded potential difference.

That is, as shown in FIG. 5, the horizontal axis represents the gate potential V,
If the drain current Ids is plotted on the vertical axis, when the gate voltage exceeds the pinch-off voltage Vp, a drain current proportional to the square of the exceeded potential difference flows. Then, by supplying the voltage applied to point 59, that is, the source conditioning voltage (hereinafter referred to as Vs) to the sources of the two FETs, when the gate potential of either FET exceeds the voltage of (Vs + Vp), The drain current proportional to the square of the exceeded potential difference is
Suction from drain 7,58.

As mentioned above, the voltage at point 55 is determined by the differential amplifier 52.
The voltage at 56 points is equal to the inverse of Vin, that is, -Vin, so FET 57 allows current to flow when Vin exceeds (Vs + Vp), and FET 58 - Vin is (Vs+
Current flows when the voltage exceeds Vp).

This situation is shown in FIG.

This is a diagram with the above Vin on the horizontal axis and the sum of the drain currents of both FETs on the vertical axis.The curve on the right side of the diagram is for FET57, and the curve on the left side is for FET5.
This is due to the characteristics of No. 8.

In this way, this circuit converts voltage to current, converts it into an absolute value, suppresses noise and the like by suppressing minute signals below (Vp+Vs), and emphasizes changes in illuminance for focus detection.

Note that the diode 60 is used to prevent malfunction of the integrator, which will be described later, due to current in the reverse direction due to reverse bias of the FET, etc. Generally, the midpoint potential of this circuit is set to be lower than the integrator GND. Since the drain voltage of the FET is obtained, the diode 60 is often unnecessary.

Note that similar elongation characteristics can be obtained by using a transistor or the like instead of the pair of FETs 57 and 58.

Reference numeral 18 denotes an emphasis characteristic control unit which controls the emphasis start level, that is, the suppression level, by setting the voltage Vs shown at 59, which is the control voltage of the illuminance change emphasis circuit 17, and controls the emphasis characteristics as a result. It has a variable effect.

That is, the level indicated by the input terminal 61 is converted into an analog signal by the D/A converter 62, realized at 63 points, and applied to 59 points through an inverting buffer circuit 64 including an operational amplifier.

65 and 66 are resistors. D/A converter 6
2 does not necessarily require multi-bit resolution;
Even in the well-known ladder type D/A converter, it is said that
A D/A converter as shown in the figure may be used.

That is, the D/A converter shown in FIG. 7 is based on a structure in which a constant voltage is generated between point 69 and Vcc by a constant voltage diode 62 and a resistor 68, and a constant current is generated by a resistor 70 and a transistor 71. It is meant to be.

Multiple such constant current power supplies and multiple FETs
- A SW 72 is provided, and the SW is turned on and off by a control terminal indicated by 73, and each constant current passing through the SW is connected to one common output terminal indicated by 74.
It is a D/A converter that converts the total current into voltage using a resistor 75.

By changing the current value of each of these constant currents, for example, 1mA, 2mA, 4mA, etc., each control terminal indicated by 73 is turned on.
The total current is changed by the combination of -off control,
74 output voltage can be changed.

Of course, it is easy to use the constant current characteristics of the FET and use the same FET as the control FET-SW.
It is also possible to turn on different numbers of constant current sources with one control terminal and perform D/A conversion.

Reference numeral 19 is a double integration circuit which is capable of A/D conversion of the integration result, and is based on an operational amplifier 76 and a capacitor 77.

The input control FET-SW 78 is turned on by setting the terminal indicated by 79 to HIGH to enable integral input.

Integration is for input control by setting control terminal 79 to HGIH.
Turn on FET-SW78 and use the above-mentioned emphasis circuit 17.
This is done by sucking out a current corresponding to the output through the diode 60, and the current is
The voltage increase at the output terminal of the operational amplifier 76, that is,
is given through the capacitor 77 by the integral output,
The voltage is added and integrated as the voltage across the capacitor 77. The above mode is called the first slope.

In this way, since the signal from the previous stage is a current, correct integration is guaranteed over a wide dynamic range.

This integral type A/D conversion will now be explained. First, by setting the terminal indicated by 80 to HIGH, the FET-SW is turned on to discharge the capacitor 77, and the operational amplifier 76 is used as a buffer amplifier, and the output voltage of the operational amplifier 76 is reduced to zero. Make it. This state is called integral reset. Next, terminal 8
0 to LOW, FET-SW81 is turned off to enable charging of the capacitor 77, terminal 79 is set to HIGH, input control FET-SW78 is turned on, and the current flows out through the diode 60. As described above, the outflow charge charges the capacitor 77 and increases the output voltage (Vo) of the operational amplifier 76.

The above output voltage Vo at this time is the above outflow current i ₁
Assuming that the capacity of the 77 capacitor is C, Vo
=∫(i ₁ /C)dt.

This mode is the first slope described above.

Next, set the terminal 79 to LOW and use it for input control.
Turn off FET-SW78 to finish the first slave.

Next, a HIGH signal is applied to the terminal indicated by 82, the second slope ST83 is turned on, and the above-mentioned first slope is Contrary to the integration in the state of , inverse integration is performed by current injection. This mode is called the second slope, and the injected current is defined as _i2 . Then, A/D conversion is performed by measuring the time _t2 until the output voltage of the operational amplifier 76 drops and becomes zero (output voltage at the time of reset). That is, at the end of the first slope, Vo=∫(i ₁ /C)dt, and
When the output voltage of the operational amplifier becomes zero at the second slope, ∫ ₀ ^t (i ₂ /C) ^dt , t・i ₂ =V ₀・C=∫
i ₁ dt, and by using a counter to measure the amount of outflow current during the first slope period at the time interval t,
A/D conversion is possible.

Next, log compression type A/D conversion will be explained.

The difference in this case is that the second slope is different from the aforementioned general double integral (dual slope A/D conversion).

That is, unlike the second slope in which inverse integration is generally performed with a constant current, the inverse integration time t is logarithmically compressed by injecting a current that increases exponentially with the inverse integration time from the terminal 84 and inversely integrating it. Therefore, it is possible.

However, since the above method is quite complicated to correctly generate an exponentially increasing current, in this proposal,
Compression type A/D conversion is performed by performing the second slope with a current proportional to the terminal voltage of the capacitor 77.

That is, on the second slope, the terminal indicated by 86 is
This is achieved by turning on the FET-SW 87 by setting it to HIGH, and causing a current proportional to the voltage between the terminals of 77 to flow through the resistor 88.

By measuring the time until the output voltage of the operational amplifier 76 becomes equal to or less than a certain set voltage, log compression type A/D conversion is realized.

However, the above set voltage must be quite accurate, so in this example, the above set voltage is
Based on the log compression type A/D, we add inverse integration using a weak constant current used in general dual slope A/D conversion to approximate the log compression type A/D.
It performs D conversion.

That is, the above-mentioned inverse integration through the resistor 88 under the control of the terminal 86 and the inverse integration using the weak constant current from the terminal 84 under the control of the terminal 82 are performed together, and thereby the operational amplifier 76 determines whether the inverse integration has ended. By simplifying the determination of the output voltage to a comparison with zero potential, the absolute accuracy is constrained to what is necessary for the process, the circuit configuration is simplified, and a compressed approximation is achieved.
The configuration is such that a wide dynamic range can be easily achieved using the digital value of log. 20A is the third
This is a comparator for A/D conversion of the above-mentioned integrating circuit which forms a part of the display control section shown in the figure.

That is, by the comparator 89, the double integration circuit 19
In other words, in the case of a general dual slope, the end of the second slope is detected as zero in the output of the operational amplifier 76, or more precisely, it is detected as being equal to the integrator output at the time of the integral reset. Therefore, when a reference is provided at the terminal indicated by 90 as a comparison reference potential and the integrator output is higher than the reference, a HIGH signal is obtained at the comparison output terminal indicated by 91.

In addition, the way to combine this integrator and comparator is as follows:
There is also a means of canceling out the input offset voltages of the operational amplifier and comparator using circuit configurations as shown in FIGS. 8 and 9.

In FIGS. 8 and 9, 92 is an integral arithmetic amplifier;
93 is an integration capacitor, 94 is a comparator, 95 is an input terminal, 96 is an input control SW, 97 is an input control terminal, 98 is a constant current source for inverse integration, 99 is a second slope control SW, 100 is a second slope control terminal,
101 is a reset control SW, 102 is a reset control terminal, and 103 is a comparison output.

In Figure 8, offset memory SW1
Reset control terminal 1 so that it works when resetting 04.
02, thereby comparator 9 at reset.
4 as a buffer, the resulting offset results of amplifier 92 and comparator 94 are passed through offset memory SW 104 to capacitor 10.
5 and is supplied to a comparator 94 as a comparison reference for performing the double integral operation as described above.

Similarly, Fig. 9 shows that the reset switch is
Through 101, the offset results of the amplifier 92 and comparator 94 are stored as initial values in the integration capacitor 93, and the state in which the comparison output shown at 103 is inverted during the double integration operation as described above is reset. By making it equal to the current state, the offset of the circuit can be canceled out.

Note that 106 is a resistor for preventing oscillation due to an increase in the loop gain due to the direct connection between the amplifier 92 and the comparator 94 during the above-mentioned reset.

Next, another example of the analog circuit will be shown.
FIG. 10 shows an example of a sample-old circuit having an FET configuration, and is an example of a sample-and-hold circuit in which 107 is an input terminal, 108 is an output terminal, and 109 is a control terminal. 109 is the terminal 48 shown in the fourth diagram;
It has the same function as 49.

That is, the signal from the input terminal 107 is sent to the FET1
FET-SW1 is generated by amplifying the current to 112 points by a source follower with resistor 10 and resistor 111, and by setting control terminal 109 to HIGH.
13 is turned on, the potential at 112 points is transferred to the capacitor 114.
By the LOW of the control terminal 109,
Turn off FET-SW113 and hold.

The potential of the capacitor 114 is sampled and held and transmitted to the output terminal 108 by a source follower including an FET 115 and a resistor 116.

In FIG. 11, in order to omit the sample and hold circuit 50 with the differential amplifier 52 of the image signal change detection section 16, the signal is obtained by differentiating the output of the sample and hold circuit 47 in the previous stage by C-R. What you get is 1
This circuit differentiates the change in the input terminal voltage 17 with a capacitor 118 and a resistor 119, and produces the output at the output terminal 120. This allows the number of parts to be reduced significantly.

The analog circuit shown in Figure 4, which uses many FETs and FETSWs, can be easily configured on a single chip by using current Mos-FET technology and Bi-Mos technology, with the exception of some external capacitors. It has a possible structure and is relatively easy to manufacture.

Note that the FET mentioned above has the main purpose of high input impedance, so it can be converted to a Darlington configuration transistor, etc., and the FET-SW is
Although the C-Mos-FET-SW is advantageous in terms of its characteristics, it goes without saying that other SWs such as combinations of transistors are also possible.

Next, in relation to the arrangement shown in FIG. 2, an example of an analog circuit system in which one set of photoelectric conversion element arrays is used is shown in FIG. 12 based on FIG.
This will be explained with reference to the figures.

That is, the analog shift register serial input control section 121 is composed of FETs 26 and 27 in FIG.
is placed at the beginning of the analog input, and then the photoelectric conversion section 1
One light receiving element block 13a consisting of 22 charge transfer section 123 and analog shift register section 124
and then 12, GNDed charge transfer section 1
23. One dummy block 13C consisting of an analog shift register section 124 is placed, and furthermore, a photoelectric conversion section 122 and a charge transfer section 12 are placed after it.
3. A second light receiving element block 13b consisting of an analog shift register section 124 is placed, and then an analog processing circuit as shown in FIG. 4 is connected.
The photoelectric conversion unit 122 includes the photoelectric conversion element 30 in FIG.
Since the anti-blooming gate 32 has a structure in which the electromotive charge changes depending on the amount of light and the electromotive voltage continues to rise, in order to obtain a signal in a certain range, the accumulation time is must be operated appropriately.

For this purpose, the analog shift register serial input control section 121 gives standards for the minimum and maximum signals to be obtained by the photoelectric conversion section 122, and inputs the signals to the analog shift register 124 of the photoelectric conversion section 122 through the same analog shift register 124. It is used as a comparison standard for excessive or insufficient signals. Here, the photoelectric transfer section corresponds to the shift gate, that is, FET 34 in FIG. 4, and the analog shift register section corresponds to that shown by 28 in FIG. In the arithmetic amplification, the sampled and held image signals generated at 128 points are amplified by resistors 126 and 127 as buffer amplifiers. Since the signal from the photoelectric converter 122 and the minimum and maximum reference signals mentioned above are transmitted in time series to its output, the sample hold is latched by the low state of the zero memory terminal 129. circuit 130
The output of 13 is used for maintaining the minimum reference level.
The output of the sample and hold circuit 132, which is latched by the low level of the full memory terminal indicated by 1, is used to hold the maximum reference level.

In order to bring the signal from the photoelectric conversion section 122 into the proper operating range of the circuit, a method is adopted in which the peak of the signal is suppressed to a certain value. This is done by holding the peak of the signal from the photoelectric conversion section 122 in a peak hold circuit 134 that holds the peak value of the signal during the period when the peak hold terminal 133 is high.

Reference numeral 135 is a reset terminal of the peak hold circuit, and the stored peak value is reset by setting the terminal to high.

Figure 13 is an example of a peak hold circuit configured with FETs, with peak hold terminal 133
At high, turn on FET-SW136 and input terminal 13
7 signal through FET 138 and resistor 139,
140 points as a source and follower.

When the potential at 140 points is higher than the past peak voltage held as the potential at 142 points by the capacitor 141, that is, when the current voltage is at its peak,
Diode 143 converts the voltage at 142 points into 1
Equal to the current voltage of 40 points.

The FET-SW 144 is reset to the high level of the reset terminal 135.
This is a reset SW that is turned on by the switch.By turning it on, the past peak held potentials of 142 points are set to zero.

The FET 145 constitutes a source follower together with the resistor 146, and transmits the voltage at 142 points, which is the peak voltage up to now, to the output terminal 147.

FIG. 14 shows the sample and hold circuit 130 shown in FIG. 12 for the aforementioned accumulation time control;
This is an example of the circuit configuration of a main sequence circuit that is a part of the third illustrated controller 22 described later for defining the accumulation time using a comparison standard given by the operations of the peak hold circuit 134 and the sample hold circuit 132.

That is, by applying the sample hold output shown at 130 for the comparison standard in FIG. 12 to the minimum reference level input terminal 148, and the sample hold output shown at 132 to the maximum reference level input terminal 149, 1 by 152
An upper limit comparison reference potential is generated at 53 points and a lower limit comparison reference potential is generated at 154 points. Then, the peak hold output indicated by 134 is sent to the peak input terminal 155.
give to

As a result, when the peak value of the signal exceeds the upper limit comparison potential, the comparator 156 selects the 157th point.
A HIGH signal is obtained at point 159 by the comparator 158 when the signal peak value is less than the lower limit comparison potential.

Then, after the signal is determined, the terminal 16
Give the accumulation time change clock to 0.

As a result, if the current accumulation time is too long and the peak value of the signal exceeds the upper limit comparison reference potential, the AND gate 1
The clock from terminal 160 is transmitted to point 162 through 61, and the clock from UP/DOWN counter 163 is transmitted.
By inputting a clock to the DOWN clock input terminal, the specified value of the accumulation time indicated by 164 is lowered by one, thereby lowering the accumulation time by one step in the main sequence circuit and shortening the accumulation time.

Also, if the current accumulation time is too short and the peak value of the signal is below the lower limit comparison reference potential, 1
With the HIGH signal at 59 points, the clock from terminal 160 is transmitted to point 166 through AND gate 165, the clock is transmitted to the UP clock input terminal of up/down counter 163, and the specified value of the accumulation time indicated by 164 is increased by one. As a result, the accumulation time is increased by one level, and the accumulation time is lengthened.

The signal voltage is adjusted by feedback that makes the accumulation time appropriate for the signal peak voltage as described above.

Note that when the power is turned on, the up/down counter 16 is set to forcibly specify the accumulation time to a predetermined value, and then perform the above control operation.
An initial value 167, which will be described later, is applied to the data input terminal 3, and a power-on signal 168, which will be described later, is applied to the preset terminal, thereby specifying the initial value when the power is turned on.

Each of the above signal processing and control is performed based on a series of predetermined sequences, but in order to explain this in detail, the main sequence circuit that is a part of the controller 22 that manages the sequence control will be explained below. 15, 16, and 15, respectively, the configuration of the circuit, the relationship between input and output in each circuit block, and the operational relationship of the analog circuit system shown in FIG. 4 under the control of the main sequence circuit.
It is shown in Figure 17.

All clocks are provided by main clock generator 170 based on the output of main oscillator 169. _The main clock generator 170 generates 10 types of non-overlapping clocks of φ ₀ .

FIG. 15 will be explained from the time when the power is turned on.

When the power is turned on, the main oscillator 169 and main clock generator 170 start operating. After power on, resistor 1
71 capacitor 172, 173 points are shown in Fig. 16a.
It detects when the power is turned on by generating a signal like this. The numbers on the horizontal axis in the bottom column of Figure 16 are the above-mentioned φ
₀ ......It corresponds to the time interval at which _φ9 is generated, that is, each cycle, and the dividing line narrowing each number is divided into 10 equal parts, and φ is generated at each timing.
₀ , φ ₁ . . . φ ₉ are generated. Therefore, in the sentence, the n-th cycle φi (i=0.1
………9) The time at which the pulse is generated is [n−φ
i].

In other words, due to the power supply turned on at the point before [0-φ ₇ ], the potential at point 173 gradually rises, and as _shown in FIG.
The inverting potential of inverter 74 is exceeded, and the output of inverter 174 becomes LOW. This situation is shown in FIG. 16b. That is, the inverter 174 becomes HIGH at the point [0-φ ₇ ] and becomes LOW at the point [2-φ ₇ ].

At the same time, 176
A LOW signal is generated at the point for at least the same period as shown in FIG. 16g. The RS flip-flop 178 (hereinafter all flip-flops are abbreviated as FF) receives the set input by the signals at the 177th and 176th points.
HIGH, the reset input receives the LOW state for at least a period before [0- _φ7 ], and the Q output 179 is output as shown in Figure 16c for at least the same period.
Set it to HIGH. The same period shown in Figure 16b
HIGH signal is synchronized through OR gate 180
It is given to the set input of RS-FF181, and the 16th
The LOW signal for the same period shown in figure a is the AND gate 18.
2 to the reset input of the FF 181. Since this RS-FF 181 is clock synchronized with _φ7 from the main clock generator 170, the set input from [0- _φ7 ] to [2- _φ7 ] before is HIGH and the reset input is LOW. , at the timing of [0- _φ7 ], the Q output 183 is set to HIGH, and the output 1 is
84 is set to LOW.

As a result, the system is said to be in the initial transfer mode. Output 18 at [1- _φ7 ]
The transfer controller 185 is released from its reset state by the transition from HIGH to LOW at 4, and since it is synchronized with the clock in %, it starts counting (1 to _φ0 ) sequentially as shown in FIG. 1023). At the same time, the accumulation time counter 186
It is reset when the Q output 183 of the output goes from LOW to HIGH.

Also, the output 184 of RS-FF181 is [0-φ
₇ ] After that, the Q output of D-FF187, which is clock synchronized with _φ3 , becomes [1-
_φ3 ] After that, it becomes LOW. The transfer controller 185
is clock synchronized with φ ₀ and receives signals of φ ₀ , φ _{1 ,} . . . , φ ₉ from the main clock generator 170, and performs counting and control as described below.

and the final point of counting (out of 1024 counts)
The look-ahead carry signal 188 (after the 1023rd count) is set to HIGH after the 1023rd cycle as shown in FIG. 16e. This signal and the previous HIGH
AND gate 18 for the 173-point signal that is
2, after 1023 cycles, S-R-FF1
Set the reset input of 81 to HIGH.

Since the reset signal 183 becomes HIGH after [0- _φ7 ], the accumulation time counter 186 remains reset, and therefore the carry signal 189 remains LOW as shown in FIG. 16h.
Also, since the signal at point 177 has become LOW by this point (1023 cycles), the output of OR gate 180 is LOW.

For this reason, the RS-FF 181 has a set input of LOW after [1023- _φ0 ] and a reset input of HIGH, so it is reset by the clock of _φ7 at [1023- _φ7 ], and the Q output 183 is LOW and the output 184 is HIGH. becomes HIGH.

This ends the initial transfer mode and Q output 18
3 becomes LOW, the accumulation time counter 186 starts counting at the timing of _φ0 . This is called the initial accumulation mode. At the same time, output 18
4 becomes HIGH, the controller 185 is reset, and as a result, the signal 188 becomes LOW at the timing of [1023- _φ7 ], and the D-FF 187 becomes HIGH.
Since the clock is synchronized with ₃ , [1023−φ
₇ ] After that, the output 184 of RS-FF181 is HIGH
In order to become [1024- _φ3 ], as shown in Figure 16 f
It becomes HIGH.

The accumulation time counter 186 is given N 2 ^N
A counter that performs frequency division (for example, Motorola's
MC-14536) is a counter that generates a clock divided by ^2N at the output when "N" is applied to the set input.In this example, when N is applied, the output of ^2N is called the ^2N carry. used.

HIGH of Q output after [1024- _φ3 ] of D-FF187 and 17 which became HIGH before that
3, through the AND gate 175,
Set the reset input 176 of the RS-FF 178 to HIGH. The RS-FF 178 is reset because the set input 177 was set to LOW before that, and the Q output 179 is reset at the timing of [1024- _φ3 ].
That is, the initial inhibition signal is set to LOW. The initial inhibition signal corresponds to 168 in FIG. [1024
−φ ₃ ] Previously, the Q output 179 of RS-FF178 was
Since it is HIGH, the initial setting value 191 is output to 192 via the data selector 190. The initial setting value 191 is indicated by 167 in FIG. [1024- _φ3 ] From then on, RS-FF17
Since the Q output 179 of 8 is LOW, the output of inverter 193 becomes HIGH, and a specified accumulation time value 194 (indicated by 164 in FIG. 14) is output to 192 via data selector 190.

Latch 195 is connected to signal 188, i.e. controller 185
Since the clock is synchronized with the look-ahead carry, the information at 196 points is undefined because the clock cycle is not performed before the 1023rd cycle, and after the 1023rd cycle, the information at the next 188 points is equal to the above initial setting value.
In FIG. 16, the 2050th cycle and subsequent cycles are equal to the specified value 194 of the accumulation time immediately before the 188th signal clock. As mentioned above,
[1023- _φ7 ] After that, the reset input is set to LOW and the accumulation time counter 186, which becomes capable of counting, inputs the initial set value latched by the latch 195 at 1023 cycles (up to 2050 cycles in FIG. 16) to its set input. If the set value is given, for example, 2, the count up to 2 ² , that is, ₄ , is counted as [1024-φ
₀ ] for 1, [1025-φ ₀ ] for 2, and so on.

In the example of FIG. 16, when the count reaches 4, that is, at [1027-φ0 _] , the look ahead carry of 189 is set to HIGH. Then, at [1027- _φ0 ], the look ahead carry of 189 becomes HIGH, and the RS-
Set the FF181 set input to HIGH.

At that time, as described above, the controller 185 controls the RS-
Since the output 184 of FF 181 has been reset since [1023- _φ7 ], the carry signal of 188 is LOW, that is, the AND gate 182 output is LOW, so the reset input of RS-FF 181 is
It becomes LOW.

Therefore, since the RS-FF181 has a clock cycle of _φ7 , it is set at [1027- _φ7 ], and the Q output 183 is set to HIGH and the output 184 is set to LOW.
Make it.

After the above process, the initial accumulation mode ends.

[ _1027φ7 ] and the output of RS-FF181 is 18
4 becomes LOW, the transfer controller 185 performs counting and receives the _φ0 clock, and as shown in Fig. 16h, 1 in 1028 cycles, 2 in 1029 cycles...
and count. This mode is called transfer mode. At the same time, the Q output 183 of RS-FF181
Since it is HIGH, the accumulation time counter 186 is reset, and the D-FF 187 receives the LOW of the output 184 of the RS-FF 181 at the clock of _φ3 , and becomes LOW at [1028- _φ3 ]. During the transfer mode, the transfer controller 185 continues to count, as described above.
At the time of 1023 counts, that is, 2050 cycles, 188 carry signals are output. Then, upon receiving the HIGH signal of the 2050th cycle of the carry signal of 188, the RS-FF181 is reset at [2050- _φ7 ] to end the transfer mode as described above, and then moves to the accumulation mode. It continues to alternate with the transfer mode in the same way as the storage mode. The difference from last time is RS
- Since the FF 178 has already been reset, its Q output 179 provides the specified value for the accumulation time. That is, before the transfer controller 185 counts 1023 cycles to which the latch 195 is clock-synchronized (before 2050 cycles in FIG. 16), the signal from the accumulation time control circuit of FIG.
The next count value of the accumulation time counter 186, that is, the accumulation mode time is determined based on this information.

In this way, the storage mode repeats the transfer mode and the storage mode while varying the time depending on the value determined immediately before the end of the transfer mode.

Note that during the above sequence, the AND gate 197
Therefore, the Q output 184 of RS-FF181 and D-
Both outputs 198 of FF187 are HIGH, that is, RS
-Q output 183 of FF181 and Q of D-FF187
When both outputs are LOW, that is, at the beginning of the accumulation mode ([1023- _φ7 ]-[1024-φ in Figure 16)
₃ ] 1 at [2050- _φ7 ] ~ [2051- _φ3 ]
99 iCG-PS signals are generated as shown in FIG. 16i.

Next, each pulse timing and signal when the analog circuit of FIG. 4 is adapted to the modified example of FIG. 12 will be explained based on the timing chart of FIG. 17.

Since these sequences are controlled by the transfer controller 185 in FIG. 15, they will be explained together with the counting of the counter. This transfer controller 185
is the main clock generator 170 as shown in FIG.
It receives φ ₀ , φ ₁ ... φ ₉ from φ 0 and performs counting in response to the φ ₀ clock, and also outputs the state at the output terminal when a specific pulse φ occurs in a specific cycle. It is something.

The transfer pulse _φ1 at 37 in FIG. 12 is set to HIGH at the timing of _φ2 and to LOW at the timing of _φ3 regardless of the count. This situation is shown in Figure 17a.
Shown below. Similarly, 38 transfer pulses φ ₂ are shown in Fig. 17b.
As shown in , regardless of the count, at the timing of φ ₃
HIGH, LOW at the timing of _φ4 , and the analog signal shown at 28 in FIG. 4 and 124 in FIG.
The shift register (256 bits in the following explanation) is shifted to the right in the diagram.

Immediately after starting the transfer mode [1-φ ₁ ] to [1-φ
₃ ], the shift pulse from the shift gate 35 is set to HIGH, and the signal generated by the photoelectric conversion unit shown at 122 in FIG. 12 is inputted in parallel to the analog shift register 124. The shift pulse at this time is shown in FIG. 17c. As a result, the analog shift register 124 sequentially transfers the outputs of the photoelectric conversion elements shown at 30 in FIG. 4 to the right side of the figure by switching or adding the serial and parallel inputs.

Then, the final serial output of this analog shift register 124 is sequentially sent to the photoelectric output control section 12.
φ ₁ , φ ₂ in time series from the photoelectric conversion element on the right side of the figure
I will tell you at the right time.

The photoelectric output control section 14 receives this signal and obtains the reset clock from 44 at the timing of _φ1 as a signal as shown in FIG. 17d in order to _clear the past signal. Until φ ₀ of the next cycle, an output proportional to the amount of light received by each photoelectric conversion element as shown in FIG. 17e is obtained at the input terminal of the sample and hold circuit 47. The above output is given to the sample hold circuit 47 and is connected to the control terminal 48 with φ
₄ (FIG. 17f), the output terminal 128 of the photoelectric output control unit 14 in FIG. 12 is applied from φ ₄ of each cycle to φ ₄ of the next cycle.
output a signal shaped as shown in Figure 17g.

As described above, the photoelectric outputs from 1 to 256 counting from the right end of the analog shift register in FIGS. 4 and 12 start transfer from [1-φ ₄ ] to [256-φ ₄ ].
is output between each cycle, and similarly, 513 to 768
The photoelectric information located at [513- _φ4 ] ~ [768-
φ ₄ ] between each cycle. In response to this, it is applied to the input of the sample hold circuit 50 in the image signal change detection section 16 shown in FIG.
9, a clock as shown in Fig. 17h that goes HIGH every φ ₀ of each cycle from [2-φ ₀ ] after the start of transfer is applied, and a photoelectric output of 1 to 256 is generated [2-φ ₀ ].
〜[257−φ ₀ ], between each cycle 513〜
768 photoelectric output from [514-φ ₀ ] to [769-φ ₀ ]
51 in Fig. 4 as in 17i.
Output to the point. Due to this, the differential amplifier 52
Inputs φ ₄ to φ of each cycle as shown in Fig. 7j.
₉ , the nth signal and the n-1th signal (n
is an arbitrary natural number). Then, a clock that goes HIGH at the timing of _φ6 of each cycle from 2 to 256 and from 514 to 768 is connected to the control terminal 53 as shown in Fig. 17k.
The 17th
As shown in FIG. 1, the signal of the illuminance change of each photoelectric conversion element is obtained as the output of the differential amplifier 52. Then, through the emphasis circuit 17 in FIG.
₃ ] ~ [257-φ ₂ ] [514-φ ₃ ] ~ [769-φ
The first slope signal as shown in FIG. 17m, which becomes HIGH during ₂ ], is added to the terminal 79 in FIG.
A multiple integration circuit 19 performs integration. The output of the operational amplifier 76, which is the result of the integration, is shown in FIG. 17n. Note that the reset signal applied to the terminal 80 of this double integration circuit 19 is set to 2 after the start of transfer as shown in FIG.
The integrator is reset during less than 511 cycles, less than 514 cycles, and 1023 cycles or more so that it becomes HIGH.

As described above, the photoelectric output generator 1 in FIG.
Based on the position of the illuminance signal of 3b, the analog shift register 124 converts the illuminance signal into a time series signal, absoluteizes and emphasizes the illuminance change, that is, the illuminance change depending on the location, and resets it in less than two cycles after the start of transfer. Depending on the integrator [2- _φ3 ] ~ [257- _φ2 ]
Integrate between. Photoelectric output generator 1 in Figure 12
The output of 3a is integrated 512 cycles later. As shown in Figure 17o, the analog integrated value obtained as a result, that is, the emphasized addition value of the illuminance change of each element, that is, the signal representing the degree of sharpness, is transferred to [257- _φ5 ]～[510− _φ9 ]
A second slope signal that becomes HIGH between [769~ _φ5 ]~[1022− _φ9 ] is applied to the terminal 82 or 86 in FIG. 4 to perform linear or exponential inverse integration,
As mentioned at the time of A/D conversion, after the second slope of FIG. is converted into a linear or log-transformed time until it becomes LOW as shown in Figure 17q.

Signal processing can be performed by generating the above clocks and signals while the transfer controller 185 shown in FIG. 15 is performing counting.

Next, by evaluating the integral value of the two light receiving elements arranged before and after the planned focal plane, that is, the photoelectric conversion elements that constitute the two photoelectric output generating units, the planned focal plane and the actual focal plane can be determined. A display control unit that displays the deviation, that is, the degree of focus, will be explained with reference to FIG. 18.

As mentioned above, dual slope A/D conversion is
Since the integrated value is A/D converted during the time from the start of the inverse integration until the integrator output falls below the reference potential, the AND gate 200 is used to convert the integrated value from the transfer controller 185 to 1st of
Input the second slope signal 201 as shown in Figure 7o.
, the output from the integrator output comparator 91 in FIG. do.

In the following, it is assumed that log conversion is performed by dual slope A/D conversion. 205 is a binary up counter that calculates the sum, or product, of the integral value, that is, the log of the visibility signal, from the two photoelectric output units; 206
By applying the output of the RS-FF 181 shown in FIG. 15 to the terminal of , a reset signal is applied, and the reset is performed in a mode other than the transfer mode. 207 is an UP-DOWN counter, which calculates the integral value from the two photoelectric output generators,
That is, it calculates the log difference, that is, the ratio, of the sharpness signals.It is reset by the above-mentioned terminal signal 206, and a HIGH signal is input to the terminal 208 while the count of the transfer controller 185 is less than 514 cycles. When the signal is applied, the signal is counted up, and when the signal is applied to the LOW signal for 514 cycles or more, the signal is counted down, and the log difference between the two integral values is calculated. These counters 205 and 207 perform counting by receiving the aforementioned clock from 204 points. The clock to the input 203 of the aforementioned AND gate 200 is selected so that neither of these counters 205, 207 overflows or underflows, or brightness control is automatically applied in the event of an overflow or underflow. If this does not occur, there will be a sharpness product signal at the output 209 of the counter 205, for example as a 4-bit signal, and a sharpness ratio signal at the output 210 of the counter 207. In this case, it is a 4-bit signal, of which 1 bit indicates a sign. If the product signal of the sharpness of 209 is below a certain value, it means that the focus judgment ability of this system is below or the case is extremely defocused, so the magnitude comparator 211
If the value is lower than the minimum setting value of 212, the output signal of 213 is set to LOW and the output of the system is prohibited. The sharpness ratio signal 210 represents the degree of out-of-focus when the subject's illuminance, contrast, etc. are normalized, so the most significant bit 214 indicates that the positive value is LOW, and Since a negative signal is expressed as HIGH, when the signal is negative, the exclusive signal 215 complements the ratio signal and converts it into an absolute value, which is then added to the magnitude comparator 216. Magnitude comparator 216 is 21
When the difference is within a predetermined deviation range before and after the correct in-focus point by comparison with the set value of 7, the absolute value of the ratio signal output of 210 is smaller than the number of 217, so HIGH is output to 218.

The positive and negative signals with a ratio of 214, ie, the front and rear pin signals, are inverted by an inverter 219 and output to 220 points. With this, for example, when the front pin is on 214,
A HIGH signal is obtained. These pre-pin signals,
If within the capabilities of this system, the above three signals are obtained separately through three AND gates 221, each of which receives the output signal of the above-mentioned 213 as one input, for the focusing signal and the rear focus signal. By adding these three signals to the reset signal 184 in FIG. 15 to the terminal 222, D
- It is latched by the latch 223 and three signals are output to 224, which are displayed inside or outside the viewfinder of the camera using three resistors 255 and three LEDs 226 to indicate the degree of focus, which is useful for focusing operations. The LED 226 corresponds to 21 in FIG.

Incidentally, it is also possible to easily construct a servo focus system using this signal.

Here, as a separate embodiment of the display or instruction method, an example of sound using a sounding body is shown in FIG. 19.

The 210 normalized comparison signals in FIG.
In addition to 227, by applying the same clock as the terminal 222 to the terminal 228, the D-latch 229 outputs the comparison signal 227 determined at the rising edge of the clock.
Further, the signal 213 in FIG. 18 applied to the terminal 230 is latched by the D-latch 231.

The sound is generated by the resistor 235 between the inverters 232, 233, 234, and the resistor 24 between the first oscillator and the inverter 237, 238, 239 due to the capacitor 236.
According to the result of the RS-FF 242, a select gate consisting of AND gates 243, 244 and an OR gate 245 selects oscillator outputs of two different frequencies from the second oscillator produced by the capacitor 241.

The result is transmitted to the tri-state buffer gate 247 and the tri-state inverter 2, which inhibits the output by making the latched signal of 246 low due to the signal from 230.
48, and in addition to the sounding body 249 (for example, a piezoelectric sounding body), the degree of focus is indicated by changing the duty of two kinds of sounds having different frequencies.

To control the duty, the UP counter 250 and the counter 251 (T/FF) are kept counting up by the clock from the terminal 252, and the counted value 253 is compared with the latched comparison signal 254 by the magnitude comparator 255. ,
When a match is made, the 256 outputs a HIGH signal.
Set RS-FF242. and,
By applying the signal of 257 to the B input of the monostable multivibrator 258 when the counter 251 (sign bit counter) rises, that is, changes from positive to negative, a high pulse of a constant width is generated at the Q output of 259 at that time. and resets the RS-FF242.

That is, when expressed in octal, the counters 250 and 251 go from 00 to 07, then to 10, and then to 17.
Count in a loop from to 00. Therefore, as described above, by resetting the RS-FF 242 when the count value changes from 07 to 10, and setting it when the count value matches the comparison signal, it will be In the case of 06, which is very blurred on one side, the duty ratio can be changed to 14:2, in the case of focused point 00, it can be changed to 8:8, and in the case of 17 (-1), which is slightly blurred on the other side, the duty can be changed to 7:9.

The basic signal processing method for detecting a focus position and the control manner of various sequences associated therewith have been described in detail above, and a method for further enhancing the capability of detecting a focus position will be described below. It has been described that image sensors such as CCDs can store image signals for any length of time, and that the storage time can be controlled depending on the brightness of the object. However, if the object has extremely low brightness, the accumulation time will be longer.
While the charge is being accumulated, the image may be distorted due to camera shake, etc., and there is a risk that the actual focus position detection ability will be reduced. In consideration of this point, the present invention aims to operate the system in a relatively short accumulation time by adding and using the outputs of a plurality of photoelectric conversion elements, thereby eliminating the adverse effects caused by the above-mentioned blurring, etc. . In this case, the size of the photoelectric conversion element appears to be rougher, resulting in a slight decrease in resolution, but overall it is possible to make the focus detection ability emit light even for low-luminance objects. This is the result.

Specifically, by converting a part of the control block from the transfer controller 185, the signals from the photoelectric conversion elements are added every few, even under the same illuminance and the same accumulation time. Even if the obtained signal level is increased and the degree of sharpness detection is slightly lowered, signal processing becomes easier.

In this way, for example, the effects of camera shake can be eliminated by adding up the photoelectric output every n times (n is a natural number of 1 or more) due to the faster accumulation time.

For this purpose, the signal applied to 44 in FIG. 12 or 4 is transferred to
It is good if it is given at timing ₁ . As a result, the signal in FIG. 17e is similarly established between _φ3 of the n-cycle step starting from cycle n and _φ1 of the next cycle.

Next, the signal 48 in FIGS. 4 and 12, ie, the signal shown in FIG. 17f, may be similarly applied at the timing _φ4 of the n cycle step starting from the n cycle. As a result, 28 in Figures 4 and 12
The signal of n, that is, the signal shown in FIG.
From _φ4 of n cycle steps starting from cycle to the next _φ3 .

Next, the signal shown in FIG. 17b, which is applied to 49 in FIG. 4, is applied at the timing of φ ₀ of the n cycle step starting from the n+1 cycle.

Next, the signal shown in FIG. 17k, which is given at 53 in FIG. 4, is given at the timing _φ6 of the n cycle step starting from the same n or 2n cycle. As a result, the differential output of the differential amplifier 52 of FIG. 4, that is, the effective part of the signal shown in FIG. 17, can be obtained at the timing _φ6 of the n cycle step starting from the 2n cycle.

Incidentally, when the differential type is used as shown in FIG. 11, the effective part is output when the signal g in FIG. 17 changes, that is, at the timing _φ3 of the n cycle step starting from the 2n cycle. Therefore, the first slope signal in FIG. 17m, that is, the visual field signal, is [2n−φ ₃ ]
It must be between [257- _φ2 ].

If you do the above, the photoelectric output will be added every n times, and although there will be a slight decrease in resolution, it will enable processing under a shorter accumulation time, especially for dark subjects, and will eliminate camera shake. The influence of accumulation time can be reduced.

Next, the reference signal used for switching the accumulation time will be explained. This is introduced by terminal 29 in FIG. 4 for 50 to 100 cycles after the transfer controller 185 starts the transfer. That is, [50-φ ₀ ] [99-φ ₉ ]
Until then, by setting terminal 24 in Figure 4 to HIGH and terminal 25 in Figure 4 to LOW, applying a terminal voltage approximately equal to that of terminal 23 in Figure 4 to analog shift register 28, the maximum A value standard is obtained. That is, since this signal is output with a delay of 768 cycles (256 x 3) by the analog shift register 28, it is output at the 39 points in Figure 4 at the timing of [818-φ ₃ ][868-φ ₂ ]. Ru. Therefore, the 12th
In the figure, addition is latched to terminal 129 in response to the voltage at which terminal 29 in FIG. 4 is LOW. A clock that goes HIGH at the 800th cycle, and the above-mentioned terminal 2 is connected to terminal 131 in Figure 12.
A clock that becomes HIGH at the 850th cycle in which addition is latched corresponding to the voltage at which 9 is HIGH is applied to latch the maximum and minimum reference voltages, respectively. Similarly, the terminal 135 in FIG. 12 is reset to HIGH in synchronization with the clock in the first cycle of the start of transfer.
The terminal 133 in FIG. 12 receives the lower 9 bits [n- _φ4 ] to [256- _φ9 ] of the transfer controller 185 corresponding to the additively shaped signals of each photoelectric conversion element.
All you have to do is give a HIGH signal until then.

FIG. 20 shows an example of an addition number switching type accumulation time control circuit for obtaining a signal in a shorter accumulation time by adding photoelectric conversion elements in this manner.

It is basically the same as the one in FIG.
If the signal peak voltage is too low, refer to 15 in Figure 14.
In response to the signal at point 9, the terminal 260 becomes HIGH, and as a result, a clock is outputted to the terminal 262 through the AND gate 261, which is synchronized with the clock at, for example, the 1022nd cycle, to the 263rd point in order to increase the accumulation time.

If the signal peak is too high, the terminal 264 becomes HIGH in response to the signal 157 in FIG. 14, and as a result, a clock is outputted through the AND gate 265 to similarly reduce the accumulation time to 266 points. Accumulation time is UP/DOWN counter 267
The counted value of 268 is determined as the specified value of the accumulation time shown at 164 in FIG. , 167 in Fig.
The initial setting value shown in is preset as the initial value.

Inverter 271 is UP/DOWN counter 26
7 over. The AND gate 272 is closed by inverting the HIGH signal of the Luck Abed Carry immediately before the flow, and the overflow occurs. Prevent flows.

Similarly, the inverter 273 detects the under value of the UP/DOWN counter 267. Lutsk bet just before the flow. AND by inverting the borrow HIGH signal.
Gate 274 is closed to prevent underflow.

As shown in FIG. 21, this operation works in such a way that the number of elements to be added changes at a certain set value T, and the accumulation time changes sequentially at other times.

That is, in order to detect this bending point, the above set value T
(shown as 275 in FIG. 20) and the prescribed value of the accumulation time of 268 in magnitude. Comparator 2
76.

For example, in Figure 21, if the current accumulation time is greater than or equal to T,
That is, if the current signal level is too low or still dark during a long accumulation time, the output of the OR gate 277 will be of magnitude. By comparator 276
In response to this, the AND gate 278 passes the signal 263, ie, the accumulation time increase request signal, to set the RS-FF 279 to a mode in which addition is performed for every two elements.

If it is still dark after adding every two elements, the output of the OR gate 280 is HIGH, so the AND gate 272 is turned on and the counter 267 is counted in order to lengthen the accumulation time. Make it hot.

Similarly, if the current accumulation time is less than this T, that is, if the current signal is too bright with a short accumulation time, the output of the OR gate 281 becomes HIGH, and the AND gate 282 decreases the accumulation time of the above 266. Through the request signal, RS-FF279
If it is still too bright even in that state, the output of the OR gate 283 is HIGH, so the AND gate 274 is turned on and the counter 267 is counted down in order to further shorten the accumulation time.

Conversely, if the current accumulation time is less than T, that is, if the accumulation time is short and the current signal is too small, the output of the OR gate 280 will be
Since it is HIGH, the counter 267 is counted through the AND gate 272. Make it hot. Also, when the current accumulation time exceeds T, that is, when the current signal is excessive due to the long accumulation time, the output of the OR gate 283 is
Since it is HIGH, the counter 267 is counted through the AND gate 274. Bring it down.

In this way, in addition to adding the outputs of any number of photoelectric conversion elements, stable system operation is possible in a wider luminance range, and the detection accuracy can be used without deterioration as much as possible.

In addition, in Figure 20, this addition switch is set to UP/
This is done by controlling the DOWN counter, but conversely, the result of addition and the result of the UP/DOWN counter may be calculated by an adder, and the accumulation time may be controlled by the output, or the accumulation time may be controlled by two elements. It can also be extended to addition for each of the above elements, and the user's choice or lens performance (for example, a lens with poor resolution does not improve performance even if the number of addition elements is increased) There is no change, and telephoto lenses are generally prone to camera shake, so it is possible to automatically control it by increasing the number of addition elements and shortening the accumulation time. This selection is effective when reducing the effects of camera shake, etc., and when switching when there is no limit to the storage time due to a tripod or the like.

Now, as mentioned above, since the light receiving element receives light from a part of the field of view at two locations far from the focusing position, the two light receiving elements do not necessarily form images of the exact same subject with different sharpness. Not necessarily.

This is especially true when there is a string-contrast object image near the outside of the boundary of one light-receiving element, and the image is blurred and formed on the other light-receiving element, resulting in information overload. Become.

In order to reduce such so-called boundary distortion, the present invention introduces a "window function" to view less information near the boundary than information in the center. That is, the lower 9 bits of the transfer controller 185 shown in FIG. 15 detect the position (2 to 256 cycles) where information of each photoelectric conversion element can be obtained as shown in FIG. 17, and the input terminal shown in FIG. The window function is created by controlling the 61 digital values.

An example is shown in FIG.

The lower 9 bit information of the total 10 bit count output of the transfer controller 185 is given to the input 284,
Magnitude. A comparator 285 compares it with the value of the in-field address signal 286 for starting to open the window. And before that starting point at 287 points
Gets HIGH signal, which causes OR gate 288
The output of the UP/DOWN counter 2 for the window function is set HIGH to disable counting, and the reset signal shown in FIG.
Keep 90 at zero.

Initially, the number of transfer cycles in 284 is smaller than the in-field address signal shown in 291 for starting to close the window, so the magnitude. This is the output of comparator 292. UP/ by 293 point signal HIGH
The DOWN counter 290 is set to UP count mode.

Next, the number of transfer cycles given to 284 is 2.
When the setting value of 86 is exceeded and the window starts to open,
287 which is the output of UP/DOWN counter 285
UP/DOWN when the signal at the point becomes LOW
While the lookup carry indicated by 294 from counter 290 is LOW, i.e., counter 2
OR gate 28 until 90 overflows
Set the output of 8 to LOW to allow counting, and terminal 295
The counter 290 is counted as the data is transferred by the transfer clock given to . Let's get it up. Then, the counted value is applied from the terminal 296 as a window control command to the terminal 61 shown in FIG. 4, and the reference level for emphasis and suppression is changed to control the window function. Then 290 looks overflow to 294 with the previous maximum value. It outputs an Abetsu carry signal and stops its own counting by OR gate 288. Then 28
If the number of transfer cycles given to 4 exceeds the set value of 291, the magnitude. Comparator 2
92 makes the signal of 293 LOW and outputs UP/
Switch the DOWN counter 290 to the DOWN count mode, and count until 294 look-ahead carries appear, that is, until underflow occurs. When the count of the counter 290 reaches zero, the count is stopped by the carry signal of the counter 294.

In this way, a window function is generated and controlled to reduce the weight of information near harmful boundaries and suppress boundary distortion.

Note that this embodiment is based on the above-mentioned analog. A shift register was used to perform parallel-to-serial conversion of each photoelectric conversion element and convert the position of the same element into a time-series signal, but the purpose of this example was to simplify the signal circuit using time-series signals. Analog. shift. Analog without using registers. The same thing can be achieved even if the multiplexer is operated with the count value of the transfer controller 185 and the data is converted into a time series.

Next, an embodiment of the internal configuration of the aforementioned transfer controller 185 will be described in detail with reference to the drawings.

FIG. 23 is a diagram of the counter section, which has 10 stages reset at 297 by the signal 184 in FIG. binary. The counters 298-307 count the clocks at 308.

This count is performed at the falling point when a _φ9 pulse is applied to the clock 308, and at the rising point when _φ0 is applied, at the timing of _φ0 .

These counters 298 to 307 output their count values to 309 to 318 as binary signals (hereinafter referred to as bits 1 to 10). Second
4 to 28 are examples of logic circuits for providing each output, and will be explained in sequence.

analog. shift. 12th for register
Φ ₁ of 37 in the figure outputs the Φ ₂ pulse to 320 points through the buffer gate 319.

analog. shift. 12th for register
_Φ2 of 38 in the figure buffers the _Φ3 pulse. It is output to 322 points through a gate 321.

peak. 135 in Figure 12 for hold
The reset signal is sent only to the first cycle of the 1024 cycles of the counter by the AND gate 323.
Obtain a HIGH signal at 324 points and give that signal.

The shift gate signal shown in FIG. 12, 35, for photocharge transfer is converted to 326 points by an AND gate 325.
Between φ ₁ and φ ₂ in the first cycle of 1024 cycles
Get a signal that goes HIGH and give that signal.

44 in Fig. 4 for adding an arbitrary number of photoelectric outputs.
The reset signal of 32 is output by AND gate 327.
Obtain a signal that goes HIGH during odd cycles when adding two elements to 8 points, and obtain a signal that goes HIGH every cycle when adding two elements to 330 points or every cycle when adding one element using the OR gate 329. An AND gate 331 obtains a clock that goes HIGH at _φ1 of the n-cycle step starting from the 1st cycle at the 332nd point, and provides that signal. A two-element addition instruction is given from 333. This is shown in Figure 20.
This is the Q output of RS-FF279. The same shall apply below.

The signal 48 in FIG. 12 for additive shaping is
The AND gate 334 obtains a signal that becomes HIGH during even cycles when adding two elements to 335 points,
OR gate 336 is used to add 337 points to odd number cycles when adding two elements or each cycle when adding one element.
A signal that becomes HIGH is obtained, and a clock that becomes HIGH at point 339 from n cycle to n cycle step at time _φ4 is obtained and that signal is applied to point 339.

The signal 53 in Fig. 4 for detecting changes in illuminance is
The AND gate 340 obtains a signal that becomes HIGH at point 341 from the signals at the 337 points mentioned above at time _φ6 of the n cycle step from the n cycle, and applies that signal.

The signal 49 in FIG. 4, which is also used to detect changes in illuminance, is processed by the AND gate 342 in FIG.
HIGH in odd cycle when adding 2 elements to 343 points
34 is obtained by the OR gate 344.
Obtain a signal that becomes HIGH at each odd cycle when adding 2 elements to 5 points or every cycle when adding 1 element, and receive the signal 342 in Figure 24 at its 1 input terminal.
The AND gate 346 causes the 347th point to go HIGH at _φ0 from the n+1 cycle to the n cycle step.
Get the clock and give that signal.

The signal 79 in FIG.
A signal that becomes HIGH only in the second cycle of each 512 cycles is obtained at 9 points, and 35
Obtain a signal that becomes HIGH in the second cycle of each 512 cycles when adding elements to one point.

Also, by AND gate 352, each 512 points becomes 353 points.
A signal that becomes HIGH until the 4th cycle of the cycle is obtained, and becomes HIGH in the 4th cycle of each 512 cycles when two elements are added to 355 points by AND gate 354.
35 is obtained by the OR gate 356.
At the 2nth cycle of each 512 cycles at 7 points
A signal that becomes HIGH is obtained, and the AND gate 358 sets the RS-FF 359 at the timing of _φ3 of the 2nth cycle of each 512 cycles. similarly
A signal that becomes HIGH only at the 257th cycle of each 512 cycles is obtained at the 361st point by the AND gate 360,
AND gate 362 converts 359 FFs into 512
It is reset at the timing of [257- _φ3 ] of the cycle. As a result, a signal that becomes HIGH from [2n-φ ₃ ] to [257-φ ₃ ] of each 512 cycles is obtained at point 363, and this signal is applied to the terminal 79 in FIG.

The reset signal 80 in FIG. 4 for resetting the integral is used by the AND gate 364 in FIG.
Reset FF366. The same RS-FF366 has 2 out of 512 cycles at each of the 349 points in Figure 25 mentioned above.
Since it is set by the signal of the cycle, 36
A signal is obtained and applied to point 7 which is LOW from 2 cycles to 511 cycles in each 512 cycles, that is, from 511 cycles to 514 cycles and from 1023 cycles to the next 2 cycles.

For example, the second slope signal indicated by 201 in FIG. 18 for inverse integration is
During the 512th cycle, the RS-FF368 is reset by the signal that becomes HIGH at the 511st cycle, and the second
257 cycles out of 512 cycles for each of the 361 points in Figure 5
Pass the signal that becomes HIGH through AND gate 369,
370 points in each 512 cycles [257- _φ5 ]
Obtain a signal that becomes HIGH and set RS-FF368 to obtain a signal that becomes HIGH from [257- _φ5 ] to [511- _φ0 ] during each 512 cycles at 369 points, and give that signal. .

The signal shown at 208 in FIG. 18 for determining the first image and second image for focusing calculation is the signal 297 in FIG. 23.
The reset signal of RS-FF371 is applied to the set input of RS-FF371 to set it at the start of counting, and the AND gate 37
2, a signal that becomes HIGH at the 514th cycle out of 1024 cycles is obtained at the 373rd point, the RS-FF 371 is reset, a signal that becomes HIGH until the 514th cycle is obtained at the 374th point, and that signal is applied.

The signal 129 in Figure 12 is the AND signal in Figure 27.
Due to gate 375, 376 points during 1024 cycles
Obtain a signal that goes HIGH at the 800th cycle, and RS−
Set FF377. And this RS-FF3
77 is reset by the signal shown at 341 in FIG. 24 mentioned above. Therefore, a HIGH signal is obtained from the 800th cycle at the 378th point until the signal 341 is output, that is, at least until [800-φ ₆ ]. And by AND gate 379, 38
At least [800-φ ₀ ] to [800-φ ₆ ] to 0 point
For example, the signal indicated by 339 between [800−φ
₄ ) Obtain a signal that becomes HIGH and give that signal.

The signal shown at 131 in FIG.
Obtain a signal that becomes HIGH in the cycle, and RS−FF
Set 383. And this RS-FF383
is reset by the signal indicated by 341 mentioned above. Therefore, a signal that becomes HIGH from the 850th cycle until the signal 341 is output at the 384th point, that is, at least until [850-φ ₆ ] is obtained.
Then, by the AND gate 385, at least 3 points between [850-φ ₀ ] and [850-φ ₆ ] are added to the 386 points.
The signal indicated by 39, for example, HIGH at [850- _φ4 ]
Obtain the signal that becomes and give that signal.

The signal shown as 133 in FIG. 12 for 134 (peak hold) in FIG.
Obtain a signal that becomes HIGH, and use the AND gate 389 to add [1-φ
₄ ] Give a signal that becomes HIGH at the
A signal that becomes HIGH in the second cycle of each 512 cycles of 349 points in Figure 5 is passed through an AND gate 391 to obtain a signal that becomes HIGH in [2- _φ4 ] of each 512 cycles when adding two elements to 392 points. , OR gate 393 sets RS-FF 394 at [n-φ ₄ ] during each 512 cycles. Also, 3 in Figure 25
At the 257th cycle of each 512 cycles with 61 points
By applying a HIGH signal to the reset input, 395 points are set during each 512 cycles [n- _φ4 ] to
Obtain a signal that becomes HIGH until [257-φ ₀ ] and apply that signal.

analog. shift. The AND gate 396 shown in FIG. 28 is connected to the terminal shown in FIG. 4 24 and the terminal shown in FIG. 4 25 for serial input control of the register.
HIGH at the 50th cycle at the point shown in 397.
Obtain the signal and set the RS-FF398.
Also, a signal that becomes HIGH at the 100th cycle is obtained at the 400 point by the AND gate 399, and the RS-FF39
In order to reset 8, a signal that goes HIGH from 50 to 100 cycles is obtained at point 401, and 24 in Figure 4 is obtained.
Except for 50 to 100 cycles at 402 points given to the terminal of
Obtain a HIGH signal and apply it to terminal 25 in Figure 4.

The accumulation time change command shown at 160 in FIG. 14 for accumulation time control obtains and applies a signal that becomes HIGH at the 1022nd cycle to the 404th point by the AND gate 403.

Look at 188 in FIG. 15 for the main sequence. Abets. The carry signal is sent to the 406th point by the AND gate 405 at the 1023rd cycle.
Get a signal that goes HIGH and give that signal.

Next, the importance of accumulation time control in this embodiment will be explained with respect to image storage in general, without being limited to the focus detection device.

Figure 29 shows a general image pickup tube.
The operation of this image pickup tube is based on the photoelectric conversion plate 40 inside the tube 407.
8 converts the brightness information of the image into an electric signal, and outputs it to the outside according to the amount of current of the electron beam 410 emitted from the cathode 409.

The beam 410 is focused by a control grid 411 and deflected by a magnetic field by a deflection coil 412 or an electric field by a deflection plate, and is applied to an arbitrary location on the photoelectric conversion plate to output the brightness at that location.

That is, the signal is transmitted to the photoelectric converter 4 as shown in FIG.
13. The signal is output through the scanning or selection section 414 and the output section 415, but the temperature and illuminance characteristics of the signal mainly depend on the photoelectric conversion section 413. In particular, the scanning section 414 is sensitive to temperature changes due to its implicit heater. In addition, since the plate potential is high, it can be said that there is almost no influence from illumination, etc., such as direct photoelectron injection into the tube 407.

In addition, the dynamic resin of the signal is also the photoelectric conversion plate 4.
Since the characteristics of the photoelectric conversion plate 408 are known, it can be said that the characteristics of the photoelectric conversion plate 408 are known and are affected almost only by the temperature. Therefore, the number of phases is easy.

Furthermore, for the same reason as above, it is easy to detect the presence or absence of clipping of a signal by observing the peak potential of the signal and to control the signal to an appropriate level. However, as in the embodiment of the present invention, it is a semiconductor analog. shift. In the case of a device having a scanning section using a register or a CCD, the illuminance and temperature changes of the scanning section are large, and the dynamic range is narrow.

For this reason, in the embodiment of the present invention, a reference potential is added to the serial input of the same scanning and transfer section in a time-division manner, and the serial output and the signal passed through the output section are used as a reference signal for the image information signal. Performs potential control.

For this purpose, in the embodiment of the present invention, a lower limit signal and an upper limit signal as a reference signal are provided according to the illuminance characteristics, temperature characteristics, etc. of the transfer section, or according to changes in the characteristics of the output section, such as control of the output section such as two-element addition. is obtained, and the image signal is controlled.

In the embodiment of the present invention, the temperature characteristics of the photoelectric conversion element are not canceled because the temperature change in the transfer section is large and the dynamic range is narrow, and the cancellation of the temperature characteristics of the photoelectric conversion element is not performed because the temperature change in the transfer section is large and the dynamic range is narrow. In the main processing, it is omitted because it is naturally canceled out, but when used for imaging purposes, the difference from the lower limit reference potential of the above-mentioned dynamic range is output, and the temperature characteristic of the photoelectric conversion element is also It is necessary to use countervailing means.

In addition, the addition of elements corresponds to the sensitization phenomenon in general photography, and is also practical for imaging that allows the expansion of information pixels, and is particularly useful because it allows a high output signal to be obtained under the same accumulation time. If the screen interval time (for example, 1/30Sec) is fixed, such as on TV,
It is very effective, and in particular, the imaging brightness range can be greatly expanded (particularly to the dark side). In that case, by controlling the clock and readout reset of the X-Y direction shift register, a signal four times as large can be easily obtained by adding, for example, 2.times.2 (pixel.times.scanning line).

Next, we will discuss the parallel type reference signal output method in Chapter 31.
This will be explained with reference to the figures.

416 converts image brightness information into an electric signal using a photoelectric conversion element as described above, and converts the image brightness information into an electric signal. shift. The register 417 scans and transfers the data, and the addition converter 418
Add elements and samples as necessary. Holding is performed and an image signal is output to 419. Also, 42
0 is a similar analog with series input set to Vcc. shift. A register 421 is an addition converter similar to 418, and outputs a maximum reference signal to 422.

Also, 423 is a similar analog .423 with its serial input grounded. shift. Register 424 is a similar addition converter and outputs a minimum reference signal to 425.

By arranging similar circuits in parallel in this manner, sample and hold is not required compared to the method of generating reference signals in time series as described above, and this method is particularly effective in general imaging.

FIG. 32 is a block diagram for obtaining a video signal from the maximum or minimum reference signal and an image signal as an example. That is, by comparing the three signals, an accumulation time control circuit 426 performs accumulation time control, a differential amplifier 427 cancels out the influence of the transfer section, and the output of a temperature compensation circuit 428 of the photoelectric conversion element performs differential amplification. A video signal is obtained by performing temperature compensation in a device 429.

Note that since the temperature compensation circuit 428 of the photoelectric conversion element depends on the accumulation time, one or more photoelectric conversion elements completely shielded from light are provided in a part of the photoelectric conversion element array 416 shown in FIG. At the time of reading, the image potential corresponding to the light-shielded element is sampled and held and applied to the differential amplifier 427, thereby making it possible to compensate for the temperature of the photoelectric conversion element and the transfer section at the same time.

FIG. 33 is an example in which the accumulation time control section shown in FIG. 14 can be configured without peak hold.

That is, if the maximum standard and minimum standard are determined and obtained before outputting the image signal, 43
Divide the maximum reference given to 0 and the minimum reference given to 431 by resistors 432, 433, 434,
435 and 436 to obtain a comparison standard.

In order to obtain a time signal corresponding to the image portion of the image signal given to 437 at 438 points, FET 440 is controlled by a signal 439 corresponding to the signal shown by 133 in FIG. If the above-mentioned image signal exceeds the upper limit comparison reference value, the comparator 4
43, a HIGH signal is obtained at 444 points.

RS-FF 445 for over-state storage and RS-FF 446 for under-state storage are applied to terminal 447.
It is reset and set by the same signal as 135 in FIG.

As a result, if the image signal exceeds the upper limit standard, RS-FF445 is set and the signal reaches 448 points.
If a HIGH signal is obtained and the lower limit reference is not exceeded, the RS-FF446 will not be reset and will reach 449 points.
A HIGH signal is obtained.

Therefore, 16 in Figure 14 is given for 450 points.
For the same clock as 0, if the upper limit reference has been exceeded, the clock is obtained at 452 by the AND gate 451, and if the lower limit reference has not been exceeded,
A clock is obtained at 454 points by AND gate 453.

This causes the UP/DOWN counter 163 to count up, hold, or count down in the same way as in FIG.
The accumulation time is controlled by the prescribed value of the accumulation time.

As described in detail above, the present invention receives an image formed by an imaging optical system by arranging a plurality of photoelectric conversion elements, and performs photoelectric conversion from the photoelectric conversion elements obtained at this time. An imaging state detection method for an image that obtains a signal regarding the imaging state of each minute portion of the image based on the signal, according to the position of each pixel in the effective receiving area of the array of photoelectric conversion elements. Different weights are given to the signals regarding the imaging state of each minute part of the image in the effective receiving area, and according to this, it is possible to apply different weights to the signals regarding the imaging state of each minute part of the image in the effective receiving area. Even if there is a secondary object that is close to this object in the relative position relationship in the vertical and horizontal directions, the differential focus image of this secondary object Therefore, the noise caused by a part of the defocused image of this secondary object entering the effective receiving area of the photoelectric conversion element array can be reliably removed. As a result, regardless of the existence of such secondary objects, it is possible to always accurately detect the image formation state of the main object, and this is an extremely useful method for detecting the image formation state of this type of image. It is beneficial to

Further, the method of the present invention can image a minute portion of the image by detecting a change in illuminance between two pixels close to each other in the image based on the photoelectric conversion signal from the photoelectric conversion element, for example. In addition to obtaining a signal regarding the state, the signal is converted to a non-linear conversion circuit (in this embodiment, an illuminance change emphasis circuit 17).
When non-linear conversion is performed based on (corresponding to This can be easily implemented by using a configuration that gives different weights to the signals regarding the imaging state of each minute part of the image in the effective receiving area depending on the position of each pixel in the area.
In this case, as shown in the embodiment, for example, as the non-linear conversion circuit, a circuit configuration that utilizes the input-output square characteristic of a field effect transistor (FET) is used. By appropriately adjusting the source potential of the conversion circuit, it is possible to adopt a configuration in which the operating input level of the conversion circuit is appropriately changed. This provides the great advantage of being able to create a more suitable circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram for explaining the imaging state of the image formed by the imaging optical system, and Fig. 2 is a conceptual diagram for explaining the imaging state (focus) of the image formed by the imaging optical system. FIG. 3 is a schematic diagram illustrating an example of an arrangement of light receiving elements adopted in , and is a circuit system according to an embodiment of the present invention when the imaging state (focus) of an image is detected using the arrangement shown in the second diagram. A block diagram showing the schematic configuration of
FIG. 4 is a circuit diagram mainly showing the details of the configuration of the analog circuit system in the circuit system shown in FIG. 3, FIG. 5 is a diagram showing the input-output characteristics of a field effect transistor, and FIG. FIG. 7 is a diagram showing input-output characteristics when non-linear and absolute value conversion of an input signal is performed using a field effect transistor of FIG. The illustrative circuit diagrams, Figures 8 and 9, are
FIG. 10 is a circuit diagram showing two other specific examples of the combination of the double integration circuit and the comparator shown in FIG. A circuit diagram showing an example of a FET structure, FIG. 11 is a circuit diagram showing another specific example of the image signal change detection section shown in FIG. FIG. 13 is a block diagram showing a schematic configuration of the analog circuit system in this case. FIG. 13 is a circuit diagram showing an example of a specific example of the peak hold circuit shown in FIG.
12 is a circuit diagram showing a configuration example for controlling the charge accumulation time of the photoelectric conversion element applied to the analog circuit system shown in the figure; FIG. 15 is a part of the sequence controller in the circuit system shown in the third figure; 16th circuit diagram showing details of the main sequence circuit that performs
The figure is a timing chart showing the relationship between input and output in each circuit block of the main sequence circuit shown in Fig. 15, and Fig. 17 is the operational relationship of the analog circuit system shown in Fig. 4 under the control of the main sequence circuit shown in Fig. 15. The timing chart shown in Fig. 18 is the timing chart shown in Fig. 3.
FIG. 19 is a circuit diagram showing details of the display control unit in the illustrated circuit system, and FIG. 20 is a circuit diagram showing a specific example of the display control unit when a sounding body is used as a display means. FIG. 21 is a circuit diagram showing an example of a circuit for charge accumulation time control applied when the addition number of pixels is switchable.
FIG. 22 is a diagram showing the relationship between the number of pixel additions and the charge accumulation time set in the circuit shown in FIG.
A circuit diagram showing a specific example of a "window function" generating section applicable to the emphasis characteristic control section in the illustrated circuit system, FIG. 23 is a circuit diagram showing details of the counter section of the fifteenth illustrated transfer controller, Figure 24, Figure 25,
26, 27, and 28 are circuit diagrams showing details of the configuration of each part of the transfer controller, FIG. 29 is a schematic diagram showing the basic configuration of the image pickup tube, and FIG. Figure 31, a block diagram showing the basic configuration of an imaging device using an image pickup tube, shows the basic configuration when a reference signal for controlling the charge accumulation time of the photoelectric conversion element is obtained in parallel. 32 is a circuit diagram showing an example of the image signal compensation circuit applied to the example shown in FIG. 31, and FIG. 33 is a circuit diagram showing another specific example of the charge accumulation time control circuit. be. 1; 6...imaging optical system, 13; 13a; 13b
...Photoelectric output generator (image sensor), 3
0; 122...Photoelectric conversion element array (photoelectric conversion unit), 16... Image signal change detection unit, 17... Weighting means (emphasis circuit-nonlinear conversion circuit), 18
...Weighting control means (motion input level changing means - emphasis characteristic control section).

Claims (1)

[Scope of Claims] 1. An image formed by an imaging optical system is received by an array of a plurality of photoelectric conversion elements, and each of said images is received based on an individual photoelectric conversion signal of each photoelectric conversion element. In an imaging state detection device that detects the imaging state of an image by obtaining a signal corresponding to the imaging state in the photoelectric conversion element section, a signal whose level is determined according to the element position in the photoelectric conversion element array is formed. A signal forming circuit, the level of the sum of the signal level from the signal forming circuit and a certain level is set as a judgment level, and the outputs of the photoelectric conversion elements are sequentially inputted, and the output level of the inputted photoelectric conversion elements is set as the sum of the signal level from the signal forming circuit and a certain level. A processing circuit is provided to send a signal having a signal value corresponding to the difference between the output level of the photoelectric conversion element and the sum level as a photoelectric conversion signal to the input photoelectric conversion element only when the output level of the photoelectric conversion element exceeds the sum level, and the output level of each photoelectric conversion element is When the image is input to the processing circuit, the signal level from the signal forming circuit is varied depending on the position of the photoelectric conversion element input to the processing circuit in the photoelectric conversion element array. Imaging state detection device.