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JPS6210449B2 - - Google Patents
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JPS6210449B2 - - Google Patents

Info

Publication number
JPS6210449B2
JPS6210449B2 JP53025647A JP2564778A JPS6210449B2 JP S6210449 B2 JPS6210449 B2 JP S6210449B2 JP 53025647 A JP53025647 A JP 53025647A JP 2564778 A JP2564778 A JP 2564778A JP S6210449 B2 JPS6210449 B2 JP S6210449B2
Authority
JP
Japan
Prior art keywords
electrode
input
output
electrodes
interdigital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53025647A
Other languages
Japanese (ja)
Other versions
JPS54118159A (en
Inventor
Koji Toda
Yoshinari Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2564778A priority Critical patent/JPS54118159A/en
Publication of JPS54118159A publication Critical patent/JPS54118159A/en
Publication of JPS6210449B2 publication Critical patent/JPS6210449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

【発明の詳細な説明】 本発明は電気信号を超音波に変換して信号処理
を行う超音波論理素子に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultrasonic logic element that converts electrical signals into ultrasonic waves and performs signal processing.

最近、信号処理素子として多値論理素子の出現
が待たれているが特筆すべきデバイスとして評価
に耐えうるものがない。
Recently, the appearance of multivalued logic elements as signal processing elements has been awaited, but there is no such device that can be evaluated as a noteworthy device.

本発明は変換効率が高く、電気的なノイズ特性
に優れ、縦続接続が容易な3値論理素子を目的と
している。
The object of the present invention is to provide a three-value logic element with high conversion efficiency, excellent electrical noise characteristics, and easy cascade connection.

以下、図面に従つて本発明を説明する。 The present invention will be explained below with reference to the drawings.

第1図は本発明の論理素子の電極構成の一例を
示す平面図であり、裏面の電極は点線で示してい
る。
FIG. 1 is a plan view showing an example of the electrode configuration of a logic element according to the present invention, and the electrodes on the back surface are shown by dotted lines.

すなわち、入力側すだれ状電極A及びBが薄板
状圧電体の一方の面にインターデイジタルに形成
されて電極対を構成している。前記電極対に対応
する如く前記圧電体の面に面電極Oが形成されて
いる。前記圧電体には入力側と同様な構成で出力
側すだれ状電極A′及びB′、出力側面電極O′が形
成されている。そして、入力側面電極O及び出力
側面電極O′は接地され、出力側すだれ状電極
A′,B′は面電極O′間と各々出力端子を構成して
いる。
That is, input-side interdigital electrodes A and B are interdigitally formed on one surface of a thin piezoelectric material to constitute an electrode pair. A surface electrode O is formed on the surface of the piezoelectric body so as to correspond to the electrode pair. The output side interdigital electrodes A' and B' and the output side electrode O' are formed on the piezoelectric body in the same configuration as the input side. The input side electrode O and the output side electrode O' are grounded, and the output side interdigital electrode
A′ and B′ constitute output terminals between the plane electrodes O′, respectively.

第2図は本発明の信号処理を示すブロツク図で
ある。
FIG. 2 is a block diagram showing signal processing of the present invention.

すなわち、すだれ状電極Aと面電極O間に基準
入力端子として基準信号Sが常に入力されてい
る。またすだれ状電極Bと面電極O間は入力端子
として入力信号S及びこれと180゜の位相差を有
する入力信号そして零入力のいずれかが印加さ
れる。出力側はすだれ状電極A′,B′と面電極
O′間を各々出力端子となしている。この場合入
力端子に入力信号Sが入力されると出力端子には
零が出力され、入力信号が入力されると出力端
子には2Sが、入力信号が零入力の場合はSが出
力される。
That is, the reference signal S is always input between the interdigital electrode A and the surface electrode O as a reference input terminal. Further, between the interdigital electrode B and the surface electrode O, either an input signal S, an input signal having a phase difference of 180 degrees from the input signal S, or a zero input is applied as an input terminal. On the output side, there are interdigital electrodes A′, B′ and a surface electrode.
The terminals between O′ serve as output terminals. In this case, when the input signal S is input to the input terminal, zero is output to the output terminal, when the input signal is input, 2S is output to the output terminal, and when the input signal is zero input, S is output.

第1図に示した構成の素子を、圧電体として長
さ40mm、巾20mm、厚さ100μmの東京電気化学工
業KK製の圧電磁器91A材(厚さ方向に分極処
理)を用い、すだれ状電極を電極指巾、電極間隔
ともに75μmとしてAlの蒸着によつて形成して
作成した。そして周波数12.8MHzにおける出力
電圧を測定したところ0:3:5の出力比という
結果を得た。すなわち入力信号S,O,に対し
て出力信号は0:S:2Sの3値が得られる3値
論理素子を構成している。
The element having the configuration shown in Fig. 1 was constructed using a piezoelectric ceramic material 91A made by Tokyo Denki Kagaku Kogyo KK (polarized in the thickness direction) with a length of 40 mm, a width of 20 mm, and a thickness of 100 μm as the piezoelectric body, and a blind-shaped electrode was used. The electrode finger width and electrode spacing were both 75 μm, and the electrode was formed by vapor deposition of Al. When the output voltage was measured at a frequency of 12.8MHz, an output ratio of 0:3:5 was obtained. In other words, it constitutes a three-value logic element that can obtain output signals of three values 0:S:2S for input signals S and O.

また、本素子を縦続接続する場合には、入・出
力すだれ状電極間距離を使用波長の整数倍とする
ことによつて、入力信号と出力信号の位相を合致
させることが可能であり、好都合な結果をもたら
す。
In addition, when this device is connected in series, it is possible to match the phases of the input signal and output signal by making the distance between the input and output interdigital electrodes an integral multiple of the wavelength used, which is convenient. results.

なお、超音波トランスデユーサとしてはここで
は薄板状圧電体(その厚みはこの基板を伝搬する
音波の波長入以下である)を基板として用いてラ
ム波を利用し良好な結果を得ているが、例えば
CdS、ZnO等の圧電性薄膜を溶融石英、ガラス等
の非圧電性基板上に設ける場合は表面弾性波を用
いることになり、この場合も同様の効果を奏す
る。
In addition, as an ultrasonic transducer, a thin piezoelectric material (the thickness of which is less than the wavelength of the sound wave propagating through this substrate) is used as the substrate, and Lamb waves are utilized, and good results have been obtained. ,for example
When a piezoelectric thin film such as CdS or ZnO is provided on a non-piezoelectric substrate such as fused silica or glass, surface acoustic waves are used, and the same effect can be achieved in this case as well.

以上述べた如く、本発明は薄板状圧電体の一方
の面にインターデイジタルに構成したすだれ状電
極対を2組形成し、前記圧電体の他方の面に前記
電極対に対応する如く面電極をそれぞれ設け、前
記電極対の他方及びこれに対応する面電極を出力
側となし、入力側のすだれ状電極の一方を基準信
号入力端となし、入力側のすだれ状電極の他方を
前記基準信号と同相、逆相、及び零入力をもつて
入力信号とする入力端となし、出力側のすだれ状
電極と面電極間をそれぞれ出力端となしたことを
特徴とする超音波論理素子であつて、変動効率が
優れているとともに、多値論理の機能を有し、フ
イルタ機能をもつことから雑音に強く、さらに製
造法が容易である等優れた発明である。
As described above, the present invention forms two pairs of interdigitated interdigitated electrodes on one surface of a thin piezoelectric material, and provides surface electrodes corresponding to the electrode pairs on the other surface of the piezoelectric material. The other of the electrode pair and the corresponding surface electrode are used as the output side, one of the interdigitated electrodes on the input side is used as a reference signal input end, and the other of the interdigitated electrodes on the input side is used as the reference signal input terminal. An ultrasonic logic element characterized by having in-phase, reverse-phase, and zero inputs as input ends for receiving input signals, and output ends between the interdigital electrode and the surface electrode on the output side, It is an excellent invention as it has excellent fluctuation efficiency, has a multi-value logic function, is resistant to noise because it has a filter function, and is easy to manufacture.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の論理素子のトランスデユー
サの実施例を示す平面図である。第2図は本発明
の論理素子のブロツク図である。
FIG. 1 is a plan view showing an embodiment of a transducer of a logic element according to the present invention. FIG. 2 is a block diagram of the logic element of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 伝搬する波がラム波である薄板状圧電体の一
方の面にインターデイジタルに構成したすだれ状
電極対を2組形成し、前記圧電体の他方の面に前
記電極対に対応する如く面電極をそれぞれ設け、
前記電極対の一方及びこれに対応する面電極を入
力側、前記電極対の他方及びこれに対応する面電
極を出力側となし、入力側のすだれ状電極の一方
と面電極間を基準信号入力端となし、入力側のす
だれ状電極の他方と面電極間を前記基準信号と同
相、逆相、及び零入力をもつて入力信号とする入
力端となし、出力側のすだれ状電極と対応面電極
間をそれぞれ出力端となしたことを特徴とする超
音波論理素子。
1. Two pairs of interdigitated interdigitated electrodes are formed on one surface of a thin plate piezoelectric material whose propagating waves are Lamb waves, and a surface electrode is provided on the other surface of the piezoelectric material corresponding to the electrode pairs. are established respectively,
One of the electrode pairs and the corresponding surface electrode are used as the input side, the other of the electrode pair and the corresponding surface electrode are used as the output side, and a reference signal is input between one of the interdigitated electrodes on the input side and the surface electrode. The other side of the interdigital electrode on the input side and the surface electrode are used as an input signal with the same phase, opposite phase, and zero input as the reference signal, and the interdigital electrode on the output side and the corresponding surface. An ultrasonic logic element characterized by having output ends between the electrodes.
JP2564778A 1978-03-07 1978-03-07 Ultrasonic logic element Granted JPS54118159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2564778A JPS54118159A (en) 1978-03-07 1978-03-07 Ultrasonic logic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2564778A JPS54118159A (en) 1978-03-07 1978-03-07 Ultrasonic logic element

Publications (2)

Publication Number Publication Date
JPS54118159A JPS54118159A (en) 1979-09-13
JPS6210449B2 true JPS6210449B2 (en) 1987-03-06

Family

ID=12171611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2564778A Granted JPS54118159A (en) 1978-03-07 1978-03-07 Ultrasonic logic element

Country Status (1)

Country Link
JP (1) JPS54118159A (en)

Also Published As

Publication number Publication date
JPS54118159A (en) 1979-09-13

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