JPS62110367A - Field decision circuit for television signal - Google Patents

Abstract

PURPOSE:To reduce the number of circuit elements by generating two kinds of clock signals different in pulse width from the front edge of horizontal synchronizing signals, detecting phase difference at the time of changing of even number fields and odd number fields utilizing the signals and outputting a judging signal. CONSTITUTION:Monostable multivibrators 2a, 2b generate two kinds of clock signals, one is 1/2H<tw<1H in pulse width (tw) and another is 1/10H<tw<1/2H, from the front edge of horizontal synchronizing signals (period 1H) respectively. These signals and inversion signals of above-mentioned horizontal synchronizing signals are inputted to a logic circuit consisting of D type flip-flop circuits 3a, 3b, 3c. The logic circuit detects phase deviation of 1/2H of vertical synchronizing signals. Thus, field signals (E/O) polarity of which is inverted at the change of even number fields and odd number fields are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field determination circuit that detects an even field and an odd field from a synchronization signal of a television signal employing an interlaced system.

(Prior Art) In an image processing device such as a video camera, captured image signals are digitized and written into memory.

At this time, since the television signal uses an interlaced system, it is necessary to switch memory addresses between even and odd fields. Therefore, a field is required to detect the even and odd fields from the synchronization signal of the television signal. A judgment circuit is required.

A conventional field determination circuit is shown in FIG. 3, and a timing chart of this field determination circuit is shown in FIG.

This field determination circuit counts the equalization pulses of the horizontal synchronization signal included in the vertical synchronization signal and generates a field determination signal at a position where the phase level can be determined.
Using a retrigger-mono staple multi-by-break 10 with a pulse width t set to 1/2H<tw<IH,
The vertical synchronization signal (
V, ) is generated, and a count pulse (H3), which is a determination element for field determination, is output from the monostable multi-by-break 12, and when this output is in the state of "5" in binary (QA = QC = 1) In binary
A pulse (ES) is generated from the counter 13 to be applied to the field determination flip-flop 14 to obtain a field determination signal (Elo).

(Problems to be Solved by the Invention) However, the field determination circuit using this type of binary counter 13 has a large number of circuit elements and uses a large number of ICs. Furthermore, when integrated into an IC, there are problems such as an increase in the proportion of elements used within the limited number of elements.

In view of this point, it is an object of the present invention to provide a field determination circuit with a reduced number of circuit elements.

(Means for solving the problem) The present invention provides a horizontal synchronizing signal (period 1
]) from the leading edge of the pulse width (tw) is 1/2H<tl,
Two types of clock signals are generated: l < 1) (and 1/10H < t, < 1/2H), and a logic circuit detects a 1/2H phase shift of the vertical synchronization signal based on these clock signals. It is constructed.

The two types of clock signals are generated by, for example, a monostable multi-by-break, and the logic circuit is generated by, for example, three
It is constructed using two D-type flip-flops.

(Function) Two types of clock signals with different pulse widths are generated from the leading edge of the horizontal synchronizing signal of the television signal, and these clock signals are used to adjust the phase difference when switching between the even and odd fields. Detection and output field judgment signal.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a television signal field determination circuit according to the present invention, and FIG. 2 is a timing chart. Note that in the following explanation, the period of the horizontal synchronization signal is expressed as IH.

In FIG. 1, the field determination circuit is composed of a group of logic gates that output a field determination signal (Elo) based on a signal (SYNC*) obtained by separating the synchronization signal component from a television signal.

The 5YNC* signal is input to two mono multi-by-breaks 2a and 2b via a buffer 1. These mono multi-by-breaks 2a and 2b generate a constant pulse width in synchronization with the falling edge of the horizontal synchronization signal, and the pulse width tWI generated by the first mono-multi high break 2a is 1/2H< t, ,<IH, and the pulse width tW2 at which the second (7) mo/7/L/chibai break 2b occurs is set to 1/IOH<t, □<1/2H. These mono multi-by break 2a, 2b
A type that does not require a retrigger is used.

Note that in this example, the pulse width t. l+tW2 is set to 45 μs and 20 μs, respectively.

Then, the Q output of the first mono multivibrator 2a is input as a signal SY to the input terminal (D) of the first D type flip-flop 3a, and the 100 output of the second mono multivibrator 2b is input as SY2. It is input to the clock terminal (CK) of the D-type flip-flop 3b of No. 2.

On the other hand, the 5YNC* signal is converted by the inverter 4 into a 5YN(, It is input to the input terminal (D) of the flip-flop 3b.

Furthermore, the Q output of the first flip-flop 3a is
The D* signal is input to the input terminal (D) of the third D-type flip-flop 3C;
A VSYNC signal, which is the Q output of the second D-type flip-flop 3b, is input to the clock terminal (CK) of C.

Therefore, the three D-type flip-flops 3a, 3b
, 3c, the SY,
By using the phase difference between the signal, 5YNC* signal, sy, and the signal, a field determination signal (Elo) whose polarity is reversed at the switching point between the even field and the odd field is generated as shown in Fig. 2 (al, (bl). generated.

(Effects of the Invention) As described above, the field determination circuit of the present invention can reduce the number of circuit elements and is a circuit system suitable for integration into an IC.

In addition, PLA (Programmable Lo
gic Array).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a television signal field determination circuit according to the present invention, and FIG. 2(a). (b) is a timing chart showing the operation of the same field determination circuit, FIG. 3 is a circuit diagram showing a conventional example, and FIG.
, (bl is a timing chart showing the operation of the conventional example. 2a, 2b... Mono multi-by-break 3a, 3b,
3c...D type flip-flop Figure 7

Claims (1)

[Claims] 1) Two types of clock signals with pulse widths (t_w) of 1/2H<t_w<1H and 1/10H<t_w<1/2H are generated from the leading edge of the horizontal synchronization signal (period 1H) of the television signal, A television signal field determination circuit comprising a logic circuit that detects a 1/2H phase shift of a vertical synchronization signal based on these clock signals.