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JPS6211497B2 - - Google Patents
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JPS6211497B2 - - Google Patents

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Publication number
JPS6211497B2
JPS6211497B2 JP6713477A JP6713477A JPS6211497B2 JP S6211497 B2 JPS6211497 B2 JP S6211497B2 JP 6713477 A JP6713477 A JP 6713477A JP 6713477 A JP6713477 A JP 6713477A JP S6211497 B2 JPS6211497 B2 JP S6211497B2
Authority
JP
Japan
Prior art keywords
strained layer
layer
silicon
depth
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6713477A
Other languages
Japanese (ja)
Other versions
JPS54985A (en
Inventor
Takeshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP6713477A priority Critical patent/JPS54985A/en
Publication of JPS54985A publication Critical patent/JPS54985A/en
Publication of JPS6211497B2 publication Critical patent/JPS6211497B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は、半導体装置の製造方法、特に半導体
基板の改良方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for improving a semiconductor substrate.

一般に、半導体装置の製造基板としてはシリコ
ンが用いられ、写真蝕刻技術や選択拡散法を用い
不純物をシリコン基板に1回又は数回拡散させる
事で部分的にトランジスター、ダイオードあるい
は拡散抵抗層等が形成されている。この場合、問
題になるのは、不純物拡散前工程や拡散中に拡散
不純物以外の不純物、例えば鉄や銅の様な重金属
がわずかでもシリコン基板内や拡散層中に入り込
むとそれらがシリコン結晶中の欠陥部分などに蓄
積される。
Generally, silicon is used as a manufacturing substrate for semiconductor devices, and by diffusing impurities into the silicon substrate once or several times using photolithography or selective diffusion, transistors, diodes, or diffused resistance layers are formed partially. has been done. In this case, the problem is that if even a small amount of impurities other than the diffused impurity, such as heavy metals such as iron or copper, enter the silicon substrate or diffusion layer during the pre-diffusion process or during the diffusion, they will be absorbed into the silicon crystal. Accumulates in defective areas.

この様な拡散で形成されるP−N接合部に電圧
を加えた場合、重金属の蓄積がリーク電流発生の
原因となつていた。このリーク発生を防ぐ為に、
従来は拡散工程の一部でシリコンの能動素子形成
面あるいは、反対側のシリコン面に燐の不純物を
拡散させる事でシリコン基板中に含まれる重金属
類をゲツタリング(吸い出し)していた。
When a voltage is applied to the P-N junction formed by such diffusion, the accumulation of heavy metals causes leakage current. In order to prevent this leak from occurring,
Conventionally, as part of the diffusion process, heavy metals contained in the silicon substrate were gettered (sucked out) by diffusing phosphorous impurities into the silicon surface where active elements are formed or the opposite silicon surface.

しかしながら、燐を拡散させる事で重金属をゲ
ツタリングする方法は、多量の金属の吸い出しや
大きな接合層リークに対しては効果があるが、超
微量の金属不純物などによるP−N接合の微小リ
ークの防止に対しては大きな効果はなかつた。
However, the method of gettering heavy metals by diffusing phosphorus is effective against sucking out large amounts of metal and large leaks in the bonding layer, but it prevents micro leaks in the P-N junction due to ultra-trace metal impurities. There was no significant effect on.

本発明は、上記欠点を除去し、半導体基板内か
ら微量の重金属を取り除き、P−N接合リーク電
流を極めて小さくし、信頼性の高い半導体装置を
製造する方法を提供するものである。
The present invention eliminates the above-mentioned drawbacks, removes trace amounts of heavy metals from the semiconductor substrate, extremely reduces the PN junction leakage current, and provides a method for manufacturing a highly reliable semiconductor device.

本発明の半導体装置の製造方法は、半導体基板
の能動素子形成面と反対側の面に、該半導体より
も硬度の大きい固型粒子を当てて該半導体基板面
に歪層を形成する工程と、前記歪層の一部もしく
は全部に燐を拡散させる工程とを含むことを特徴
とする。
The method for manufacturing a semiconductor device of the present invention includes a step of applying solid particles having a harder hardness than the semiconductor to the surface of the semiconductor substrate opposite to the active element forming surface to form a strained layer on the semiconductor substrate surface; The method is characterized in that it includes a step of diffusing phosphorus into part or all of the strained layer.

本発明によれば、P−N接合リーク電流が極め
て小さく、信頼性の高い半導体装置が得られるの
で、例えば、従来半導体メモリー用の集積回路等
で、問題となつていたP−N接合の微小リークに
依るメモリー情報の記憶時間が短くなる問題等も
解決できる。
According to the present invention, a highly reliable semiconductor device with extremely small P-N junction leakage current can be obtained. This also solves the problem of shortening the storage time of memory information due to leaks.

本発明を実施例により説明する。 The present invention will be explained by examples.

第1図乃至第3図は本発明をダイオードの製造
に実施した場合の主な工程における断面図であ
る。容器5の中に石英の固型粒子2を水と混ぜた
ものを入れ、ポンプ4で加圧してノズル3を通し
てP型シリコン基板1上に当てる(第1図)。シ
リコン基板1の表面上に粒子が当たる事により機
械的な歪が入り、歪層6が形成される(第2
図)。
FIGS. 1 to 3 are cross-sectional views of the main steps when the present invention is applied to the manufacture of diodes. A mixture of solid quartz particles 2 and water is placed in a container 5, pressurized by a pump 4, and applied onto a P-type silicon substrate 1 through a nozzle 3 (FIG. 1). When particles hit the surface of the silicon substrate 1, mechanical strain is introduced, forming a strained layer 6 (second layer).
figure).

この様な方法でポンプの圧力、粒子の径や硬
度、また、粒子を基板に当てる時間を適当に選ぶ
と、シリコン基板上の加工歪は、一定の深さが任
意に出来る事になる。特に、歪層の効果を大きく
する為には、深さ方向の制御は重要である。歪層
6の深さは浅過ぎても効果は少く、深過ぎても逆
効果になり、0.2〜10μm程度の深さが望まし
い。
By appropriately selecting the pump pressure, the diameter and hardness of the particles, and the time during which the particles are exposed to the substrate using this method, processing strain on the silicon substrate can be created to any desired depth. In particular, control in the depth direction is important in order to increase the effect of the strained layer. If the depth of the strained layer 6 is too shallow, the effect will be small, and if it is too deep, it will have the opposite effect, so a depth of about 0.2 to 10 μm is desirable.

ここで加速する粒子の硬度は、シリコン基板に
比べ、大きい方が望ましく、ここではシリコンに
ぶつつける粒子は、石英を選んだが、アルミナや
炭化シリコンでも良い。
It is preferable that the hardness of the particles accelerated here is greater than that of the silicon substrate, and here the particles that collide with the silicon are made of quartz, but alumina or silicon carbide may also be used.

一般に、半導体装置に使用するシリコン基板
は、その結晶性を良くし、できるかぎり結晶欠陥
を少くする方法をとつている。例えば、表面結晶
欠陥数で言うと、数個〜数千個/cm2である。これ
に対し、本方法で作つた歪層は、結晶欠陥数は数
万から数千万個/cm2と結晶欠陥数は、1桁から5
桁ほど多い。従つて、ここで言う歪層とは、結晶
欠陥密度が104〜108個/cm2と多いシリコン層と言
つてよい。
In general, silicon substrates used in semiconductor devices are made to have good crystallinity and have as few crystal defects as possible. For example, the number of surface crystal defects is from several to several thousand defects/cm 2 . On the other hand, in the strained layer made by this method, the number of crystal defects ranges from tens of thousands to tens of millions/ cm2 , and the number of crystal defects ranges from one digit to five.
There are so many digits. Therefore, the strained layer referred to here can be said to be a silicon layer with a high crystal defect density of 10 4 to 10 8 /cm 2 .

ここで言う歪層深さの測定には、シリコンを
1100℃程度の酸化雰囲気中で2時間程度熱処理を
した後に、シリコンを厚さ方向に劈開し、公知の
ジルトルエツチング液(100mlの水に50gの無水
クロム酸を溶かし100mlのフツ酸との混液、詳細
はE.Sirtl、A.Adler:Z.Metallkde.、Vol.52
(1961)P.529を参照)又はダツシユエツチング液
(10mlのフツ酸と30mlの硝酸と120mlの酢酸との混
液、詳細はW.C.Dash:J.Appl.Phys.、Vol.27
(1958)P.705を参照)等で5〜15分間エツチング
すると、シリコン転位がエツチングされ結晶欠陥
が現われる。結晶欠陥密度は104〜108個/cm2であ
り、その深さを顕微鏡を使つて測微計で測定すれ
ば歪層の深さが測定できる。
To measure the strained layer depth mentioned here, silicon is used.
After heat treatment for about 2 hours in an oxidizing atmosphere at about 1100°C, the silicone was cleaved in the thickness direction and treated with a well-known dilute etching solution (a mixture of 50g of chromic anhydride dissolved in 100ml of water and 100ml of hydrofluoric acid). , Details in E. Sirtl, A. Adler: Z. Metallkde., Vol.52
(1961) p. 529) or dossier etching solution (a mixture of 10 ml of hydrofluoric acid, 30 ml of nitric acid, and 120 ml of acetic acid, details: WCDash: J.Appl.Phys., Vol. 27)
(1958) (see page 705) for 5 to 15 minutes, silicon dislocations are etched and crystal defects appear. The crystal defect density is 10 4 to 10 8 /cm 2 , and the depth of the strained layer can be measured by measuring the depth with a micrometer using a microscope.

次に、この歪層を持つたP型シリコン基板1の
歪層6の存在する面と反対側の面にシリコン酸化
膜7を設け、選択拡散法を用いてリンの拡散層8
を形成する。この時、同時に裏面の歪層6にもリ
ン拡散層9が形成されたことになる。このシリコ
ン歪層部分へのリンの拡散は1000℃以上の高温で
時間が長い程効果が大きいので、リン拡散層8の
形成とは別の工程で拡散しても良い。また、N型
基板へホウ素の拡散層を形成する場合には、歪層
6へ別にリンを拡散させなければならない。その
後通常の方法によりアルミニウムの配線電極10
を形成する(第3図)。
Next, a silicon oxide film 7 is provided on the side opposite to the side where the strained layer 6 is present on the P-type silicon substrate 1 having this strained layer, and a phosphorus diffusion layer 8 is formed using a selective diffusion method.
form. At this time, the phosphorus diffusion layer 9 was also formed on the strained layer 6 on the back surface at the same time. The diffusion of phosphorus into the silicon strained layer portion becomes more effective as the time increases at a high temperature of 1000° C. or higher, so it may be diffused in a separate process from the formation of the phosphorus diffusion layer 8. Further, when forming a boron diffusion layer on an N-type substrate, phosphorus must be separately diffused into the strained layer 6. After that, the wiring electrode 10 of aluminum is formed by the usual method.
(Figure 3).

第4図は、本発明によつて製造したダイオード
の歪層深さと逆リーク電流との関係を示す特性図
である。
FIG. 4 is a characteristic diagram showing the relationship between strain layer depth and reverse leakage current of a diode manufactured according to the present invention.

ここに用いたダイオードは、拡散層深さが2μ
m幅10μm、長さ20mmの大きさである。歪層がな
いもの(第4図左端の〇印)に比べ、歪層を0.1
〜10μmの深さに形成したダイオードはリーク電
流が小さいことがわかる。特に歪層の深さが1〜
5μm程度のときに効果が大きい事がわかつた。
The diode used here has a diffusion layer depth of 2μ.
It has a width of 10 μm and a length of 20 mm. Compared to the one without a strained layer (marked with a circle on the left end of Figure 4), the strained layer is reduced by 0.1.
It can be seen that the diode formed at a depth of ~10 μm has a small leakage current. In particular, the depth of the strained layer is 1~
It was found that the effect was large when the thickness was about 5 μm.

この他に本方法を使つてNチヤンネルのMOS
メモリー集積回路を製作したところ、リーク電流
が減少する事で、ホールド時間が倍以上に長くな
るという顕著な効果が認められ、信頼性の高い半
導体装置を得る事が出来。またこの裏面歪を有し
た半導体装置を製品として組立てる場合に、裏面
歪層を取り去つても前記の効果は変らない事もわ
かつた。
In addition, using this method, N-channel MOS
When we fabricated a memory integrated circuit, we found that by reducing leakage current, the hold time was more than doubled, making it possible to obtain a highly reliable semiconductor device. It was also found that when a semiconductor device having back surface strain is assembled as a product, the above-mentioned effect does not change even if the back surface strain layer is removed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明をダイオード製造に
実施した場合の主な工程における断面図、第4図
は本発明によつて製造したダイオードの歪層深さ
と逆リーク電流との関係を示す特性図である。 1……P型シリコン基板、2……石英粒子、3
……ノズル、4……ポンプ、5……容器、6……
歪層、7……シリコン酸化膜、8……N型拡散
層、9……リン拡散層、10……配線電極。
Figures 1 to 3 are cross-sectional views of the main steps when the present invention is applied to diode manufacturing, and Figure 4 shows the relationship between the strain layer depth and reverse leakage current of the diode manufactured according to the present invention. It is a characteristic diagram. 1... P-type silicon substrate, 2... Quartz particles, 3
... Nozzle, 4 ... Pump, 5 ... Container, 6 ...
Strained layer, 7... Silicon oxide film, 8... N-type diffusion layer, 9... Phosphorus diffusion layer, 10... Wiring electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の能動素子形成面とは異なる面
に、該半導体基板よりも硬度の大きい固体粒子を
ぶつつけて該導体基板の前記異なる面に深さ0.2
〜10μmの歪層を形成する工程と、前記歪層を有
する面の一部又は全部に燐を拡散させる工程とを
含むことを特徴とする半導体装置の製造方法。
1. Solid particles having a harder hardness than the semiconductor substrate are bombarded onto a surface of the semiconductor substrate different from the active element forming surface to a depth of 0.2 to the different surface of the conductor substrate.
A method for manufacturing a semiconductor device, comprising the steps of forming a strained layer with a thickness of ~10 μm, and diffusing phosphorus into part or all of a surface having the strained layer.
JP6713477A 1977-06-06 1977-06-06 Method of producing semiconductor Granted JPS54985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6713477A JPS54985A (en) 1977-06-06 1977-06-06 Method of producing semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6713477A JPS54985A (en) 1977-06-06 1977-06-06 Method of producing semiconductor

Publications (2)

Publication Number Publication Date
JPS54985A JPS54985A (en) 1979-01-06
JPS6211497B2 true JPS6211497B2 (en) 1987-03-12

Family

ID=13336112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6713477A Granted JPS54985A (en) 1977-06-06 1977-06-06 Method of producing semiconductor

Country Status (1)

Country Link
JP (1) JPS54985A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57122868U (en) * 1981-01-27 1982-07-30
JPS58153337A (en) * 1982-03-08 1983-09-12 Nec Corp Manufacture of semiconductor device
JPS60227631A (en) * 1984-04-25 1985-11-12 Masatoshi Muraoka Method of packaging of krill
JPS60251838A (en) * 1984-05-26 1985-12-12 Masatoshi Muraoka Packaging of krill

Also Published As

Publication number Publication date
JPS54985A (en) 1979-01-06

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